1 # Copyright (c) 2005-2007 The Regents of The University of Michigan
4 # Redistribution and use in source and binary forms, with or without
5 # modification, are permitted provided that the following conditions are
6 # met: redistributions of source code must retain the above copyright
7 # notice, this list of conditions and the following disclaimer;
8 # redistributions in binary form must reproduce the above copyright
9 # notice, this list of conditions and the following disclaimer in the
10 # documentation and/or other materials provided with the distribution;
11 # neither the name of the copyright holders nor the names of its
12 # contributors may be used to endorse or promote products derived from
13 # this software without specific prior written permission.
15 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
18 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
19 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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25 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 # Authors: Nathan Binkert
29 from m5
.params
import *
30 from MemObject
import MemObject
32 class Prefetch(Enum
): vals
= ['none', 'tagged', 'stride', 'ghb']
34 class BaseCache(MemObject
):
36 adaptive_compression
= Param
.Bool(False,
37 "Use an adaptive compression scheme")
38 assoc
= Param
.Int("associativity")
39 block_size
= Param
.Int("block size in bytes")
40 latency
= Param
.Latency("Latency")
41 compressed_bus
= Param
.Bool(False,
42 "This cache connects to a compressed memory")
43 compression_latency
= Param
.Latency('0ns',
44 "Latency in cycles of compression algorithm")
45 hash_delay
= Param
.Int(1, "time in cycles of hash access")
46 lifo
= Param
.Bool(False,
47 "whether this NIC partition should use LIFO repl. policy")
48 max_miss_count
= Param
.Counter(0,
49 "number of misses to handle before calling exit")
50 mshrs
= Param
.Int("number of MSHRs (max outstanding requests)")
51 prioritizeRequests
= Param
.Bool(False,
52 "always service demand misses first")
53 protocol
= Param
.CoherenceProtocol(NULL
, "coherence protocol to use")
54 repl
= Param
.Repl(NULL
, "replacement policy")
55 size
= Param
.MemorySize("capacity in bytes")
56 split
= Param
.Bool(False, "whether or not this cache is split")
57 split_size
= Param
.Int(0,
58 "How many ways of the cache belong to CPU/LRU partition")
59 store_compressed
= Param
.Bool(False,
60 "Store compressed data in the cache")
61 subblock_size
= Param
.Int(0,
62 "Size of subblock in IIC used for compression")
63 tgts_per_mshr
= Param
.Int("max number of accesses per MSHR")
64 trace_addr
= Param
.Addr(0, "address to trace")
65 two_queue
= Param
.Bool(False,
66 "whether the lifo should have two queue replacement")
67 write_buffers
= Param
.Int(8, "number of write buffers")
68 prefetch_miss
= Param
.Bool(False,
69 "wheter you are using the hardware prefetcher from Miss stream")
70 prefetch_access
= Param
.Bool(False,
71 "wheter you are using the hardware prefetcher from Access stream")
72 prefetcher_size
= Param
.Int(100,
73 "Number of entries in the harware prefetch queue")
74 prefetch_past_page
= Param
.Bool(False,
75 "Allow prefetches to cross virtual page boundaries")
76 prefetch_serial_squash
= Param
.Bool(False,
77 "Squash prefetches with a later time on a subsequent miss")
78 prefetch_degree
= Param
.Int(1,
79 "Degree of the prefetch depth")
80 prefetch_latency
= Param
.Tick(10,
81 "Latency of the prefetcher")
82 prefetch_policy
= Param
.Prefetch('none',
83 "Type of prefetcher to use")
84 prefetch_cache_check_push
= Param
.Bool(True,
85 "Check if in cash on push or pop of prefetch queue")
86 prefetch_use_cpu_id
= Param
.Bool(True,
87 "Use the CPU ID to seperate calculations of prefetches")
88 prefetch_data_accesses_only
= Param
.Bool(False,
89 "Only prefetch on data not on instruction accesses")
90 cpu_side
= Port("Port on side closer to CPU")
91 mem_side
= Port("Port on side closer to MEM")