0a590c2ca5d4a0b9aeeee2b2cc7c2112a6aa5b4e
1 # Copyright (c) 2012-2013, 2015, 2018 ARM Limited
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13 # Copyright (c) 2005-2007 The Regents of The University of Michigan
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39 # Authors: Nathan Binkert
42 from m5
.params
import *
43 from m5
.proxy
import *
44 from m5
.SimObject
import SimObject
46 from m5
.objects
.MemObject
import MemObject
47 from m5
.objects
.Prefetcher
import BasePrefetcher
48 from m5
.objects
.ReplacementPolicies
import *
49 from m5
.objects
.Tags
import *
52 # Enum for cache clusivity, currently mostly inclusive or mostly
54 class Clusivity(Enum
): vals
= ['mostly_incl', 'mostly_excl']
56 class WriteAllocator(SimObject
):
57 type = 'WriteAllocator'
58 cxx_header
= "mem/cache/cache.hh"
60 # Control the limits for when the cache introduces extra delays to
61 # allow whole-line write coalescing, and eventually switches to a
62 # write-no-allocate policy.
63 coalesce_limit
= Param
.Unsigned(2, "Consecutive lines written before "
64 "delaying for coalescing")
65 no_allocate_limit
= Param
.Unsigned(12, "Consecutive lines written before"
66 " skipping allocation")
68 delay_threshold
= Param
.Unsigned(8, "Number of delay quanta imposed on an "
69 "MSHR with write requests to allow for "
72 block_size
= Param
.Int(Parent
.cache_line_size
, "block size in bytes")
75 class BaseCache(MemObject
):
78 cxx_header
= "mem/cache/base.hh"
80 size
= Param
.MemorySize("Capacity")
81 assoc
= Param
.Unsigned("Associativity")
83 tag_latency
= Param
.Cycles("Tag lookup latency")
84 data_latency
= Param
.Cycles("Data access latency")
85 response_latency
= Param
.Cycles("Latency for the return path on a miss");
87 warmup_percentage
= Param
.Percent(0,
88 "Percentage of tags to be touched to warm up the cache")
90 max_miss_count
= Param
.Counter(0,
91 "Number of misses to handle before calling exit")
93 mshrs
= Param
.Unsigned("Number of MSHRs (max outstanding requests)")
94 demand_mshr_reserve
= Param
.Unsigned(1, "MSHRs reserved for demand access")
95 tgts_per_mshr
= Param
.Unsigned("Max number of accesses per MSHR")
96 write_buffers
= Param
.Unsigned(8, "Number of write buffers")
98 is_read_only
= Param
.Bool(False, "Is this cache read only (e.g. inst)")
100 prefetcher
= Param
.BasePrefetcher(NULL
,"Prefetcher attached to cache")
101 prefetch_on_access
= Param
.Bool(False,
102 "Notify the hardware prefetcher on every access (not just misses)")
104 tags
= Param
.BaseTags(BaseSetAssoc(), "Tag store")
105 replacement_policy
= Param
.BaseReplacementPolicy(LRURP(),
106 "Replacement policy")
108 sequential_access
= Param
.Bool(False,
109 "Whether to access tags and data sequentially")
111 cpu_side
= SlavePort("Upstream port closer to the CPU and/or device")
112 mem_side
= MasterPort("Downstream port closer to memory")
114 addr_ranges
= VectorParam
.AddrRange([AllMemory
],
115 "Address range for the CPU-side port (to allow striping)")
117 system
= Param
.System(Parent
.any
, "System we belong to")
119 # Determine if this cache sends out writebacks for clean lines, or
120 # simply clean evicts. In cases where a downstream cache is mostly
121 # exclusive with respect to this cache (acting as a victim cache),
122 # the clean writebacks are essential for performance. In general
123 # this should be set to True for anything but the last-level
125 writeback_clean
= Param
.Bool(False, "Writeback clean lines")
127 # Control whether this cache should be mostly inclusive or mostly
128 # exclusive with respect to upstream caches. The behaviour on a
129 # fill is determined accordingly. For a mostly inclusive cache,
130 # blocks are allocated on all fill operations. Thus, L1 caches
131 # should be set as mostly inclusive even if they have no upstream
132 # caches. In the case of a mostly exclusive cache, fills are not
133 # allocating unless they came directly from a non-caching source,
134 # e.g. a table walker. Additionally, on a hit from an upstream
135 # cache a line is dropped for a mostly exclusive cache.
136 clusivity
= Param
.Clusivity('mostly_incl',
137 "Clusivity with upstream cache")
139 # The write allocator enables optimizations for streaming write
140 # accesses by first coalescing writes and then avoiding allocation
141 # in the current cache. Typically, this would be enabled in the
143 write_allocator
= Param
.WriteAllocator(NULL
, "Write allocator")
145 class Cache(BaseCache
):
147 cxx_header
= 'mem/cache/cache.hh'
150 class NoncoherentCache(BaseCache
):
151 type = 'NoncoherentCache'
152 cxx_header
= 'mem/cache/noncoherent_cache.hh'
154 # This is typically a last level cache and any clean
155 # writebacks would be unnecessary traffic to the main memory.
156 writeback_clean
= False