src/mem/cache/Cache.py

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  38 #
  39 # Authors: Nathan Binkert
  40 #          Andreas Hansson
  41
  42 from m5.params import *
  43 from m5.proxy import *
  44 from MemObject import MemObject
  45 from Prefetcher import BasePrefetcher
  46 from ReplacementPolicies import *
  47 from Tags import *
  48
  49
  50 # Enum for cache clusivity, currently mostly inclusive or mostly
  51 # exclusive.
  52 class Clusivity(Enum): vals = ['mostly_incl', 'mostly_excl']
  53
  54
  55 class BaseCache(MemObject):
  56     type = 'BaseCache'
  57     abstract = True
  58     cxx_header = "mem/cache/base.hh"
  59
  60     size = Param.MemorySize("Capacity")
  61     assoc = Param.Unsigned("Associativity")
  62
  63     tag_latency = Param.Cycles("Tag lookup latency")
  64     data_latency = Param.Cycles("Data access latency")
  65     response_latency = Param.Cycles("Latency for the return path on a miss");
  66
  67     warmup_percentage = Param.Percent(0,
  68         "Percentage of tags to be touched to warm up the cache")
  69
  70     max_miss_count = Param.Counter(0,
  71         "Number of misses to handle before calling exit")
  72
  73     mshrs = Param.Unsigned("Number of MSHRs (max outstanding requests)")
  74     demand_mshr_reserve = Param.Unsigned(1, "MSHRs reserved for demand access")
  75     tgts_per_mshr = Param.Unsigned("Max number of accesses per MSHR")
  76     write_buffers = Param.Unsigned(8, "Number of write buffers")
  77
  78     is_read_only = Param.Bool(False, "Is this cache read only (e.g. inst)")
  79
  80     prefetcher = Param.BasePrefetcher(NULL,"Prefetcher attached to cache")
  81     prefetch_on_access = Param.Bool(False,
  82          "Notify the hardware prefetcher on every access (not just misses)")
  83
  84     tags = Param.BaseTags(BaseSetAssoc(), "Tag store")
  85     replacement_policy = Param.BaseReplacementPolicy(LRURP(),
  86         "Replacement policy")
  87
  88     sequential_access = Param.Bool(False,
  89         "Whether to access tags and data sequentially")
  90
  91     cpu_side = SlavePort("Upstream port closer to the CPU and/or device")
  92     mem_side = MasterPort("Downstream port closer to memory")
  93
  94     addr_ranges = VectorParam.AddrRange([AllMemory],
  95          "Address range for the CPU-side port (to allow striping)")
  96
  97     system = Param.System(Parent.any, "System we belong to")
  98
  99     # Determine if this cache sends out writebacks for clean lines, or
 100     # simply clean evicts. In cases where a downstream cache is mostly
 101     # exclusive with respect to this cache (acting as a victim cache),
 102     # the clean writebacks are essential for performance. In general
 103     # this should be set to True for anything but the last-level
 104     # cache.
 105     writeback_clean = Param.Bool(False, "Writeback clean lines")
 106
 107     # Control whether this cache should be mostly inclusive or mostly
 108     # exclusive with respect to upstream caches. The behaviour on a
 109     # fill is determined accordingly. For a mostly inclusive cache,
 110     # blocks are allocated on all fill operations. Thus, L1 caches
 111     # should be set as mostly inclusive even if they have no upstream
 112     # caches. In the case of a mostly exclusive cache, fills are not
 113     # allocating unless they came directly from a non-caching source,
 114     # e.g. a table walker. Additionally, on a hit from an upstream
 115     # cache a line is dropped for a mostly exclusive cache.
 116     clusivity = Param.Clusivity('mostly_incl',
 117                                 "Clusivity with upstream cache")
 118
 119
 120 class Cache(BaseCache):
 121     type = 'Cache'
 122     cxx_header = 'mem/cache/cache.hh'
 123
 124
 125 class NoncoherentCache(BaseCache):
 126     type = 'NoncoherentCache'
 127     cxx_header = 'mem/cache/noncoherent_cache.hh'
 128
 129     # This is typically a last level cache and any clean
 130     # writebacks would be unnecessary traffic to the main memory.
 131     writeback_clean = False
 132