src/mem/cache/Cache.py

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  38 #
  39 # Authors: Nathan Binkert
  40 #          Andreas Hansson
  41
  42 from m5.params import *
  43 from m5.proxy import *
  44 from m5.SimObject import SimObject
  45
  46 from m5.objects.ClockedObject import ClockedObject
  47 from m5.objects.Compressors import BaseCacheCompressor
  48 from m5.objects.Prefetcher import BasePrefetcher
  49 from m5.objects.ReplacementPolicies import *
  50 from m5.objects.Tags import *
  51
  52 # Enum for cache clusivity, currently mostly inclusive or mostly
  53 # exclusive.
  54 class Clusivity(Enum): vals = ['mostly_incl', 'mostly_excl']
  55
  56 class WriteAllocator(SimObject):
  57     type = 'WriteAllocator'
  58     cxx_header = "mem/cache/cache.hh"
  59
  60     # Control the limits for when the cache introduces extra delays to
  61     # allow whole-line write coalescing, and eventually switches to a
  62     # write-no-allocate policy.
  63     coalesce_limit = Param.Unsigned(2, "Consecutive lines written before "
  64                                     "delaying for coalescing")
  65     no_allocate_limit = Param.Unsigned(12, "Consecutive lines written before"
  66                                        " skipping allocation")
  67
  68     delay_threshold = Param.Unsigned(8, "Number of delay quanta imposed on an "
  69                                      "MSHR with write requests to allow for "
  70                                      "write coalescing")
  71
  72     block_size = Param.Int(Parent.cache_line_size, "block size in bytes")
  73
  74
  75 class BaseCache(ClockedObject):
  76     type = 'BaseCache'
  77     abstract = True
  78     cxx_header = "mem/cache/base.hh"
  79
  80     size = Param.MemorySize("Capacity")
  81     assoc = Param.Unsigned("Associativity")
  82
  83     tag_latency = Param.Cycles("Tag lookup latency")
  84     data_latency = Param.Cycles("Data access latency")
  85     response_latency = Param.Cycles("Latency for the return path on a miss");
  86
  87     warmup_percentage = Param.Percent(0,
  88         "Percentage of tags to be touched to warm up the cache")
  89
  90     max_miss_count = Param.Counter(0,
  91         "Number of misses to handle before calling exit")
  92
  93     mshrs = Param.Unsigned("Number of MSHRs (max outstanding requests)")
  94     demand_mshr_reserve = Param.Unsigned(1, "MSHRs reserved for demand access")
  95     tgts_per_mshr = Param.Unsigned("Max number of accesses per MSHR")
  96     write_buffers = Param.Unsigned(8, "Number of write buffers")
  97
  98     is_read_only = Param.Bool(False, "Is this cache read only (e.g. inst)")
  99
 100     prefetcher = Param.BasePrefetcher(NULL,"Prefetcher attached to cache")
 101     prefetch_on_access = Param.Bool(False,
 102          "Notify the hardware prefetcher on every access (not just misses)")
 103
 104     tags = Param.BaseTags(BaseSetAssoc(), "Tag store")
 105     replacement_policy = Param.BaseReplacementPolicy(LRURP(),
 106         "Replacement policy")
 107
 108     compressor = Param.BaseCacheCompressor(NULL, "Cache compressor.")
 109
 110     sequential_access = Param.Bool(False,
 111         "Whether to access tags and data sequentially")
 112
 113     cpu_side = SlavePort("Upstream port closer to the CPU and/or device")
 114     mem_side = MasterPort("Downstream port closer to memory")
 115
 116     addr_ranges = VectorParam.AddrRange([AllMemory],
 117          "Address range for the CPU-side port (to allow striping)")
 118
 119     system = Param.System(Parent.any, "System we belong to")
 120
 121     # Determine if this cache sends out writebacks for clean lines, or
 122     # simply clean evicts. In cases where a downstream cache is mostly
 123     # exclusive with respect to this cache (acting as a victim cache),
 124     # the clean writebacks are essential for performance. In general
 125     # this should be set to True for anything but the last-level
 126     # cache.
 127     writeback_clean = Param.Bool(False, "Writeback clean lines")
 128
 129     # Control whether this cache should be mostly inclusive or mostly
 130     # exclusive with respect to upstream caches. The behaviour on a
 131     # fill is determined accordingly. For a mostly inclusive cache,
 132     # blocks are allocated on all fill operations. Thus, L1 caches
 133     # should be set as mostly inclusive even if they have no upstream
 134     # caches. In the case of a mostly exclusive cache, fills are not
 135     # allocating unless they came directly from a non-caching source,
 136     # e.g. a table walker. Additionally, on a hit from an upstream
 137     # cache a line is dropped for a mostly exclusive cache.
 138     clusivity = Param.Clusivity('mostly_incl',
 139                                 "Clusivity with upstream cache")
 140
 141     # The write allocator enables optimizations for streaming write
 142     # accesses by first coalescing writes and then avoiding allocation
 143     # in the current cache. Typically, this would be enabled in the
 144     # data cache.
 145     write_allocator = Param.WriteAllocator(NULL, "Write allocator")
 146
 147 class Cache(BaseCache):
 148     type = 'Cache'
 149     cxx_header = 'mem/cache/cache.hh'
 150
 151
 152 class NoncoherentCache(BaseCache):
 153     type = 'NoncoherentCache'
 154     cxx_header = 'mem/cache/noncoherent_cache.hh'
 155
 156     # This is typically a last level cache and any clean
 157     # writebacks would be unnecessary traffic to the main memory.
 158     writeback_clean = False
 159