1 # Copyright (c) 2012-2013, 2015, 2018 ARM Limited
4 # The license below extends only to copyright in the software and shall
5 # not be construed as granting a license to any other intellectual
6 # property including but not limited to intellectual property relating
7 # to a hardware implementation of the functionality of the software
8 # licensed hereunder. You may use the software subject to the license
9 # terms below provided that you ensure that this notice is replicated
10 # unmodified and in its entirety in all distributions of the software,
11 # modified or unmodified, in source code or in binary form.
13 # Copyright (c) 2005-2007 The Regents of The University of Michigan
14 # All rights reserved.
16 # Redistribution and use in source and binary forms, with or without
17 # modification, are permitted provided that the following conditions are
18 # met: redistributions of source code must retain the above copyright
19 # notice, this list of conditions and the following disclaimer;
20 # redistributions in binary form must reproduce the above copyright
21 # notice, this list of conditions and the following disclaimer in the
22 # documentation and/or other materials provided with the distribution;
23 # neither the name of the copyright holders nor the names of its
24 # contributors may be used to endorse or promote products derived from
25 # this software without specific prior written permission.
27 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
30 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
32 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
33 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
34 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
35 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
36 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
37 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 # Authors: Nathan Binkert
42 from m5
.params
import *
43 from m5
.proxy
import *
44 from m5
.SimObject
import SimObject
46 from m5
.objects
.ClockedObject
import ClockedObject
47 from m5
.objects
.Compressors
import BaseCacheCompressor
48 from m5
.objects
.Prefetcher
import BasePrefetcher
49 from m5
.objects
.ReplacementPolicies
import *
50 from m5
.objects
.Tags
import *
52 # Enum for cache clusivity, currently mostly inclusive or mostly
54 class Clusivity(Enum
): vals
= ['mostly_incl', 'mostly_excl']
56 class WriteAllocator(SimObject
):
57 type = 'WriteAllocator'
58 cxx_header
= "mem/cache/cache.hh"
60 # Control the limits for when the cache introduces extra delays to
61 # allow whole-line write coalescing, and eventually switches to a
62 # write-no-allocate policy.
63 coalesce_limit
= Param
.Unsigned(2, "Consecutive lines written before "
64 "delaying for coalescing")
65 no_allocate_limit
= Param
.Unsigned(12, "Consecutive lines written before"
66 " skipping allocation")
68 delay_threshold
= Param
.Unsigned(8, "Number of delay quanta imposed on an "
69 "MSHR with write requests to allow for "
72 block_size
= Param
.Int(Parent
.cache_line_size
, "block size in bytes")
75 class BaseCache(ClockedObject
):
78 cxx_header
= "mem/cache/base.hh"
80 size
= Param
.MemorySize("Capacity")
81 assoc
= Param
.Unsigned("Associativity")
83 tag_latency
= Param
.Cycles("Tag lookup latency")
84 data_latency
= Param
.Cycles("Data access latency")
85 response_latency
= Param
.Cycles("Latency for the return path on a miss");
87 warmup_percentage
= Param
.Percent(0,
88 "Percentage of tags to be touched to warm up the cache")
90 max_miss_count
= Param
.Counter(0,
91 "Number of misses to handle before calling exit")
93 mshrs
= Param
.Unsigned("Number of MSHRs (max outstanding requests)")
94 demand_mshr_reserve
= Param
.Unsigned(1, "MSHRs reserved for demand access")
95 tgts_per_mshr
= Param
.Unsigned("Max number of accesses per MSHR")
96 write_buffers
= Param
.Unsigned(8, "Number of write buffers")
98 is_read_only
= Param
.Bool(False, "Is this cache read only (e.g. inst)")
100 prefetcher
= Param
.BasePrefetcher(NULL
,"Prefetcher attached to cache")
101 prefetch_on_access
= Param
.Bool(False,
102 "Notify the hardware prefetcher on every access (not just misses)")
104 tags
= Param
.BaseTags(BaseSetAssoc(), "Tag store")
105 replacement_policy
= Param
.BaseReplacementPolicy(LRURP(),
106 "Replacement policy")
108 compressor
= Param
.BaseCacheCompressor(NULL
, "Cache compressor.")
110 sequential_access
= Param
.Bool(False,
111 "Whether to access tags and data sequentially")
113 cpu_side
= SlavePort("Upstream port closer to the CPU and/or device")
114 mem_side
= MasterPort("Downstream port closer to memory")
116 addr_ranges
= VectorParam
.AddrRange([AllMemory
],
117 "Address range for the CPU-side port (to allow striping)")
119 system
= Param
.System(Parent
.any
, "System we belong to")
121 # Determine if this cache sends out writebacks for clean lines, or
122 # simply clean evicts. In cases where a downstream cache is mostly
123 # exclusive with respect to this cache (acting as a victim cache),
124 # the clean writebacks are essential for performance. In general
125 # this should be set to True for anything but the last-level
127 writeback_clean
= Param
.Bool(False, "Writeback clean lines")
129 # Control whether this cache should be mostly inclusive or mostly
130 # exclusive with respect to upstream caches. The behaviour on a
131 # fill is determined accordingly. For a mostly inclusive cache,
132 # blocks are allocated on all fill operations. Thus, L1 caches
133 # should be set as mostly inclusive even if they have no upstream
134 # caches. In the case of a mostly exclusive cache, fills are not
135 # allocating unless they came directly from a non-caching source,
136 # e.g. a table walker. Additionally, on a hit from an upstream
137 # cache a line is dropped for a mostly exclusive cache.
138 clusivity
= Param
.Clusivity('mostly_incl',
139 "Clusivity with upstream cache")
141 # The write allocator enables optimizations for streaming write
142 # accesses by first coalescing writes and then avoiding allocation
143 # in the current cache. Typically, this would be enabled in the
145 write_allocator
= Param
.WriteAllocator(NULL
, "Write allocator")
147 class Cache(BaseCache
):
149 cxx_header
= 'mem/cache/cache.hh'
152 class NoncoherentCache(BaseCache
):
153 type = 'NoncoherentCache'
154 cxx_header
= 'mem/cache/noncoherent_cache.hh'
156 # This is typically a last level cache and any clean
157 # writebacks would be unnecessary traffic to the main memory.
158 writeback_clean
= False