src/mem/cache/Cache.py

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  39 # Authors: Nathan Binkert
  40 #          Andreas Hansson
  41
  42 from m5.params import *
  43 from m5.proxy import *
  44 from MemObject import MemObject
  45 from Prefetcher import BasePrefetcher
  46 from Tags import *
  47
  48 class BaseCache(MemObject):
  49     type = 'BaseCache'
  50     abstract = True
  51     cxx_header = "mem/cache/base.hh"
  52
  53     size = Param.MemorySize("Capacity")
  54     assoc = Param.Unsigned("Associativity")
  55
  56     hit_latency = Param.Cycles("Hit latency")
  57     response_latency = Param.Cycles("Latency for the return path on a miss");
  58
  59     max_miss_count = Param.Counter(0,
  60         "Number of misses to handle before calling exit")
  61
  62     mshrs = Param.Unsigned("Number of MSHRs (max outstanding requests)")
  63     demand_mshr_reserve = Param.Unsigned(1, "MSHRs reserved for demand access")
  64     tgts_per_mshr = Param.Unsigned("Max number of accesses per MSHR")
  65     write_buffers = Param.Unsigned(8, "Number of write buffers")
  66
  67     forward_snoops = Param.Bool(True,
  68         "Forward snoops from mem side to cpu side")
  69     is_read_only = Param.Bool(False, "Is this cache read only (e.g. inst)")
  70
  71     prefetcher = Param.BasePrefetcher(NULL,"Prefetcher attached to cache")
  72     prefetch_on_access = Param.Bool(False,
  73          "Notify the hardware prefetcher on every access (not just misses)")
  74
  75     tags = Param.BaseTags(LRU(), "Tag store (replacement policy)")
  76     sequential_access = Param.Bool(False,
  77         "Whether to access tags and data sequentially")
  78
  79     cpu_side = SlavePort("Upstream port closer to the CPU and/or device")
  80     mem_side = MasterPort("Downstream port closer to memory")
  81
  82     addr_ranges = VectorParam.AddrRange([AllMemory],
  83          "Address range for the CPU-side port (to allow striping)")
  84
  85     system = Param.System(Parent.any, "System we belong to")
  86
  87 class Cache(BaseCache):
  88     type = 'Cache'
  89     cxx_header = 'mem/cache/cache.hh'