src/mem/cache/Cache.py

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  38
  39 from m5.params import *
  40 from m5.proxy import *
  41 from m5.SimObject import SimObject
  42
  43 from m5.objects.ClockedObject import ClockedObject
  44 from m5.objects.Compressors import BaseCacheCompressor
  45 from m5.objects.Prefetcher import BasePrefetcher
  46 from m5.objects.ReplacementPolicies import *
  47 from m5.objects.Tags import *
  48
  49 # Enum for cache clusivity, currently mostly inclusive or mostly
  50 # exclusive.
  51 class Clusivity(Enum): vals = ['mostly_incl', 'mostly_excl']
  52
  53 class WriteAllocator(SimObject):
  54     type = 'WriteAllocator'
  55     cxx_header = "mem/cache/cache.hh"
  56
  57     # Control the limits for when the cache introduces extra delays to
  58     # allow whole-line write coalescing, and eventually switches to a
  59     # write-no-allocate policy.
  60     coalesce_limit = Param.Unsigned(2, "Consecutive lines written before "
  61                                     "delaying for coalescing")
  62     no_allocate_limit = Param.Unsigned(12, "Consecutive lines written before"
  63                                        " skipping allocation")
  64
  65     delay_threshold = Param.Unsigned(8, "Number of delay quanta imposed on an "
  66                                      "MSHR with write requests to allow for "
  67                                      "write coalescing")
  68
  69     block_size = Param.Int(Parent.cache_line_size, "block size in bytes")
  70
  71
  72 class BaseCache(ClockedObject):
  73     type = 'BaseCache'
  74     abstract = True
  75     cxx_header = "mem/cache/base.hh"
  76
  77     size = Param.MemorySize("Capacity")
  78     assoc = Param.Unsigned("Associativity")
  79
  80     tag_latency = Param.Cycles("Tag lookup latency")
  81     data_latency = Param.Cycles("Data access latency")
  82     response_latency = Param.Cycles("Latency for the return path on a miss");
  83
  84     warmup_percentage = Param.Percent(0,
  85         "Percentage of tags to be touched to warm up the cache")
  86
  87     max_miss_count = Param.Counter(0,
  88         "Number of misses to handle before calling exit")
  89
  90     mshrs = Param.Unsigned("Number of MSHRs (max outstanding requests)")
  91     demand_mshr_reserve = Param.Unsigned(1, "MSHRs reserved for demand access")
  92     tgts_per_mshr = Param.Unsigned("Max number of accesses per MSHR")
  93     write_buffers = Param.Unsigned(8, "Number of write buffers")
  94
  95     is_read_only = Param.Bool(False, "Is this cache read only (e.g. inst)")
  96
  97     prefetcher = Param.BasePrefetcher(NULL,"Prefetcher attached to cache")
  98     prefetch_on_access = Param.Bool(False,
  99          "Notify the hardware prefetcher on every access (not just misses)")
 100
 101     tags = Param.BaseTags(BaseSetAssoc(), "Tag store")
 102     replacement_policy = Param.BaseReplacementPolicy(LRURP(),
 103         "Replacement policy")
 104
 105     compressor = Param.BaseCacheCompressor(NULL, "Cache compressor.")
 106
 107     sequential_access = Param.Bool(False,
 108         "Whether to access tags and data sequentially")
 109
 110     cpu_side = ResponsePort("Upstream port closer to the CPU and/or device")
 111     mem_side = RequestPort("Downstream port closer to memory")
 112
 113     addr_ranges = VectorParam.AddrRange([AllMemory],
 114          "Address range for the CPU-side port (to allow striping)")
 115
 116     system = Param.System(Parent.any, "System we belong to")
 117
 118     # Determine if this cache sends out writebacks for clean lines, or
 119     # simply clean evicts. In cases where a downstream cache is mostly
 120     # exclusive with respect to this cache (acting as a victim cache),
 121     # the clean writebacks are essential for performance. In general
 122     # this should be set to True for anything but the last-level
 123     # cache.
 124     writeback_clean = Param.Bool(False, "Writeback clean lines")
 125
 126     # Control whether this cache should be mostly inclusive or mostly
 127     # exclusive with respect to upstream caches. The behaviour on a
 128     # fill is determined accordingly. For a mostly inclusive cache,
 129     # blocks are allocated on all fill operations. Thus, L1 caches
 130     # should be set as mostly inclusive even if they have no upstream
 131     # caches. In the case of a mostly exclusive cache, fills are not
 132     # allocating unless they came directly from a non-caching source,
 133     # e.g. a table walker. Additionally, on a hit from an upstream
 134     # cache a line is dropped for a mostly exclusive cache.
 135     clusivity = Param.Clusivity('mostly_incl',
 136                                 "Clusivity with upstream cache")
 137
 138     # The write allocator enables optimizations for streaming write
 139     # accesses by first coalescing writes and then avoiding allocation
 140     # in the current cache. Typically, this would be enabled in the
 141     # data cache.
 142     write_allocator = Param.WriteAllocator(NULL, "Write allocator")
 143
 144 class Cache(BaseCache):
 145     type = 'Cache'
 146     cxx_header = 'mem/cache/cache.hh'
 147
 148
 149 class NoncoherentCache(BaseCache):
 150     type = 'NoncoherentCache'
 151     cxx_header = 'mem/cache/noncoherent_cache.hh'
 152
 153     # This is typically a last level cache and any clean
 154     # writebacks would be unnecessary traffic to the main memory.
 155     writeback_clean = False
 156