src/mem/cache/Cache.py

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  38 #
  39 # Authors: Nathan Binkert
  40 #          Andreas Hansson
  41
  42 from m5.params import *
  43 from m5.proxy import *
  44 from MemObject import MemObject
  45 from Prefetcher import BasePrefetcher
  46 from Tags import *
  47
  48 class BaseCache(MemObject):
  49     type = 'BaseCache'
  50     abstract = True
  51     cxx_header = "mem/cache/base.hh"
  52
  53     size = Param.MemorySize("Capacity")
  54     assoc = Param.Unsigned("Associativity")
  55
  56     hit_latency = Param.Cycles("Hit latency")
  57     response_latency = Param.Cycles("Latency for the return path on a miss");
  58
  59     max_miss_count = Param.Counter(0,
  60         "Number of misses to handle before calling exit")
  61
  62     mshrs = Param.Unsigned("Number of MSHRs (max outstanding requests)")
  63     demand_mshr_reserve = Param.Unsigned(1, "MSHRs reserved for demand access")
  64     tgts_per_mshr = Param.Unsigned("Max number of accesses per MSHR")
  65     write_buffers = Param.Unsigned(8, "Number of write buffers")
  66
  67     is_read_only = Param.Bool(False, "Is this cache read only (e.g. inst)")
  68
  69     prefetcher = Param.BasePrefetcher(NULL,"Prefetcher attached to cache")
  70     prefetch_on_access = Param.Bool(False,
  71          "Notify the hardware prefetcher on every access (not just misses)")
  72
  73     tags = Param.BaseTags(LRU(), "Tag store (replacement policy)")
  74     sequential_access = Param.Bool(False,
  75         "Whether to access tags and data sequentially")
  76
  77     cpu_side = SlavePort("Upstream port closer to the CPU and/or device")
  78     mem_side = MasterPort("Downstream port closer to memory")
  79
  80     addr_ranges = VectorParam.AddrRange([AllMemory],
  81          "Address range for the CPU-side port (to allow striping)")
  82
  83     system = Param.System(Parent.any, "System we belong to")
  84
  85 # Enum for cache clusivity, currently mostly inclusive or mostly
  86 # exclusive.
  87 class Clusivity(Enum): vals = ['mostly_incl', 'mostly_excl']
  88
  89 class Cache(BaseCache):
  90     type = 'Cache'
  91     cxx_header = 'mem/cache/cache.hh'
  92
  93     # Control whether this cache should be mostly inclusive or mostly
  94     # exclusive with respect to upstream caches. The behaviour on a
  95     # fill is determined accordingly. For a mostly inclusive cache,
  96     # blocks are allocated on all fill operations. Thus, L1 caches
  97     # should be set as mostly inclusive even if they have no upstream
  98     # caches. In the case of a mostly exclusive cache, fills are not
  99     # allocating unless they came directly from a non-caching source,
 100     # e.g. a table walker. Additionally, on a hit from an upstream
 101     # cache a line is dropped for a mostly exclusive cache.
 102     clusivity = Param.Clusivity('mostly_incl',
 103                                 "Clusivity with upstream cache")
 104
 105     # Determine if this cache sends out writebacks for clean lines, or
 106     # simply clean evicts. In cases where a downstream cache is mostly
 107     # exclusive with respect to this cache (acting as a victim cache),
 108     # the clean writebacks are essential for performance. In general
 109     # this should be set to True for anything but the last-level
 110     # cache.
 111     writeback_clean = Param.Bool(False, "Writeback clean lines")