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40 * Authors: Erik Hallnor
46 * Definition of BaseCache functions.
49 #include "mem/cache/base.hh"
51 #include "base/compiler.hh"
52 #include "base/logging.hh"
53 #include "debug/Cache.hh"
54 #include "debug/CachePort.hh"
55 #include "debug/CacheVerbose.hh"
56 #include "mem/cache/mshr.hh"
57 #include "mem/cache/prefetch/base.hh"
58 #include "mem/cache/queue_entry.hh"
59 #include "params/BaseCache.hh"
60 #include "sim/core.hh"
67 BaseCache::CacheSlavePort::CacheSlavePort(const std::string
&_name
,
69 const std::string
&_label
)
70 : QueuedSlavePort(_name
, _cache
, queue
), queue(*_cache
, *this, _label
),
71 blocked(false), mustSendRetry(false),
72 sendRetryEvent([this]{ processSendRetry(); }, _name
)
76 BaseCache::BaseCache(const BaseCacheParams
*p
, unsigned blk_size
)
78 cpuSidePort (p
->name
+ ".cpu_side", this, "CpuSidePort"),
79 memSidePort(p
->name
+ ".mem_side", this, "MemSidePort"),
80 mshrQueue("MSHRs", p
->mshrs
, 0, p
->demand_mshr_reserve
), // see below
81 writeBuffer("write buffer", p
->write_buffers
, p
->mshrs
), // see below
83 prefetcher(p
->prefetcher
),
84 prefetchOnAccess(p
->prefetch_on_access
),
85 writebackClean(p
->writeback_clean
),
86 tempBlockWriteback(nullptr),
87 writebackTempBlockAtomicEvent([this]{ writebackTempBlockAtomic(); },
89 EventBase::Delayed_Writeback_Pri
),
91 lookupLatency(p
->tag_latency
),
92 dataLatency(p
->data_latency
),
93 forwardLatency(p
->tag_latency
),
94 fillLatency(p
->data_latency
),
95 responseLatency(p
->response_latency
),
96 numTarget(p
->tgts_per_mshr
),
98 clusivity(p
->clusivity
),
99 isReadOnly(p
->is_read_only
),
102 noTargetMSHR(nullptr),
103 missCount(p
->max_miss_count
),
104 addrRanges(p
->addr_ranges
.begin(), p
->addr_ranges
.end()),
107 // the MSHR queue has no reserve entries as we check the MSHR
108 // queue on every single allocation, whereas the write queue has
109 // as many reserve entries as we have MSHRs, since every MSHR may
110 // eventually require a writeback, and we do not check the write
111 // buffer before committing to an MSHR
113 // forward snoops is overridden in init() once we can query
114 // whether the connected master is actually snooping or not
116 tempBlock
= new TempCacheBlk(blkSize
);
118 tags
->setCache(this);
120 prefetcher
->setCache(this);
123 BaseCache::~BaseCache()
129 BaseCache::CacheSlavePort::setBlocked()
132 DPRINTF(CachePort
, "Port is blocking new requests\n");
134 // if we already scheduled a retry in this cycle, but it has not yet
135 // happened, cancel it
136 if (sendRetryEvent
.scheduled()) {
137 owner
.deschedule(sendRetryEvent
);
138 DPRINTF(CachePort
, "Port descheduled retry\n");
139 mustSendRetry
= true;
144 BaseCache::CacheSlavePort::clearBlocked()
147 DPRINTF(CachePort
, "Port is accepting new requests\n");
150 // @TODO: need to find a better time (next cycle?)
151 owner
.schedule(sendRetryEvent
, curTick() + 1);
156 BaseCache::CacheSlavePort::processSendRetry()
158 DPRINTF(CachePort
, "Port is sending retry\n");
160 // reset the flag and call retry
161 mustSendRetry
= false;
166 BaseCache::regenerateBlkAddr(CacheBlk
* blk
)
168 if (blk
!= tempBlock
) {
169 return tags
->regenerateBlkAddr(blk
);
171 return tempBlock
->getAddr();
178 if (!cpuSidePort
.isConnected() || !memSidePort
.isConnected())
179 fatal("Cache ports on %s are not connected\n", name());
180 cpuSidePort
.sendRangeChange();
181 forwardSnoops
= cpuSidePort
.isSnooping();
185 BaseCache::getMasterPort(const std::string
&if_name
, PortID idx
)
187 if (if_name
== "mem_side") {
190 return MemObject::getMasterPort(if_name
, idx
);
195 BaseCache::getSlavePort(const std::string
&if_name
, PortID idx
)
197 if (if_name
== "cpu_side") {
200 return MemObject::getSlavePort(if_name
, idx
);
205 BaseCache::inRange(Addr addr
) const
207 for (const auto& r
: addrRanges
) {
208 if (r
.contains(addr
)) {
216 BaseCache::handleTimingReqHit(PacketPtr pkt
, CacheBlk
*blk
, Tick request_time
)
218 if (pkt
->needsResponse()) {
219 pkt
->makeTimingResponse();
220 // @todo: Make someone pay for this
221 pkt
->headerDelay
= pkt
->payloadDelay
= 0;
223 // In this case we are considering request_time that takes
224 // into account the delay of the xbar, if any, and just
225 // lat, neglecting responseLatency, modelling hit latency
226 // just as lookupLatency or or the value of lat overriden
227 // by access(), that calls accessBlock() function.
228 cpuSidePort
.schedTimingResp(pkt
, request_time
, true);
230 DPRINTF(Cache
, "%s satisfied %s, no response needed\n", __func__
,
233 // queue the packet for deletion, as the sending cache is
234 // still relying on it; if the block is found in access(),
235 // CleanEvict and Writeback messages will be deleted
237 pendingDelete
.reset(pkt
);
242 BaseCache::handleTimingReqMiss(PacketPtr pkt
, MSHR
*mshr
, CacheBlk
*blk
,
243 Tick forward_time
, Tick request_time
)
247 /// @note writebacks will be checked in getNextMSHR()
248 /// for any conflicting requests to the same block
250 //@todo remove hw_pf here
252 // Coalesce unless it was a software prefetch (see above).
254 assert(!pkt
->isWriteback());
255 // CleanEvicts corresponding to blocks which have
256 // outstanding requests in MSHRs are simply sunk here
257 if (pkt
->cmd
== MemCmd::CleanEvict
) {
258 pendingDelete
.reset(pkt
);
259 } else if (pkt
->cmd
== MemCmd::WriteClean
) {
260 // A WriteClean should never coalesce with any
261 // outstanding cache maintenance requests.
263 // We use forward_time here because there is an
264 // uncached memory write, forwarded to WriteBuffer.
265 allocateWriteBuffer(pkt
, forward_time
);
267 DPRINTF(Cache
, "%s coalescing MSHR for %s\n", __func__
,
270 assert(pkt
->req
->masterId() < system
->maxMasters());
271 mshr_hits
[pkt
->cmdToIndex()][pkt
->req
->masterId()]++;
273 // We use forward_time here because it is the same
274 // considering new targets. We have multiple
275 // requests for the same address here. It
276 // specifies the latency to allocate an internal
277 // buffer and to schedule an event to the queued
278 // port and also takes into account the additional
279 // delay of the xbar.
280 mshr
->allocateTarget(pkt
, forward_time
, order
++,
281 allocOnFill(pkt
->cmd
));
282 if (mshr
->getNumTargets() == numTarget
) {
284 setBlocked(Blocked_NoTargets
);
285 // need to be careful with this... if this mshr isn't
286 // ready yet (i.e. time > curTick()), we don't want to
287 // move it ahead of mshrs that are ready
288 // mshrQueue.moveToFront(mshr);
294 assert(pkt
->req
->masterId() < system
->maxMasters());
295 mshr_misses
[pkt
->cmdToIndex()][pkt
->req
->masterId()]++;
297 if (pkt
->isEviction() || pkt
->cmd
== MemCmd::WriteClean
) {
298 // We use forward_time here because there is an
299 // writeback or writeclean, forwarded to WriteBuffer.
300 allocateWriteBuffer(pkt
, forward_time
);
302 if (blk
&& blk
->isValid()) {
303 // If we have a write miss to a valid block, we
304 // need to mark the block non-readable. Otherwise
305 // if we allow reads while there's an outstanding
306 // write miss, the read could return stale data
307 // out of the cache block... a more aggressive
308 // system could detect the overlap (if any) and
309 // forward data out of the MSHRs, but we don't do
310 // that yet. Note that we do need to leave the
311 // block valid so that it stays in the cache, in
312 // case we get an upgrade response (and hence no
313 // new data) when the write miss completes.
314 // As long as CPUs do proper store/load forwarding
315 // internally, and have a sufficiently weak memory
316 // model, this is probably unnecessary, but at some
317 // point it must have seemed like we needed it...
318 assert((pkt
->needsWritable() && !blk
->isWritable()) ||
319 pkt
->req
->isCacheMaintenance());
320 blk
->status
&= ~BlkReadable
;
322 // Here we are using forward_time, modelling the latency of
323 // a miss (outbound) just as forwardLatency, neglecting the
324 // lookupLatency component.
325 allocateMissBuffer(pkt
, forward_time
);
331 BaseCache::recvTimingReq(PacketPtr pkt
)
333 // anything that is merely forwarded pays for the forward latency and
334 // the delay provided by the crossbar
335 Tick forward_time
= clockEdge(forwardLatency
) + pkt
->headerDelay
;
337 // We use lookupLatency here because it is used to specify the latency
339 Cycles lat
= lookupLatency
;
340 CacheBlk
*blk
= nullptr;
341 bool satisfied
= false;
343 PacketList writebacks
;
344 // Note that lat is passed by reference here. The function
345 // access() calls accessBlock() which can modify lat value.
346 satisfied
= access(pkt
, blk
, lat
, writebacks
);
348 // copy writebacks to write buffer here to ensure they logically
349 // precede anything happening below
350 doWritebacks(writebacks
, forward_time
);
353 // Here we charge the headerDelay that takes into account the latencies
354 // of the bus, if the packet comes from it.
355 // The latency charged it is just lat that is the value of lookupLatency
356 // modified by access() function, or if not just lookupLatency.
357 // In case of a hit we are neglecting response latency.
358 // In case of a miss we are neglecting forward latency.
359 Tick request_time
= clockEdge(lat
) + pkt
->headerDelay
;
360 // Here we reset the timing of the packet.
361 pkt
->headerDelay
= pkt
->payloadDelay
= 0;
362 // track time of availability of next prefetch, if any
363 Tick next_pf_time
= MaxTick
;
366 // if need to notify the prefetcher we have to do it before
367 // anything else as later handleTimingReqHit might turn the
368 // packet in a response
370 (prefetchOnAccess
|| (blk
&& blk
->wasPrefetched()))) {
372 blk
->status
&= ~BlkHWPrefetched
;
374 // Don't notify on SWPrefetch
375 if (!pkt
->cmd
.isSWPrefetch()) {
376 assert(!pkt
->req
->isCacheMaintenance());
377 next_pf_time
= prefetcher
->notify(pkt
);
381 handleTimingReqHit(pkt
, blk
, request_time
);
383 handleTimingReqMiss(pkt
, blk
, forward_time
, request_time
);
385 // We should call the prefetcher reguardless if the request is
386 // satisfied or not, reguardless if the request is in the MSHR
387 // or not. The request could be a ReadReq hit, but still not
388 // satisfied (potentially because of a prior write to the same
389 // cache line. So, even when not satisfied, there is an MSHR
390 // already allocated for this, we need to let the prefetcher
391 // know about the request
393 // Don't notify prefetcher on SWPrefetch or cache maintenance
395 if (prefetcher
&& pkt
&&
396 !pkt
->cmd
.isSWPrefetch() &&
397 !pkt
->req
->isCacheMaintenance()) {
398 next_pf_time
= prefetcher
->notify(pkt
);
402 if (next_pf_time
!= MaxTick
) {
403 schedMemSideSendEvent(next_pf_time
);
408 BaseCache::handleUncacheableWriteResp(PacketPtr pkt
)
410 Tick completion_time
= clockEdge(responseLatency
) +
411 pkt
->headerDelay
+ pkt
->payloadDelay
;
413 // Reset the bus additional time as it is now accounted for
414 pkt
->headerDelay
= pkt
->payloadDelay
= 0;
416 cpuSidePort
.schedTimingResp(pkt
, completion_time
, true);
420 BaseCache::recvTimingResp(PacketPtr pkt
)
422 assert(pkt
->isResponse());
424 // all header delay should be paid for by the crossbar, unless
425 // this is a prefetch response from above
426 panic_if(pkt
->headerDelay
!= 0 && pkt
->cmd
!= MemCmd::HardPFResp
,
427 "%s saw a non-zero packet delay\n", name());
429 const bool is_error
= pkt
->isError();
432 DPRINTF(Cache
, "%s: Cache received %s with error\n", __func__
,
436 DPRINTF(Cache
, "%s: Handling response %s\n", __func__
,
439 // if this is a write, we should be looking at an uncacheable
441 if (pkt
->isWrite()) {
442 assert(pkt
->req
->isUncacheable());
443 handleUncacheableWriteResp(pkt
);
447 // we have dealt with any (uncacheable) writes above, from here on
448 // we know we are dealing with an MSHR due to a miss or a prefetch
449 MSHR
*mshr
= dynamic_cast<MSHR
*>(pkt
->popSenderState());
452 if (mshr
== noTargetMSHR
) {
453 // we always clear at least one target
454 clearBlocked(Blocked_NoTargets
);
455 noTargetMSHR
= nullptr;
458 // Initial target is used just for stats
459 MSHR::Target
*initial_tgt
= mshr
->getTarget();
460 int stats_cmd_idx
= initial_tgt
->pkt
->cmdToIndex();
461 Tick miss_latency
= curTick() - initial_tgt
->recvTime
;
463 if (pkt
->req
->isUncacheable()) {
464 assert(pkt
->req
->masterId() < system
->maxMasters());
465 mshr_uncacheable_lat
[stats_cmd_idx
][pkt
->req
->masterId()] +=
468 assert(pkt
->req
->masterId() < system
->maxMasters());
469 mshr_miss_latency
[stats_cmd_idx
][pkt
->req
->masterId()] +=
473 PacketList writebacks
;
475 bool is_fill
= !mshr
->isForward
&&
476 (pkt
->isRead() || pkt
->cmd
== MemCmd::UpgradeResp
);
478 CacheBlk
*blk
= tags
->findBlock(pkt
->getAddr(), pkt
->isSecure());
480 if (is_fill
&& !is_error
) {
481 DPRINTF(Cache
, "Block for addr %#llx being updated in Cache\n",
484 blk
= handleFill(pkt
, blk
, writebacks
, mshr
->allocOnFill());
485 assert(blk
!= nullptr);
488 if (blk
&& blk
->isValid() && pkt
->isClean() && !pkt
->isInvalidate()) {
489 // The block was marked not readable while there was a pending
490 // cache maintenance operation, restore its flag.
491 blk
->status
|= BlkReadable
;
493 // This was a cache clean operation (without invalidate)
494 // and we have a copy of the block already. Since there
495 // is no invalidation, we can promote targets that don't
496 // require a writable copy
497 mshr
->promoteReadable();
500 if (blk
&& blk
->isWritable() && !pkt
->req
->isCacheInvalidate()) {
501 // If at this point the referenced block is writable and the
502 // response is not a cache invalidate, we promote targets that
503 // were deferred as we couldn't guarrantee a writable copy
504 mshr
->promoteWritable();
507 serviceMSHRTargets(mshr
, pkt
, blk
, writebacks
);
509 if (mshr
->promoteDeferredTargets()) {
510 // avoid later read getting stale data while write miss is
511 // outstanding.. see comment in timingAccess()
513 blk
->status
&= ~BlkReadable
;
515 mshrQueue
.markPending(mshr
);
516 schedMemSideSendEvent(clockEdge() + pkt
->payloadDelay
);
518 // while we deallocate an mshr from the queue we still have to
519 // check the isFull condition before and after as we might
520 // have been using the reserved entries already
521 const bool was_full
= mshrQueue
.isFull();
522 mshrQueue
.deallocate(mshr
);
523 if (was_full
&& !mshrQueue
.isFull()) {
524 clearBlocked(Blocked_NoMSHRs
);
527 // Request the bus for a prefetch if this deallocation freed enough
528 // MSHRs for a prefetch to take place
529 if (prefetcher
&& mshrQueue
.canPrefetch()) {
530 Tick next_pf_time
= std::max(prefetcher
->nextPrefetchReadyTime(),
532 if (next_pf_time
!= MaxTick
)
533 schedMemSideSendEvent(next_pf_time
);
537 // if we used temp block, check to see if its valid and then clear it out
538 if (blk
== tempBlock
&& tempBlock
->isValid()) {
539 evictBlock(blk
, writebacks
);
542 const Tick forward_time
= clockEdge(forwardLatency
) + pkt
->headerDelay
;
543 // copy writebacks to write buffer
544 doWritebacks(writebacks
, forward_time
);
546 DPRINTF(CacheVerbose
, "%s: Leaving with %s\n", __func__
, pkt
->print());
552 BaseCache::recvAtomic(PacketPtr pkt
)
554 // We are in atomic mode so we pay just for lookupLatency here.
555 Cycles lat
= lookupLatency
;
557 // follow the same flow as in recvTimingReq, and check if a cache
558 // above us is responding
559 if (pkt
->cacheResponding() && !pkt
->isClean()) {
560 assert(!pkt
->req
->isCacheInvalidate());
561 DPRINTF(Cache
, "Cache above responding to %s: not responding\n",
564 // if a cache is responding, and it had the line in Owned
565 // rather than Modified state, we need to invalidate any
566 // copies that are not on the same path to memory
567 assert(pkt
->needsWritable() && !pkt
->responderHadWritable());
568 lat
+= ticksToCycles(memSidePort
.sendAtomic(pkt
));
570 return lat
* clockPeriod();
573 // should assert here that there are no outstanding MSHRs or
574 // writebacks... that would mean that someone used an atomic
575 // access in timing mode
577 CacheBlk
*blk
= nullptr;
578 PacketList writebacks
;
579 bool satisfied
= access(pkt
, blk
, lat
, writebacks
);
581 if (pkt
->isClean() && blk
&& blk
->isDirty()) {
582 // A cache clean opearation is looking for a dirty
583 // block. If a dirty block is encountered a WriteClean
584 // will update any copies to the path to the memory
585 // until the point of reference.
586 DPRINTF(CacheVerbose
, "%s: packet %s found block: %s\n",
587 __func__
, pkt
->print(), blk
->print());
588 PacketPtr wb_pkt
= writecleanBlk(blk
, pkt
->req
->getDest(), pkt
->id
);
589 writebacks
.push_back(wb_pkt
);
593 // handle writebacks resulting from the access here to ensure they
594 // logically precede anything happening below
595 doWritebacksAtomic(writebacks
);
596 assert(writebacks
.empty());
599 lat
+= handleAtomicReqMiss(pkt
, blk
, writebacks
);
602 // Note that we don't invoke the prefetcher at all in atomic mode.
603 // It's not clear how to do it properly, particularly for
604 // prefetchers that aggressively generate prefetch candidates and
605 // rely on bandwidth contention to throttle them; these will tend
606 // to pollute the cache in atomic mode since there is no bandwidth
607 // contention. If we ever do want to enable prefetching in atomic
608 // mode, though, this is the place to do it... see timingAccess()
609 // for an example (though we'd want to issue the prefetch(es)
610 // immediately rather than calling requestMemSideBus() as we do
613 // do any writebacks resulting from the response handling
614 doWritebacksAtomic(writebacks
);
616 // if we used temp block, check to see if its valid and if so
617 // clear it out, but only do so after the call to recvAtomic is
618 // finished so that any downstream observers (such as a snoop
619 // filter), first see the fill, and only then see the eviction
620 if (blk
== tempBlock
&& tempBlock
->isValid()) {
621 // the atomic CPU calls recvAtomic for fetch and load/store
622 // sequentuially, and we may already have a tempBlock
623 // writeback from the fetch that we have not yet sent
624 if (tempBlockWriteback
) {
625 // if that is the case, write the prevoius one back, and
626 // do not schedule any new event
627 writebackTempBlockAtomic();
629 // the writeback/clean eviction happens after the call to
630 // recvAtomic has finished (but before any successive
631 // calls), so that the response handling from the fill is
632 // allowed to happen first
633 schedule(writebackTempBlockAtomicEvent
, curTick());
636 tempBlockWriteback
= evictBlock(blk
);
639 if (pkt
->needsResponse()) {
640 pkt
->makeAtomicResponse();
643 return lat
* clockPeriod();
647 BaseCache::functionalAccess(PacketPtr pkt
, bool from_cpu_side
)
649 Addr blk_addr
= pkt
->getBlockAddr(blkSize
);
650 bool is_secure
= pkt
->isSecure();
651 CacheBlk
*blk
= tags
->findBlock(pkt
->getAddr(), is_secure
);
652 MSHR
*mshr
= mshrQueue
.findMatch(blk_addr
, is_secure
);
654 pkt
->pushLabel(name());
656 CacheBlkPrintWrapper
cbpw(blk
);
658 // Note that just because an L2/L3 has valid data doesn't mean an
659 // L1 doesn't have a more up-to-date modified copy that still
660 // needs to be found. As a result we always update the request if
661 // we have it, but only declare it satisfied if we are the owner.
663 // see if we have data at all (owned or otherwise)
664 bool have_data
= blk
&& blk
->isValid()
665 && pkt
->trySatisfyFunctional(&cbpw
, blk_addr
, is_secure
, blkSize
,
668 // data we have is dirty if marked as such or if we have an
669 // in-service MSHR that is pending a modified line
671 have_data
&& (blk
->isDirty() ||
672 (mshr
&& mshr
->inService
&& mshr
->isPendingModified()));
674 bool done
= have_dirty
||
675 cpuSidePort
.trySatisfyFunctional(pkt
) ||
676 mshrQueue
.trySatisfyFunctional(pkt
, blk_addr
) ||
677 writeBuffer
.trySatisfyFunctional(pkt
, blk_addr
) ||
678 memSidePort
.trySatisfyFunctional(pkt
);
680 DPRINTF(CacheVerbose
, "%s: %s %s%s%s\n", __func__
, pkt
->print(),
681 (blk
&& blk
->isValid()) ? "valid " : "",
682 have_data
? "data " : "", done
? "done " : "");
684 // We're leaving the cache, so pop cache->name() label
690 // if it came as a request from the CPU side then make sure it
691 // continues towards the memory side
693 memSidePort
.sendFunctional(pkt
);
694 } else if (cpuSidePort
.isSnooping()) {
695 // if it came from the memory side, it must be a snoop request
696 // and we should only forward it if we are forwarding snoops
697 cpuSidePort
.sendFunctionalSnoop(pkt
);
704 BaseCache::cmpAndSwap(CacheBlk
*blk
, PacketPtr pkt
)
706 assert(pkt
->isRequest());
708 uint64_t overwrite_val
;
710 uint64_t condition_val64
;
711 uint32_t condition_val32
;
713 int offset
= pkt
->getOffset(blkSize
);
714 uint8_t *blk_data
= blk
->data
+ offset
;
716 assert(sizeof(uint64_t) >= pkt
->getSize());
718 overwrite_mem
= true;
719 // keep a copy of our possible write value, and copy what is at the
720 // memory address into the packet
721 pkt
->writeData((uint8_t *)&overwrite_val
);
722 pkt
->setData(blk_data
);
724 if (pkt
->req
->isCondSwap()) {
725 if (pkt
->getSize() == sizeof(uint64_t)) {
726 condition_val64
= pkt
->req
->getExtraData();
727 overwrite_mem
= !std::memcmp(&condition_val64
, blk_data
,
729 } else if (pkt
->getSize() == sizeof(uint32_t)) {
730 condition_val32
= (uint32_t)pkt
->req
->getExtraData();
731 overwrite_mem
= !std::memcmp(&condition_val32
, blk_data
,
734 panic("Invalid size for conditional read/write\n");
738 std::memcpy(blk_data
, &overwrite_val
, pkt
->getSize());
739 blk
->status
|= BlkDirty
;
744 BaseCache::getNextQueueEntry()
746 // Check both MSHR queue and write buffer for potential requests,
747 // note that null does not mean there is no request, it could
748 // simply be that it is not ready
749 MSHR
*miss_mshr
= mshrQueue
.getNext();
750 WriteQueueEntry
*wq_entry
= writeBuffer
.getNext();
752 // If we got a write buffer request ready, first priority is a
753 // full write buffer, otherwise we favour the miss requests
754 if (wq_entry
&& (writeBuffer
.isFull() || !miss_mshr
)) {
755 // need to search MSHR queue for conflicting earlier miss.
756 MSHR
*conflict_mshr
=
757 mshrQueue
.findPending(wq_entry
->blkAddr
,
760 if (conflict_mshr
&& conflict_mshr
->order
< wq_entry
->order
) {
761 // Service misses in order until conflict is cleared.
762 return conflict_mshr
;
764 // @todo Note that we ignore the ready time of the conflict here
767 // No conflicts; issue write
769 } else if (miss_mshr
) {
770 // need to check for conflicting earlier writeback
771 WriteQueueEntry
*conflict_mshr
=
772 writeBuffer
.findPending(miss_mshr
->blkAddr
,
773 miss_mshr
->isSecure
);
775 // not sure why we don't check order here... it was in the
776 // original code but commented out.
778 // The only way this happens is if we are
779 // doing a write and we didn't have permissions
780 // then subsequently saw a writeback (owned got evicted)
781 // We need to make sure to perform the writeback first
782 // To preserve the dirty data, then we can issue the write
784 // should we return wq_entry here instead? I.e. do we
785 // have to flush writes in order? I don't think so... not
786 // for Alpha anyway. Maybe for x86?
787 return conflict_mshr
;
789 // @todo Note that we ignore the ready time of the conflict here
792 // No conflicts; issue read
796 // fall through... no pending requests. Try a prefetch.
797 assert(!miss_mshr
&& !wq_entry
);
798 if (prefetcher
&& mshrQueue
.canPrefetch()) {
799 // If we have a miss queue slot, we can try a prefetch
800 PacketPtr pkt
= prefetcher
->getPacket();
802 Addr pf_addr
= pkt
->getBlockAddr(blkSize
);
803 if (!tags
->findBlock(pf_addr
, pkt
->isSecure()) &&
804 !mshrQueue
.findMatch(pf_addr
, pkt
->isSecure()) &&
805 !writeBuffer
.findMatch(pf_addr
, pkt
->isSecure())) {
806 // Update statistic on number of prefetches issued
807 // (hwpf_mshr_misses)
808 assert(pkt
->req
->masterId() < system
->maxMasters());
809 mshr_misses
[pkt
->cmdToIndex()][pkt
->req
->masterId()]++;
811 // allocate an MSHR and return it, note
812 // that we send the packet straight away, so do not
814 return allocateMissBuffer(pkt
, curTick(), false);
816 // free the request and packet
826 BaseCache::satisfyRequest(PacketPtr pkt
, CacheBlk
*blk
, bool, bool)
828 assert(pkt
->isRequest());
830 assert(blk
&& blk
->isValid());
831 // Occasionally this is not true... if we are a lower-level cache
832 // satisfying a string of Read and ReadEx requests from
833 // upper-level caches, a Read will mark the block as shared but we
834 // can satisfy a following ReadEx anyway since we can rely on the
835 // Read requester(s) to have buffered the ReadEx snoop and to
836 // invalidate their blocks after receiving them.
837 // assert(!pkt->needsWritable() || blk->isWritable());
838 assert(pkt
->getOffset(blkSize
) + pkt
->getSize() <= blkSize
);
840 // Check RMW operations first since both isRead() and
841 // isWrite() will be true for them
842 if (pkt
->cmd
== MemCmd::SwapReq
) {
843 if (pkt
->isAtomicOp()) {
844 // extract data from cache and save it into the data field in
845 // the packet as a return value from this atomic op
847 int offset
= tags
->extractBlkOffset(pkt
->getAddr());
848 uint8_t *blk_data
= blk
->data
+ offset
;
849 std::memcpy(pkt
->getPtr
<uint8_t>(), blk_data
, pkt
->getSize());
851 // execute AMO operation
852 (*(pkt
->getAtomicOp()))(blk_data
);
854 // set block status to dirty
855 blk
->status
|= BlkDirty
;
857 cmpAndSwap(blk
, pkt
);
859 } else if (pkt
->isWrite()) {
860 // we have the block in a writable state and can go ahead,
861 // note that the line may be also be considered writable in
862 // downstream caches along the path to memory, but always
863 // Exclusive, and never Modified
864 assert(blk
->isWritable());
865 // Write or WriteLine at the first cache with block in writable state
866 if (blk
->checkWrite(pkt
)) {
867 pkt
->writeDataToBlock(blk
->data
, blkSize
);
869 // Always mark the line as dirty (and thus transition to the
870 // Modified state) even if we are a failed StoreCond so we
871 // supply data to any snoops that have appended themselves to
872 // this cache before knowing the store will fail.
873 blk
->status
|= BlkDirty
;
874 DPRINTF(CacheVerbose
, "%s for %s (write)\n", __func__
, pkt
->print());
875 } else if (pkt
->isRead()) {
877 blk
->trackLoadLocked(pkt
);
880 // all read responses have a data payload
881 assert(pkt
->hasRespData());
882 pkt
->setDataFromBlock(blk
->data
, blkSize
);
883 } else if (pkt
->isUpgrade()) {
885 assert(!pkt
->hasSharers());
887 if (blk
->isDirty()) {
888 // we were in the Owned state, and a cache above us that
889 // has the line in Shared state needs to be made aware
890 // that the data it already has is in fact dirty
891 pkt
->setCacheResponding();
892 blk
->status
&= ~BlkDirty
;
894 } else if (pkt
->isClean()) {
895 blk
->status
&= ~BlkDirty
;
897 assert(pkt
->isInvalidate());
898 invalidateBlock(blk
);
899 DPRINTF(CacheVerbose
, "%s for %s (invalidation)\n", __func__
,
904 /////////////////////////////////////////////////////
906 // Access path: requests coming in from the CPU side
908 /////////////////////////////////////////////////////
911 BaseCache::access(PacketPtr pkt
, CacheBlk
*&blk
, Cycles
&lat
,
912 PacketList
&writebacks
)
915 assert(pkt
->isRequest());
917 chatty_assert(!(isReadOnly
&& pkt
->isWrite()),
918 "Should never see a write in a read-only cache %s\n",
921 // Here lat is the value passed as parameter to accessBlock() function
922 // that can modify its value.
923 blk
= tags
->accessBlock(pkt
->getAddr(), pkt
->isSecure(), lat
);
925 DPRINTF(Cache
, "%s for %s %s\n", __func__
, pkt
->print(),
926 blk
? "hit " + blk
->print() : "miss");
928 if (pkt
->req
->isCacheMaintenance()) {
929 // A cache maintenance operation is always forwarded to the
930 // memory below even if the block is found in dirty state.
932 // We defer any changes to the state of the block until we
933 // create and mark as in service the mshr for the downstream
938 if (pkt
->isEviction()) {
939 // We check for presence of block in above caches before issuing
940 // Writeback or CleanEvict to write buffer. Therefore the only
941 // possible cases can be of a CleanEvict packet coming from above
942 // encountering a Writeback generated in this cache peer cache and
943 // waiting in the write buffer. Cases of upper level peer caches
944 // generating CleanEvict and Writeback or simply CleanEvict and
945 // CleanEvict almost simultaneously will be caught by snoops sent out
947 WriteQueueEntry
*wb_entry
= writeBuffer
.findMatch(pkt
->getAddr(),
950 assert(wb_entry
->getNumTargets() == 1);
951 PacketPtr wbPkt
= wb_entry
->getTarget()->pkt
;
952 assert(wbPkt
->isWriteback());
954 if (pkt
->isCleanEviction()) {
955 // The CleanEvict and WritebackClean snoops into other
956 // peer caches of the same level while traversing the
957 // crossbar. If a copy of the block is found, the
958 // packet is deleted in the crossbar. Hence, none of
959 // the other upper level caches connected to this
960 // cache have the block, so we can clear the
961 // BLOCK_CACHED flag in the Writeback if set and
962 // discard the CleanEvict by returning true.
963 wbPkt
->clearBlockCached();
966 assert(pkt
->cmd
== MemCmd::WritebackDirty
);
967 // Dirty writeback from above trumps our clean
968 // writeback... discard here
969 // Note: markInService will remove entry from writeback buffer.
970 markInService(wb_entry
);
976 // Writeback handling is special case. We can write the block into
977 // the cache without having a writeable copy (or any copy at all).
978 if (pkt
->isWriteback()) {
979 assert(blkSize
== pkt
->getSize());
981 // we could get a clean writeback while we are having
982 // outstanding accesses to a block, do the simple thing for
983 // now and drop the clean writeback so that we do not upset
984 // any ordering/decisions about ownership already taken
985 if (pkt
->cmd
== MemCmd::WritebackClean
&&
986 mshrQueue
.findMatch(pkt
->getAddr(), pkt
->isSecure())) {
987 DPRINTF(Cache
, "Clean writeback %#llx to block with MSHR, "
988 "dropping\n", pkt
->getAddr());
993 // need to do a replacement
994 blk
= allocateBlock(pkt
, writebacks
);
996 // no replaceable block available: give up, fwd to next level.
1001 blk
->status
|= (BlkValid
| BlkReadable
);
1003 // only mark the block dirty if we got a writeback command,
1004 // and leave it as is for a clean writeback
1005 if (pkt
->cmd
== MemCmd::WritebackDirty
) {
1006 // TODO: the coherent cache can assert(!blk->isDirty());
1007 blk
->status
|= BlkDirty
;
1009 // if the packet does not have sharers, it is passing
1010 // writable, and we got the writeback in Modified or Exclusive
1011 // state, if not we are in the Owned or Shared state
1012 if (!pkt
->hasSharers()) {
1013 blk
->status
|= BlkWritable
;
1015 // nothing else to do; writeback doesn't expect response
1016 assert(!pkt
->needsResponse());
1017 pkt
->writeDataToBlock(blk
->data
, blkSize
);
1018 DPRINTF(Cache
, "%s new state is %s\n", __func__
, blk
->print());
1020 // populate the time when the block will be ready to access.
1021 blk
->whenReady
= clockEdge(fillLatency
) + pkt
->headerDelay
+
1024 } else if (pkt
->cmd
== MemCmd::CleanEvict
) {
1026 // Found the block in the tags, need to stop CleanEvict from
1027 // propagating further down the hierarchy. Returning true will
1028 // treat the CleanEvict like a satisfied write request and delete
1032 // We didn't find the block here, propagate the CleanEvict further
1033 // down the memory hierarchy. Returning false will treat the CleanEvict
1034 // like a Writeback which could not find a replaceable block so has to
1035 // go to next level.
1037 } else if (pkt
->cmd
== MemCmd::WriteClean
) {
1038 // WriteClean handling is a special case. We can allocate a
1039 // block directly if it doesn't exist and we can update the
1040 // block immediately. The WriteClean transfers the ownership
1041 // of the block as well.
1042 assert(blkSize
== pkt
->getSize());
1045 if (pkt
->writeThrough()) {
1046 // if this is a write through packet, we don't try to
1047 // allocate if the block is not present
1050 // a writeback that misses needs to allocate a new block
1051 blk
= allocateBlock(pkt
, writebacks
);
1053 // no replaceable block available: give up, fwd to
1059 blk
->status
|= (BlkValid
| BlkReadable
);
1063 // at this point either this is a writeback or a write-through
1064 // write clean operation and the block is already in this
1065 // cache, we need to update the data and the block flags
1067 // TODO: the coherent cache can assert(!blk->isDirty());
1068 if (!pkt
->writeThrough()) {
1069 blk
->status
|= BlkDirty
;
1071 // nothing else to do; writeback doesn't expect response
1072 assert(!pkt
->needsResponse());
1073 pkt
->writeDataToBlock(blk
->data
, blkSize
);
1074 DPRINTF(Cache
, "%s new state is %s\n", __func__
, blk
->print());
1077 // populate the time when the block will be ready to access.
1078 blk
->whenReady
= clockEdge(fillLatency
) + pkt
->headerDelay
+
1080 // if this a write-through packet it will be sent to cache
1082 return !pkt
->writeThrough();
1083 } else if (blk
&& (pkt
->needsWritable() ? blk
->isWritable() :
1084 blk
->isReadable())) {
1085 // OK to satisfy access
1087 satisfyRequest(pkt
, blk
);
1088 maintainClusivity(pkt
->fromCache(), blk
);
1093 // Can't satisfy access normally... either no block (blk == nullptr)
1094 // or have block but need writable
1098 if (!blk
&& pkt
->isLLSC() && pkt
->isWrite()) {
1099 // complete miss on store conditional... just give up now
1100 pkt
->req
->setExtraData(0);
1108 BaseCache::maintainClusivity(bool from_cache
, CacheBlk
*blk
)
1110 if (from_cache
&& blk
&& blk
->isValid() && !blk
->isDirty() &&
1111 clusivity
== Enums::mostly_excl
) {
1112 // if we have responded to a cache, and our block is still
1113 // valid, but not dirty, and this cache is mostly exclusive
1114 // with respect to the cache above, drop the block
1115 invalidateBlock(blk
);
1120 BaseCache::handleFill(PacketPtr pkt
, CacheBlk
*blk
, PacketList
&writebacks
,
1123 assert(pkt
->isResponse() || pkt
->cmd
== MemCmd::WriteLineReq
);
1124 Addr addr
= pkt
->getAddr();
1125 bool is_secure
= pkt
->isSecure();
1127 CacheBlk::State old_state
= blk
? blk
->status
: 0;
1130 // When handling a fill, we should have no writes to this line.
1131 assert(addr
== pkt
->getBlockAddr(blkSize
));
1132 assert(!writeBuffer
.findMatch(addr
, is_secure
));
1135 // better have read new data...
1136 assert(pkt
->hasData());
1138 // only read responses and write-line requests have data;
1139 // note that we don't write the data here for write-line - that
1140 // happens in the subsequent call to satisfyRequest
1141 assert(pkt
->isRead() || pkt
->cmd
== MemCmd::WriteLineReq
);
1143 // need to do a replacement if allocating, otherwise we stick
1144 // with the temporary storage
1145 blk
= allocate
? allocateBlock(pkt
, writebacks
) : nullptr;
1148 // No replaceable block or a mostly exclusive
1149 // cache... just use temporary storage to complete the
1150 // current request and then get rid of it
1151 assert(!tempBlock
->isValid());
1153 tempBlock
->insert(addr
, is_secure
);
1154 DPRINTF(Cache
, "using temp block for %#llx (%s)\n", addr
,
1155 is_secure
? "s" : "ns");
1158 // we should never be overwriting a valid block
1159 assert(!blk
->isValid());
1161 // existing block... probably an upgrade
1162 assert(regenerateBlkAddr(blk
) == addr
);
1163 assert(blk
->isSecure() == is_secure
);
1164 // either we're getting new data or the block should already be valid
1165 assert(pkt
->hasData() || blk
->isValid());
1166 // don't clear block status... if block is already dirty we
1167 // don't want to lose that
1170 blk
->status
|= BlkValid
| BlkReadable
;
1172 // sanity check for whole-line writes, which should always be
1173 // marked as writable as part of the fill, and then later marked
1174 // dirty as part of satisfyRequest
1175 if (pkt
->cmd
== MemCmd::WriteLineReq
) {
1176 assert(!pkt
->hasSharers());
1179 // here we deal with setting the appropriate state of the line,
1180 // and we start by looking at the hasSharers flag, and ignore the
1181 // cacheResponding flag (normally signalling dirty data) if the
1182 // packet has sharers, thus the line is never allocated as Owned
1183 // (dirty but not writable), and always ends up being either
1184 // Shared, Exclusive or Modified, see Packet::setCacheResponding
1186 if (!pkt
->hasSharers()) {
1187 // we could get a writable line from memory (rather than a
1188 // cache) even in a read-only cache, note that we set this bit
1189 // even for a read-only cache, possibly revisit this decision
1190 blk
->status
|= BlkWritable
;
1192 // check if we got this via cache-to-cache transfer (i.e., from a
1193 // cache that had the block in Modified or Owned state)
1194 if (pkt
->cacheResponding()) {
1195 // we got the block in Modified state, and invalidated the
1197 blk
->status
|= BlkDirty
;
1199 chatty_assert(!isReadOnly
, "Should never see dirty snoop response "
1200 "in read-only cache %s\n", name());
1204 DPRINTF(Cache
, "Block addr %#llx (%s) moving from state %x to %s\n",
1205 addr
, is_secure
? "s" : "ns", old_state
, blk
->print());
1207 // if we got new data, copy it in (checking for a read response
1208 // and a response that has data is the same in the end)
1209 if (pkt
->isRead()) {
1211 assert(pkt
->hasData());
1212 assert(pkt
->getSize() == blkSize
);
1214 pkt
->writeDataToBlock(blk
->data
, blkSize
);
1216 // We pay for fillLatency here.
1217 blk
->whenReady
= clockEdge() + fillLatency
* clockPeriod() +
1224 BaseCache::allocateBlock(const PacketPtr pkt
, PacketList
&writebacks
)
1227 const Addr addr
= pkt
->getAddr();
1230 const bool is_secure
= pkt
->isSecure();
1232 // Find replacement victim
1233 std::vector
<CacheBlk
*> evict_blks
;
1234 CacheBlk
*victim
= tags
->findVictim(addr
, is_secure
, evict_blks
);
1236 // It is valid to return nullptr if there is no victim
1240 // Check for transient state allocations. If any of the entries listed
1241 // for eviction has a transient state, the allocation fails
1242 for (const auto& blk
: evict_blks
) {
1243 if (blk
->isValid()) {
1244 Addr repl_addr
= regenerateBlkAddr(blk
);
1245 MSHR
*repl_mshr
= mshrQueue
.findMatch(repl_addr
, blk
->isSecure());
1247 // must be an outstanding upgrade or clean request
1248 // on a block we're about to replace...
1249 assert((!blk
->isWritable() && repl_mshr
->needsWritable()) ||
1250 repl_mshr
->isCleaning());
1252 // too hard to replace block with transient state
1253 // allocation failed, block not inserted
1259 // The victim will be replaced by a new entry, so increase the replacement
1260 // counter if a valid block is being replaced
1261 if (victim
->isValid()) {
1262 DPRINTF(Cache
, "replacement: replacing %#llx (%s) with %#llx "
1263 "(%s): %s\n", regenerateBlkAddr(victim
),
1264 victim
->isSecure() ? "s" : "ns",
1265 addr
, is_secure
? "s" : "ns",
1266 victim
->isDirty() ? "writeback" : "clean");
1271 // Evict valid blocks associated to this victim block
1272 for (const auto& blk
: evict_blks
) {
1273 if (blk
->isValid()) {
1274 if (blk
->wasPrefetched()) {
1278 evictBlock(blk
, writebacks
);
1282 // Insert new block at victimized entry
1283 tags
->insertBlock(pkt
, victim
);
1289 BaseCache::invalidateBlock(CacheBlk
*blk
)
1291 if (blk
!= tempBlock
)
1292 tags
->invalidate(blk
);
1297 BaseCache::writebackBlk(CacheBlk
*blk
)
1299 chatty_assert(!isReadOnly
|| writebackClean
,
1300 "Writeback from read-only cache");
1301 assert(blk
&& blk
->isValid() && (blk
->isDirty() || writebackClean
));
1303 writebacks
[Request::wbMasterId
]++;
1305 RequestPtr req
= std::make_shared
<Request
>(
1306 regenerateBlkAddr(blk
), blkSize
, 0, Request::wbMasterId
);
1308 if (blk
->isSecure())
1309 req
->setFlags(Request::SECURE
);
1311 req
->taskId(blk
->task_id
);
1314 new Packet(req
, blk
->isDirty() ?
1315 MemCmd::WritebackDirty
: MemCmd::WritebackClean
);
1317 DPRINTF(Cache
, "Create Writeback %s writable: %d, dirty: %d\n",
1318 pkt
->print(), blk
->isWritable(), blk
->isDirty());
1320 if (blk
->isWritable()) {
1321 // not asserting shared means we pass the block in modified
1322 // state, mark our own block non-writeable
1323 blk
->status
&= ~BlkWritable
;
1325 // we are in the Owned state, tell the receiver
1326 pkt
->setHasSharers();
1329 // make sure the block is not marked dirty
1330 blk
->status
&= ~BlkDirty
;
1333 pkt
->setDataFromBlock(blk
->data
, blkSize
);
1339 BaseCache::writecleanBlk(CacheBlk
*blk
, Request::Flags dest
, PacketId id
)
1341 RequestPtr req
= std::make_shared
<Request
>(
1342 regenerateBlkAddr(blk
), blkSize
, 0, Request::wbMasterId
);
1344 if (blk
->isSecure()) {
1345 req
->setFlags(Request::SECURE
);
1347 req
->taskId(blk
->task_id
);
1349 PacketPtr pkt
= new Packet(req
, MemCmd::WriteClean
, blkSize
, id
);
1352 req
->setFlags(dest
);
1353 pkt
->setWriteThrough();
1356 DPRINTF(Cache
, "Create %s writable: %d, dirty: %d\n", pkt
->print(),
1357 blk
->isWritable(), blk
->isDirty());
1359 if (blk
->isWritable()) {
1360 // not asserting shared means we pass the block in modified
1361 // state, mark our own block non-writeable
1362 blk
->status
&= ~BlkWritable
;
1364 // we are in the Owned state, tell the receiver
1365 pkt
->setHasSharers();
1368 // make sure the block is not marked dirty
1369 blk
->status
&= ~BlkDirty
;
1372 pkt
->setDataFromBlock(blk
->data
, blkSize
);
1379 BaseCache::memWriteback()
1381 tags
->forEachBlk([this](CacheBlk
&blk
) { writebackVisitor(blk
); });
1385 BaseCache::memInvalidate()
1387 tags
->forEachBlk([this](CacheBlk
&blk
) { invalidateVisitor(blk
); });
1391 BaseCache::isDirty() const
1393 return tags
->anyBlk([](CacheBlk
&blk
) { return blk
.isDirty(); });
1397 BaseCache::writebackVisitor(CacheBlk
&blk
)
1399 if (blk
.isDirty()) {
1400 assert(blk
.isValid());
1402 RequestPtr request
= std::make_shared
<Request
>(
1403 regenerateBlkAddr(&blk
), blkSize
, 0, Request::funcMasterId
);
1405 request
->taskId(blk
.task_id
);
1406 if (blk
.isSecure()) {
1407 request
->setFlags(Request::SECURE
);
1410 Packet
packet(request
, MemCmd::WriteReq
);
1411 packet
.dataStatic(blk
.data
);
1413 memSidePort
.sendFunctional(&packet
);
1415 blk
.status
&= ~BlkDirty
;
1420 BaseCache::invalidateVisitor(CacheBlk
&blk
)
1423 warn_once("Invalidating dirty cache lines. " \
1424 "Expect things to break.\n");
1426 if (blk
.isValid()) {
1427 assert(!blk
.isDirty());
1428 invalidateBlock(&blk
);
1433 BaseCache::nextQueueReadyTime() const
1435 Tick nextReady
= std::min(mshrQueue
.nextReadyTime(),
1436 writeBuffer
.nextReadyTime());
1438 // Don't signal prefetch ready time if no MSHRs available
1439 // Will signal once enoguh MSHRs are deallocated
1440 if (prefetcher
&& mshrQueue
.canPrefetch()) {
1441 nextReady
= std::min(nextReady
,
1442 prefetcher
->nextPrefetchReadyTime());
1450 BaseCache::sendMSHRQueuePacket(MSHR
* mshr
)
1454 // use request from 1st target
1455 PacketPtr tgt_pkt
= mshr
->getTarget()->pkt
;
1457 DPRINTF(Cache
, "%s: MSHR %s\n", __func__
, tgt_pkt
->print());
1459 CacheBlk
*blk
= tags
->findBlock(mshr
->blkAddr
, mshr
->isSecure
);
1461 // either a prefetch that is not present upstream, or a normal
1462 // MSHR request, proceed to get the packet to send downstream
1463 PacketPtr pkt
= createMissPacket(tgt_pkt
, blk
, mshr
->needsWritable());
1465 mshr
->isForward
= (pkt
== nullptr);
1467 if (mshr
->isForward
) {
1468 // not a cache block request, but a response is expected
1469 // make copy of current packet to forward, keep current
1470 // copy for response handling
1471 pkt
= new Packet(tgt_pkt
, false, true);
1472 assert(!pkt
->isWrite());
1475 // play it safe and append (rather than set) the sender state,
1476 // as forwarded packets may already have existing state
1477 pkt
->pushSenderState(mshr
);
1479 if (pkt
->isClean() && blk
&& blk
->isDirty()) {
1480 // A cache clean opearation is looking for a dirty block. Mark
1481 // the packet so that the destination xbar can determine that
1482 // there will be a follow-up write packet as well.
1483 pkt
->setSatisfied();
1486 if (!memSidePort
.sendTimingReq(pkt
)) {
1487 // we are awaiting a retry, but we
1488 // delete the packet and will be creating a new packet
1489 // when we get the opportunity
1492 // note that we have now masked any requestBus and
1493 // schedSendEvent (we will wait for a retry before
1494 // doing anything), and this is so even if we do not
1495 // care about this packet and might override it before
1499 // As part of the call to sendTimingReq the packet is
1500 // forwarded to all neighbouring caches (and any caches
1501 // above them) as a snoop. Thus at this point we know if
1502 // any of the neighbouring caches are responding, and if
1503 // so, we know it is dirty, and we can determine if it is
1504 // being passed as Modified, making our MSHR the ordering
1506 bool pending_modified_resp
= !pkt
->hasSharers() &&
1507 pkt
->cacheResponding();
1508 markInService(mshr
, pending_modified_resp
);
1510 if (pkt
->isClean() && blk
&& blk
->isDirty()) {
1511 // A cache clean opearation is looking for a dirty
1512 // block. If a dirty block is encountered a WriteClean
1513 // will update any copies to the path to the memory
1514 // until the point of reference.
1515 DPRINTF(CacheVerbose
, "%s: packet %s found block: %s\n",
1516 __func__
, pkt
->print(), blk
->print());
1517 PacketPtr wb_pkt
= writecleanBlk(blk
, pkt
->req
->getDest(),
1519 PacketList writebacks
;
1520 writebacks
.push_back(wb_pkt
);
1521 doWritebacks(writebacks
, 0);
1529 BaseCache::sendWriteQueuePacket(WriteQueueEntry
* wq_entry
)
1533 // always a single target for write queue entries
1534 PacketPtr tgt_pkt
= wq_entry
->getTarget()->pkt
;
1536 DPRINTF(Cache
, "%s: write %s\n", __func__
, tgt_pkt
->print());
1538 // forward as is, both for evictions and uncacheable writes
1539 if (!memSidePort
.sendTimingReq(tgt_pkt
)) {
1540 // note that we have now masked any requestBus and
1541 // schedSendEvent (we will wait for a retry before
1542 // doing anything), and this is so even if we do not
1543 // care about this packet and might override it before
1547 markInService(wq_entry
);
1553 BaseCache::serialize(CheckpointOut
&cp
) const
1555 bool dirty(isDirty());
1558 warn("*** The cache still contains dirty data. ***\n");
1559 warn(" Make sure to drain the system using the correct flags.\n");
1560 warn(" This checkpoint will not restore correctly " \
1561 "and dirty data in the cache will be lost!\n");
1564 // Since we don't checkpoint the data in the cache, any dirty data
1565 // will be lost when restoring from a checkpoint of a system that
1566 // wasn't drained properly. Flag the checkpoint as invalid if the
1567 // cache contains dirty data.
1568 bool bad_checkpoint(dirty
);
1569 SERIALIZE_SCALAR(bad_checkpoint
);
1573 BaseCache::unserialize(CheckpointIn
&cp
)
1575 bool bad_checkpoint
;
1576 UNSERIALIZE_SCALAR(bad_checkpoint
);
1577 if (bad_checkpoint
) {
1578 fatal("Restoring from checkpoints with dirty caches is not "
1579 "supported in the classic memory system. Please remove any "
1580 "caches or drain them properly before taking checkpoints.\n");
1585 BaseCache::regStats()
1587 MemObject::regStats();
1589 using namespace Stats
;
1592 for (int access_idx
= 0; access_idx
< MemCmd::NUM_MEM_CMDS
; ++access_idx
) {
1593 MemCmd
cmd(access_idx
);
1594 const string
&cstr
= cmd
.toString();
1597 .init(system
->maxMasters())
1598 .name(name() + "." + cstr
+ "_hits")
1599 .desc("number of " + cstr
+ " hits")
1600 .flags(total
| nozero
| nonan
)
1602 for (int i
= 0; i
< system
->maxMasters(); i
++) {
1603 hits
[access_idx
].subname(i
, system
->getMasterName(i
));
1607 // These macros make it easier to sum the right subset of commands and
1608 // to change the subset of commands that are considered "demand" vs
1610 #define SUM_DEMAND(s) \
1611 (s[MemCmd::ReadReq] + s[MemCmd::WriteReq] + s[MemCmd::WriteLineReq] + \
1612 s[MemCmd::ReadExReq] + s[MemCmd::ReadCleanReq] + s[MemCmd::ReadSharedReq])
1614 // should writebacks be included here? prior code was inconsistent...
1615 #define SUM_NON_DEMAND(s) \
1616 (s[MemCmd::SoftPFReq] + s[MemCmd::HardPFReq])
1619 .name(name() + ".demand_hits")
1620 .desc("number of demand (read+write) hits")
1621 .flags(total
| nozero
| nonan
)
1623 demandHits
= SUM_DEMAND(hits
);
1624 for (int i
= 0; i
< system
->maxMasters(); i
++) {
1625 demandHits
.subname(i
, system
->getMasterName(i
));
1629 .name(name() + ".overall_hits")
1630 .desc("number of overall hits")
1631 .flags(total
| nozero
| nonan
)
1633 overallHits
= demandHits
+ SUM_NON_DEMAND(hits
);
1634 for (int i
= 0; i
< system
->maxMasters(); i
++) {
1635 overallHits
.subname(i
, system
->getMasterName(i
));
1639 for (int access_idx
= 0; access_idx
< MemCmd::NUM_MEM_CMDS
; ++access_idx
) {
1640 MemCmd
cmd(access_idx
);
1641 const string
&cstr
= cmd
.toString();
1644 .init(system
->maxMasters())
1645 .name(name() + "." + cstr
+ "_misses")
1646 .desc("number of " + cstr
+ " misses")
1647 .flags(total
| nozero
| nonan
)
1649 for (int i
= 0; i
< system
->maxMasters(); i
++) {
1650 misses
[access_idx
].subname(i
, system
->getMasterName(i
));
1655 .name(name() + ".demand_misses")
1656 .desc("number of demand (read+write) misses")
1657 .flags(total
| nozero
| nonan
)
1659 demandMisses
= SUM_DEMAND(misses
);
1660 for (int i
= 0; i
< system
->maxMasters(); i
++) {
1661 demandMisses
.subname(i
, system
->getMasterName(i
));
1665 .name(name() + ".overall_misses")
1666 .desc("number of overall misses")
1667 .flags(total
| nozero
| nonan
)
1669 overallMisses
= demandMisses
+ SUM_NON_DEMAND(misses
);
1670 for (int i
= 0; i
< system
->maxMasters(); i
++) {
1671 overallMisses
.subname(i
, system
->getMasterName(i
));
1674 // Miss latency statistics
1675 for (int access_idx
= 0; access_idx
< MemCmd::NUM_MEM_CMDS
; ++access_idx
) {
1676 MemCmd
cmd(access_idx
);
1677 const string
&cstr
= cmd
.toString();
1679 missLatency
[access_idx
]
1680 .init(system
->maxMasters())
1681 .name(name() + "." + cstr
+ "_miss_latency")
1682 .desc("number of " + cstr
+ " miss cycles")
1683 .flags(total
| nozero
| nonan
)
1685 for (int i
= 0; i
< system
->maxMasters(); i
++) {
1686 missLatency
[access_idx
].subname(i
, system
->getMasterName(i
));
1691 .name(name() + ".demand_miss_latency")
1692 .desc("number of demand (read+write) miss cycles")
1693 .flags(total
| nozero
| nonan
)
1695 demandMissLatency
= SUM_DEMAND(missLatency
);
1696 for (int i
= 0; i
< system
->maxMasters(); i
++) {
1697 demandMissLatency
.subname(i
, system
->getMasterName(i
));
1701 .name(name() + ".overall_miss_latency")
1702 .desc("number of overall miss cycles")
1703 .flags(total
| nozero
| nonan
)
1705 overallMissLatency
= demandMissLatency
+ SUM_NON_DEMAND(missLatency
);
1706 for (int i
= 0; i
< system
->maxMasters(); i
++) {
1707 overallMissLatency
.subname(i
, system
->getMasterName(i
));
1711 for (int access_idx
= 0; access_idx
< MemCmd::NUM_MEM_CMDS
; ++access_idx
) {
1712 MemCmd
cmd(access_idx
);
1713 const string
&cstr
= cmd
.toString();
1715 accesses
[access_idx
]
1716 .name(name() + "." + cstr
+ "_accesses")
1717 .desc("number of " + cstr
+ " accesses(hits+misses)")
1718 .flags(total
| nozero
| nonan
)
1720 accesses
[access_idx
] = hits
[access_idx
] + misses
[access_idx
];
1722 for (int i
= 0; i
< system
->maxMasters(); i
++) {
1723 accesses
[access_idx
].subname(i
, system
->getMasterName(i
));
1728 .name(name() + ".demand_accesses")
1729 .desc("number of demand (read+write) accesses")
1730 .flags(total
| nozero
| nonan
)
1732 demandAccesses
= demandHits
+ demandMisses
;
1733 for (int i
= 0; i
< system
->maxMasters(); i
++) {
1734 demandAccesses
.subname(i
, system
->getMasterName(i
));
1738 .name(name() + ".overall_accesses")
1739 .desc("number of overall (read+write) accesses")
1740 .flags(total
| nozero
| nonan
)
1742 overallAccesses
= overallHits
+ overallMisses
;
1743 for (int i
= 0; i
< system
->maxMasters(); i
++) {
1744 overallAccesses
.subname(i
, system
->getMasterName(i
));
1747 // miss rate formulas
1748 for (int access_idx
= 0; access_idx
< MemCmd::NUM_MEM_CMDS
; ++access_idx
) {
1749 MemCmd
cmd(access_idx
);
1750 const string
&cstr
= cmd
.toString();
1752 missRate
[access_idx
]
1753 .name(name() + "." + cstr
+ "_miss_rate")
1754 .desc("miss rate for " + cstr
+ " accesses")
1755 .flags(total
| nozero
| nonan
)
1757 missRate
[access_idx
] = misses
[access_idx
] / accesses
[access_idx
];
1759 for (int i
= 0; i
< system
->maxMasters(); i
++) {
1760 missRate
[access_idx
].subname(i
, system
->getMasterName(i
));
1765 .name(name() + ".demand_miss_rate")
1766 .desc("miss rate for demand accesses")
1767 .flags(total
| nozero
| nonan
)
1769 demandMissRate
= demandMisses
/ demandAccesses
;
1770 for (int i
= 0; i
< system
->maxMasters(); i
++) {
1771 demandMissRate
.subname(i
, system
->getMasterName(i
));
1775 .name(name() + ".overall_miss_rate")
1776 .desc("miss rate for overall accesses")
1777 .flags(total
| nozero
| nonan
)
1779 overallMissRate
= overallMisses
/ overallAccesses
;
1780 for (int i
= 0; i
< system
->maxMasters(); i
++) {
1781 overallMissRate
.subname(i
, system
->getMasterName(i
));
1784 // miss latency formulas
1785 for (int access_idx
= 0; access_idx
< MemCmd::NUM_MEM_CMDS
; ++access_idx
) {
1786 MemCmd
cmd(access_idx
);
1787 const string
&cstr
= cmd
.toString();
1789 avgMissLatency
[access_idx
]
1790 .name(name() + "." + cstr
+ "_avg_miss_latency")
1791 .desc("average " + cstr
+ " miss latency")
1792 .flags(total
| nozero
| nonan
)
1794 avgMissLatency
[access_idx
] =
1795 missLatency
[access_idx
] / misses
[access_idx
];
1797 for (int i
= 0; i
< system
->maxMasters(); i
++) {
1798 avgMissLatency
[access_idx
].subname(i
, system
->getMasterName(i
));
1802 demandAvgMissLatency
1803 .name(name() + ".demand_avg_miss_latency")
1804 .desc("average overall miss latency")
1805 .flags(total
| nozero
| nonan
)
1807 demandAvgMissLatency
= demandMissLatency
/ demandMisses
;
1808 for (int i
= 0; i
< system
->maxMasters(); i
++) {
1809 demandAvgMissLatency
.subname(i
, system
->getMasterName(i
));
1812 overallAvgMissLatency
1813 .name(name() + ".overall_avg_miss_latency")
1814 .desc("average overall miss latency")
1815 .flags(total
| nozero
| nonan
)
1817 overallAvgMissLatency
= overallMissLatency
/ overallMisses
;
1818 for (int i
= 0; i
< system
->maxMasters(); i
++) {
1819 overallAvgMissLatency
.subname(i
, system
->getMasterName(i
));
1822 blocked_cycles
.init(NUM_BLOCKED_CAUSES
);
1824 .name(name() + ".blocked_cycles")
1825 .desc("number of cycles access was blocked")
1826 .subname(Blocked_NoMSHRs
, "no_mshrs")
1827 .subname(Blocked_NoTargets
, "no_targets")
1831 blocked_causes
.init(NUM_BLOCKED_CAUSES
);
1833 .name(name() + ".blocked")
1834 .desc("number of cycles access was blocked")
1835 .subname(Blocked_NoMSHRs
, "no_mshrs")
1836 .subname(Blocked_NoTargets
, "no_targets")
1840 .name(name() + ".avg_blocked_cycles")
1841 .desc("average number of cycles each access was blocked")
1842 .subname(Blocked_NoMSHRs
, "no_mshrs")
1843 .subname(Blocked_NoTargets
, "no_targets")
1846 avg_blocked
= blocked_cycles
/ blocked_causes
;
1849 .name(name() + ".unused_prefetches")
1850 .desc("number of HardPF blocks evicted w/o reference")
1855 .init(system
->maxMasters())
1856 .name(name() + ".writebacks")
1857 .desc("number of writebacks")
1858 .flags(total
| nozero
| nonan
)
1860 for (int i
= 0; i
< system
->maxMasters(); i
++) {
1861 writebacks
.subname(i
, system
->getMasterName(i
));
1865 // MSHR hit statistics
1866 for (int access_idx
= 0; access_idx
< MemCmd::NUM_MEM_CMDS
; ++access_idx
) {
1867 MemCmd
cmd(access_idx
);
1868 const string
&cstr
= cmd
.toString();
1870 mshr_hits
[access_idx
]
1871 .init(system
->maxMasters())
1872 .name(name() + "." + cstr
+ "_mshr_hits")
1873 .desc("number of " + cstr
+ " MSHR hits")
1874 .flags(total
| nozero
| nonan
)
1876 for (int i
= 0; i
< system
->maxMasters(); i
++) {
1877 mshr_hits
[access_idx
].subname(i
, system
->getMasterName(i
));
1882 .name(name() + ".demand_mshr_hits")
1883 .desc("number of demand (read+write) MSHR hits")
1884 .flags(total
| nozero
| nonan
)
1886 demandMshrHits
= SUM_DEMAND(mshr_hits
);
1887 for (int i
= 0; i
< system
->maxMasters(); i
++) {
1888 demandMshrHits
.subname(i
, system
->getMasterName(i
));
1892 .name(name() + ".overall_mshr_hits")
1893 .desc("number of overall MSHR hits")
1894 .flags(total
| nozero
| nonan
)
1896 overallMshrHits
= demandMshrHits
+ SUM_NON_DEMAND(mshr_hits
);
1897 for (int i
= 0; i
< system
->maxMasters(); i
++) {
1898 overallMshrHits
.subname(i
, system
->getMasterName(i
));
1901 // MSHR miss statistics
1902 for (int access_idx
= 0; access_idx
< MemCmd::NUM_MEM_CMDS
; ++access_idx
) {
1903 MemCmd
cmd(access_idx
);
1904 const string
&cstr
= cmd
.toString();
1906 mshr_misses
[access_idx
]
1907 .init(system
->maxMasters())
1908 .name(name() + "." + cstr
+ "_mshr_misses")
1909 .desc("number of " + cstr
+ " MSHR misses")
1910 .flags(total
| nozero
| nonan
)
1912 for (int i
= 0; i
< system
->maxMasters(); i
++) {
1913 mshr_misses
[access_idx
].subname(i
, system
->getMasterName(i
));
1918 .name(name() + ".demand_mshr_misses")
1919 .desc("number of demand (read+write) MSHR misses")
1920 .flags(total
| nozero
| nonan
)
1922 demandMshrMisses
= SUM_DEMAND(mshr_misses
);
1923 for (int i
= 0; i
< system
->maxMasters(); i
++) {
1924 demandMshrMisses
.subname(i
, system
->getMasterName(i
));
1928 .name(name() + ".overall_mshr_misses")
1929 .desc("number of overall MSHR misses")
1930 .flags(total
| nozero
| nonan
)
1932 overallMshrMisses
= demandMshrMisses
+ SUM_NON_DEMAND(mshr_misses
);
1933 for (int i
= 0; i
< system
->maxMasters(); i
++) {
1934 overallMshrMisses
.subname(i
, system
->getMasterName(i
));
1937 // MSHR miss latency statistics
1938 for (int access_idx
= 0; access_idx
< MemCmd::NUM_MEM_CMDS
; ++access_idx
) {
1939 MemCmd
cmd(access_idx
);
1940 const string
&cstr
= cmd
.toString();
1942 mshr_miss_latency
[access_idx
]
1943 .init(system
->maxMasters())
1944 .name(name() + "." + cstr
+ "_mshr_miss_latency")
1945 .desc("number of " + cstr
+ " MSHR miss cycles")
1946 .flags(total
| nozero
| nonan
)
1948 for (int i
= 0; i
< system
->maxMasters(); i
++) {
1949 mshr_miss_latency
[access_idx
].subname(i
, system
->getMasterName(i
));
1953 demandMshrMissLatency
1954 .name(name() + ".demand_mshr_miss_latency")
1955 .desc("number of demand (read+write) MSHR miss cycles")
1956 .flags(total
| nozero
| nonan
)
1958 demandMshrMissLatency
= SUM_DEMAND(mshr_miss_latency
);
1959 for (int i
= 0; i
< system
->maxMasters(); i
++) {
1960 demandMshrMissLatency
.subname(i
, system
->getMasterName(i
));
1963 overallMshrMissLatency
1964 .name(name() + ".overall_mshr_miss_latency")
1965 .desc("number of overall MSHR miss cycles")
1966 .flags(total
| nozero
| nonan
)
1968 overallMshrMissLatency
=
1969 demandMshrMissLatency
+ SUM_NON_DEMAND(mshr_miss_latency
);
1970 for (int i
= 0; i
< system
->maxMasters(); i
++) {
1971 overallMshrMissLatency
.subname(i
, system
->getMasterName(i
));
1974 // MSHR uncacheable statistics
1975 for (int access_idx
= 0; access_idx
< MemCmd::NUM_MEM_CMDS
; ++access_idx
) {
1976 MemCmd
cmd(access_idx
);
1977 const string
&cstr
= cmd
.toString();
1979 mshr_uncacheable
[access_idx
]
1980 .init(system
->maxMasters())
1981 .name(name() + "." + cstr
+ "_mshr_uncacheable")
1982 .desc("number of " + cstr
+ " MSHR uncacheable")
1983 .flags(total
| nozero
| nonan
)
1985 for (int i
= 0; i
< system
->maxMasters(); i
++) {
1986 mshr_uncacheable
[access_idx
].subname(i
, system
->getMasterName(i
));
1990 overallMshrUncacheable
1991 .name(name() + ".overall_mshr_uncacheable_misses")
1992 .desc("number of overall MSHR uncacheable misses")
1993 .flags(total
| nozero
| nonan
)
1995 overallMshrUncacheable
=
1996 SUM_DEMAND(mshr_uncacheable
) + SUM_NON_DEMAND(mshr_uncacheable
);
1997 for (int i
= 0; i
< system
->maxMasters(); i
++) {
1998 overallMshrUncacheable
.subname(i
, system
->getMasterName(i
));
2001 // MSHR miss latency statistics
2002 for (int access_idx
= 0; access_idx
< MemCmd::NUM_MEM_CMDS
; ++access_idx
) {
2003 MemCmd
cmd(access_idx
);
2004 const string
&cstr
= cmd
.toString();
2006 mshr_uncacheable_lat
[access_idx
]
2007 .init(system
->maxMasters())
2008 .name(name() + "." + cstr
+ "_mshr_uncacheable_latency")
2009 .desc("number of " + cstr
+ " MSHR uncacheable cycles")
2010 .flags(total
| nozero
| nonan
)
2012 for (int i
= 0; i
< system
->maxMasters(); i
++) {
2013 mshr_uncacheable_lat
[access_idx
].subname(
2014 i
, system
->getMasterName(i
));
2018 overallMshrUncacheableLatency
2019 .name(name() + ".overall_mshr_uncacheable_latency")
2020 .desc("number of overall MSHR uncacheable cycles")
2021 .flags(total
| nozero
| nonan
)
2023 overallMshrUncacheableLatency
=
2024 SUM_DEMAND(mshr_uncacheable_lat
) +
2025 SUM_NON_DEMAND(mshr_uncacheable_lat
);
2026 for (int i
= 0; i
< system
->maxMasters(); i
++) {
2027 overallMshrUncacheableLatency
.subname(i
, system
->getMasterName(i
));
2031 // MSHR access formulas
2032 for (int access_idx
= 0; access_idx
< MemCmd::NUM_MEM_CMDS
; ++access_idx
) {
2033 MemCmd
cmd(access_idx
);
2034 const string
&cstr
= cmd
.toString();
2036 mshrAccesses
[access_idx
]
2037 .name(name() + "." + cstr
+ "_mshr_accesses")
2038 .desc("number of " + cstr
+ " mshr accesses(hits+misses)")
2039 .flags(total
| nozero
| nonan
)
2041 mshrAccesses
[access_idx
] =
2042 mshr_hits
[access_idx
] + mshr_misses
[access_idx
]
2043 + mshr_uncacheable
[access_idx
];
2047 .name(name() + ".demand_mshr_accesses")
2048 .desc("number of demand (read+write) mshr accesses")
2049 .flags(total
| nozero
| nonan
)
2051 demandMshrAccesses
= demandMshrHits
+ demandMshrMisses
;
2054 .name(name() + ".overall_mshr_accesses")
2055 .desc("number of overall (read+write) mshr accesses")
2056 .flags(total
| nozero
| nonan
)
2058 overallMshrAccesses
= overallMshrHits
+ overallMshrMisses
2059 + overallMshrUncacheable
;
2062 // MSHR miss rate formulas
2063 for (int access_idx
= 0; access_idx
< MemCmd::NUM_MEM_CMDS
; ++access_idx
) {
2064 MemCmd
cmd(access_idx
);
2065 const string
&cstr
= cmd
.toString();
2067 mshrMissRate
[access_idx
]
2068 .name(name() + "." + cstr
+ "_mshr_miss_rate")
2069 .desc("mshr miss rate for " + cstr
+ " accesses")
2070 .flags(total
| nozero
| nonan
)
2072 mshrMissRate
[access_idx
] =
2073 mshr_misses
[access_idx
] / accesses
[access_idx
];
2075 for (int i
= 0; i
< system
->maxMasters(); i
++) {
2076 mshrMissRate
[access_idx
].subname(i
, system
->getMasterName(i
));
2081 .name(name() + ".demand_mshr_miss_rate")
2082 .desc("mshr miss rate for demand accesses")
2083 .flags(total
| nozero
| nonan
)
2085 demandMshrMissRate
= demandMshrMisses
/ demandAccesses
;
2086 for (int i
= 0; i
< system
->maxMasters(); i
++) {
2087 demandMshrMissRate
.subname(i
, system
->getMasterName(i
));
2091 .name(name() + ".overall_mshr_miss_rate")
2092 .desc("mshr miss rate for overall accesses")
2093 .flags(total
| nozero
| nonan
)
2095 overallMshrMissRate
= overallMshrMisses
/ overallAccesses
;
2096 for (int i
= 0; i
< system
->maxMasters(); i
++) {
2097 overallMshrMissRate
.subname(i
, system
->getMasterName(i
));
2100 // mshrMiss latency formulas
2101 for (int access_idx
= 0; access_idx
< MemCmd::NUM_MEM_CMDS
; ++access_idx
) {
2102 MemCmd
cmd(access_idx
);
2103 const string
&cstr
= cmd
.toString();
2105 avgMshrMissLatency
[access_idx
]
2106 .name(name() + "." + cstr
+ "_avg_mshr_miss_latency")
2107 .desc("average " + cstr
+ " mshr miss latency")
2108 .flags(total
| nozero
| nonan
)
2110 avgMshrMissLatency
[access_idx
] =
2111 mshr_miss_latency
[access_idx
] / mshr_misses
[access_idx
];
2113 for (int i
= 0; i
< system
->maxMasters(); i
++) {
2114 avgMshrMissLatency
[access_idx
].subname(
2115 i
, system
->getMasterName(i
));
2119 demandAvgMshrMissLatency
2120 .name(name() + ".demand_avg_mshr_miss_latency")
2121 .desc("average overall mshr miss latency")
2122 .flags(total
| nozero
| nonan
)
2124 demandAvgMshrMissLatency
= demandMshrMissLatency
/ demandMshrMisses
;
2125 for (int i
= 0; i
< system
->maxMasters(); i
++) {
2126 demandAvgMshrMissLatency
.subname(i
, system
->getMasterName(i
));
2129 overallAvgMshrMissLatency
2130 .name(name() + ".overall_avg_mshr_miss_latency")
2131 .desc("average overall mshr miss latency")
2132 .flags(total
| nozero
| nonan
)
2134 overallAvgMshrMissLatency
= overallMshrMissLatency
/ overallMshrMisses
;
2135 for (int i
= 0; i
< system
->maxMasters(); i
++) {
2136 overallAvgMshrMissLatency
.subname(i
, system
->getMasterName(i
));
2139 // mshrUncacheable latency formulas
2140 for (int access_idx
= 0; access_idx
< MemCmd::NUM_MEM_CMDS
; ++access_idx
) {
2141 MemCmd
cmd(access_idx
);
2142 const string
&cstr
= cmd
.toString();
2144 avgMshrUncacheableLatency
[access_idx
]
2145 .name(name() + "." + cstr
+ "_avg_mshr_uncacheable_latency")
2146 .desc("average " + cstr
+ " mshr uncacheable latency")
2147 .flags(total
| nozero
| nonan
)
2149 avgMshrUncacheableLatency
[access_idx
] =
2150 mshr_uncacheable_lat
[access_idx
] / mshr_uncacheable
[access_idx
];
2152 for (int i
= 0; i
< system
->maxMasters(); i
++) {
2153 avgMshrUncacheableLatency
[access_idx
].subname(
2154 i
, system
->getMasterName(i
));
2158 overallAvgMshrUncacheableLatency
2159 .name(name() + ".overall_avg_mshr_uncacheable_latency")
2160 .desc("average overall mshr uncacheable latency")
2161 .flags(total
| nozero
| nonan
)
2163 overallAvgMshrUncacheableLatency
=
2164 overallMshrUncacheableLatency
/ overallMshrUncacheable
;
2165 for (int i
= 0; i
< system
->maxMasters(); i
++) {
2166 overallAvgMshrUncacheableLatency
.subname(i
, system
->getMasterName(i
));
2170 .name(name() + ".replacements")
2171 .desc("number of replacements")
2181 BaseCache::CpuSidePort::recvTimingSnoopResp(PacketPtr pkt
)
2183 // Snoops shouldn't happen when bypassing caches
2184 assert(!cache
->system
->bypassCaches());
2186 assert(pkt
->isResponse());
2188 // Express snoop responses from master to slave, e.g., from L1 to L2
2189 cache
->recvTimingSnoopResp(pkt
);
2195 BaseCache::CpuSidePort::tryTiming(PacketPtr pkt
)
2197 if (cache
->system
->bypassCaches() || pkt
->isExpressSnoop()) {
2198 // always let express snoop packets through even if blocked
2200 } else if (blocked
|| mustSendRetry
) {
2201 // either already committed to send a retry, or blocked
2202 mustSendRetry
= true;
2205 mustSendRetry
= false;
2210 BaseCache::CpuSidePort::recvTimingReq(PacketPtr pkt
)
2212 assert(pkt
->isRequest());
2214 if (cache
->system
->bypassCaches()) {
2215 // Just forward the packet if caches are disabled.
2216 // @todo This should really enqueue the packet rather
2217 bool M5_VAR_USED success
= cache
->memSidePort
.sendTimingReq(pkt
);
2220 } else if (tryTiming(pkt
)) {
2221 cache
->recvTimingReq(pkt
);
2228 BaseCache::CpuSidePort::recvAtomic(PacketPtr pkt
)
2230 if (cache
->system
->bypassCaches()) {
2231 // Forward the request if the system is in cache bypass mode.
2232 return cache
->memSidePort
.sendAtomic(pkt
);
2234 return cache
->recvAtomic(pkt
);
2239 BaseCache::CpuSidePort::recvFunctional(PacketPtr pkt
)
2241 if (cache
->system
->bypassCaches()) {
2242 // The cache should be flushed if we are in cache bypass mode,
2243 // so we don't need to check if we need to update anything.
2244 cache
->memSidePort
.sendFunctional(pkt
);
2248 // functional request
2249 cache
->functionalAccess(pkt
, true);
2253 BaseCache::CpuSidePort::getAddrRanges() const
2255 return cache
->getAddrRanges();
2260 CpuSidePort::CpuSidePort(const std::string
&_name
, BaseCache
*_cache
,
2261 const std::string
&_label
)
2262 : CacheSlavePort(_name
, _cache
, _label
), cache(_cache
)
2272 BaseCache::MemSidePort::recvTimingResp(PacketPtr pkt
)
2274 cache
->recvTimingResp(pkt
);
2278 // Express snooping requests to memside port
2280 BaseCache::MemSidePort::recvTimingSnoopReq(PacketPtr pkt
)
2282 // Snoops shouldn't happen when bypassing caches
2283 assert(!cache
->system
->bypassCaches());
2285 // handle snooping requests
2286 cache
->recvTimingSnoopReq(pkt
);
2290 BaseCache::MemSidePort::recvAtomicSnoop(PacketPtr pkt
)
2292 // Snoops shouldn't happen when bypassing caches
2293 assert(!cache
->system
->bypassCaches());
2295 return cache
->recvAtomicSnoop(pkt
);
2299 BaseCache::MemSidePort::recvFunctionalSnoop(PacketPtr pkt
)
2301 // Snoops shouldn't happen when bypassing caches
2302 assert(!cache
->system
->bypassCaches());
2304 // functional snoop (note that in contrast to atomic we don't have
2305 // a specific functionalSnoop method, as they have the same
2306 // behaviour regardless)
2307 cache
->functionalAccess(pkt
, false);
2311 BaseCache::CacheReqPacketQueue::sendDeferredPacket()
2314 assert(!waitingOnRetry
);
2316 // there should never be any deferred request packets in the
2317 // queue, instead we resly on the cache to provide the packets
2318 // from the MSHR queue or write queue
2319 assert(deferredPacketReadyTime() == MaxTick
);
2321 // check for request packets (requests & writebacks)
2322 QueueEntry
* entry
= cache
.getNextQueueEntry();
2325 // can happen if e.g. we attempt a writeback and fail, but
2326 // before the retry, the writeback is eliminated because
2327 // we snoop another cache's ReadEx.
2329 // let our snoop responses go first if there are responses to
2330 // the same addresses
2331 if (checkConflictingSnoop(entry
->blkAddr
)) {
2334 waitingOnRetry
= entry
->sendPacket(cache
);
2337 // if we succeeded and are not waiting for a retry, schedule the
2338 // next send considering when the next queue is ready, note that
2339 // snoop responses have their own packet queue and thus schedule
2341 if (!waitingOnRetry
) {
2342 schedSendEvent(cache
.nextQueueReadyTime());
2346 BaseCache::MemSidePort::MemSidePort(const std::string
&_name
,
2348 const std::string
&_label
)
2349 : CacheMasterPort(_name
, _cache
, _reqQueue
, _snoopRespQueue
),
2350 _reqQueue(*_cache
, *this, _snoopRespQueue
, _label
),
2351 _snoopRespQueue(*_cache
, *this, _label
), cache(_cache
)