2 * Copyright (c) 2012-2013, 2018 ARM Limited
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
14 * Copyright (c) 2003-2005 The Regents of The University of Michigan
15 * All rights reserved.
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 * Authors: Erik Hallnor
46 * Definition of BaseCache functions.
49 #include "mem/cache/base.hh"
51 #include "base/compiler.hh"
52 #include "base/logging.hh"
53 #include "debug/Cache.hh"
54 #include "debug/CachePort.hh"
55 #include "debug/CacheVerbose.hh"
56 #include "mem/cache/mshr.hh"
57 #include "mem/cache/prefetch/base.hh"
58 #include "mem/cache/queue_entry.hh"
59 #include "params/BaseCache.hh"
60 #include "sim/core.hh"
67 BaseCache::CacheSlavePort::CacheSlavePort(const std::string
&_name
,
69 const std::string
&_label
)
70 : QueuedSlavePort(_name
, _cache
, queue
), queue(*_cache
, *this, _label
),
71 blocked(false), mustSendRetry(false),
72 sendRetryEvent([this]{ processSendRetry(); }, _name
)
76 BaseCache::BaseCache(const BaseCacheParams
*p
, unsigned blk_size
)
78 cpuSidePort (p
->name
+ ".cpu_side", this, "CpuSidePort"),
79 memSidePort(p
->name
+ ".mem_side", this, "MemSidePort"),
80 mshrQueue("MSHRs", p
->mshrs
, 0, p
->demand_mshr_reserve
), // see below
81 writeBuffer("write buffer", p
->write_buffers
, p
->mshrs
), // see below
83 prefetcher(p
->prefetcher
),
84 prefetchOnAccess(p
->prefetch_on_access
),
85 writebackClean(p
->writeback_clean
),
86 tempBlockWriteback(nullptr),
87 writebackTempBlockAtomicEvent([this]{ writebackTempBlockAtomic(); },
89 EventBase::Delayed_Writeback_Pri
),
91 lookupLatency(p
->tag_latency
),
92 dataLatency(p
->data_latency
),
93 forwardLatency(p
->tag_latency
),
94 fillLatency(p
->data_latency
),
95 responseLatency(p
->response_latency
),
96 numTarget(p
->tgts_per_mshr
),
98 clusivity(p
->clusivity
),
99 isReadOnly(p
->is_read_only
),
102 noTargetMSHR(nullptr),
103 missCount(p
->max_miss_count
),
104 addrRanges(p
->addr_ranges
.begin(), p
->addr_ranges
.end()),
107 // the MSHR queue has no reserve entries as we check the MSHR
108 // queue on every single allocation, whereas the write queue has
109 // as many reserve entries as we have MSHRs, since every MSHR may
110 // eventually require a writeback, and we do not check the write
111 // buffer before committing to an MSHR
113 // forward snoops is overridden in init() once we can query
114 // whether the connected master is actually snooping or not
116 tempBlock
= new TempCacheBlk();
117 tempBlock
->data
= new uint8_t[blkSize
];
119 tags
->setCache(this);
121 prefetcher
->setCache(this);
124 BaseCache::~BaseCache()
126 delete [] tempBlock
->data
;
131 BaseCache::CacheSlavePort::setBlocked()
134 DPRINTF(CachePort
, "Port is blocking new requests\n");
136 // if we already scheduled a retry in this cycle, but it has not yet
137 // happened, cancel it
138 if (sendRetryEvent
.scheduled()) {
139 owner
.deschedule(sendRetryEvent
);
140 DPRINTF(CachePort
, "Port descheduled retry\n");
141 mustSendRetry
= true;
146 BaseCache::CacheSlavePort::clearBlocked()
149 DPRINTF(CachePort
, "Port is accepting new requests\n");
152 // @TODO: need to find a better time (next cycle?)
153 owner
.schedule(sendRetryEvent
, curTick() + 1);
158 BaseCache::CacheSlavePort::processSendRetry()
160 DPRINTF(CachePort
, "Port is sending retry\n");
162 // reset the flag and call retry
163 mustSendRetry
= false;
168 BaseCache::regenerateBlkAddr(CacheBlk
* blk
)
170 if (blk
!= tempBlock
) {
171 return tags
->regenerateBlkAddr(blk
);
173 return tempBlock
->getAddr();
180 if (!cpuSidePort
.isConnected() || !memSidePort
.isConnected())
181 fatal("Cache ports on %s are not connected\n", name());
182 cpuSidePort
.sendRangeChange();
183 forwardSnoops
= cpuSidePort
.isSnooping();
187 BaseCache::getMasterPort(const std::string
&if_name
, PortID idx
)
189 if (if_name
== "mem_side") {
192 return MemObject::getMasterPort(if_name
, idx
);
197 BaseCache::getSlavePort(const std::string
&if_name
, PortID idx
)
199 if (if_name
== "cpu_side") {
202 return MemObject::getSlavePort(if_name
, idx
);
207 BaseCache::inRange(Addr addr
) const
209 for (const auto& r
: addrRanges
) {
210 if (r
.contains(addr
)) {
218 BaseCache::handleTimingReqHit(PacketPtr pkt
, CacheBlk
*blk
, Tick request_time
)
220 if (pkt
->needsResponse()) {
221 pkt
->makeTimingResponse();
222 // @todo: Make someone pay for this
223 pkt
->headerDelay
= pkt
->payloadDelay
= 0;
225 // In this case we are considering request_time that takes
226 // into account the delay of the xbar, if any, and just
227 // lat, neglecting responseLatency, modelling hit latency
228 // just as lookupLatency or or the value of lat overriden
229 // by access(), that calls accessBlock() function.
230 cpuSidePort
.schedTimingResp(pkt
, request_time
, true);
232 DPRINTF(Cache
, "%s satisfied %s, no response needed\n", __func__
,
235 // queue the packet for deletion, as the sending cache is
236 // still relying on it; if the block is found in access(),
237 // CleanEvict and Writeback messages will be deleted
239 pendingDelete
.reset(pkt
);
244 BaseCache::handleTimingReqMiss(PacketPtr pkt
, MSHR
*mshr
, CacheBlk
*blk
,
245 Tick forward_time
, Tick request_time
)
249 /// @note writebacks will be checked in getNextMSHR()
250 /// for any conflicting requests to the same block
252 //@todo remove hw_pf here
254 // Coalesce unless it was a software prefetch (see above).
256 assert(!pkt
->isWriteback());
257 // CleanEvicts corresponding to blocks which have
258 // outstanding requests in MSHRs are simply sunk here
259 if (pkt
->cmd
== MemCmd::CleanEvict
) {
260 pendingDelete
.reset(pkt
);
261 } else if (pkt
->cmd
== MemCmd::WriteClean
) {
262 // A WriteClean should never coalesce with any
263 // outstanding cache maintenance requests.
265 // We use forward_time here because there is an
266 // uncached memory write, forwarded to WriteBuffer.
267 allocateWriteBuffer(pkt
, forward_time
);
269 DPRINTF(Cache
, "%s coalescing MSHR for %s\n", __func__
,
272 assert(pkt
->req
->masterId() < system
->maxMasters());
273 mshr_hits
[pkt
->cmdToIndex()][pkt
->req
->masterId()]++;
275 // We use forward_time here because it is the same
276 // considering new targets. We have multiple
277 // requests for the same address here. It
278 // specifies the latency to allocate an internal
279 // buffer and to schedule an event to the queued
280 // port and also takes into account the additional
281 // delay of the xbar.
282 mshr
->allocateTarget(pkt
, forward_time
, order
++,
283 allocOnFill(pkt
->cmd
));
284 if (mshr
->getNumTargets() == numTarget
) {
286 setBlocked(Blocked_NoTargets
);
287 // need to be careful with this... if this mshr isn't
288 // ready yet (i.e. time > curTick()), we don't want to
289 // move it ahead of mshrs that are ready
290 // mshrQueue.moveToFront(mshr);
296 assert(pkt
->req
->masterId() < system
->maxMasters());
297 mshr_misses
[pkt
->cmdToIndex()][pkt
->req
->masterId()]++;
299 if (pkt
->isEviction() || pkt
->cmd
== MemCmd::WriteClean
) {
300 // We use forward_time here because there is an
301 // writeback or writeclean, forwarded to WriteBuffer.
302 allocateWriteBuffer(pkt
, forward_time
);
304 if (blk
&& blk
->isValid()) {
305 // If we have a write miss to a valid block, we
306 // need to mark the block non-readable. Otherwise
307 // if we allow reads while there's an outstanding
308 // write miss, the read could return stale data
309 // out of the cache block... a more aggressive
310 // system could detect the overlap (if any) and
311 // forward data out of the MSHRs, but we don't do
312 // that yet. Note that we do need to leave the
313 // block valid so that it stays in the cache, in
314 // case we get an upgrade response (and hence no
315 // new data) when the write miss completes.
316 // As long as CPUs do proper store/load forwarding
317 // internally, and have a sufficiently weak memory
318 // model, this is probably unnecessary, but at some
319 // point it must have seemed like we needed it...
320 assert((pkt
->needsWritable() && !blk
->isWritable()) ||
321 pkt
->req
->isCacheMaintenance());
322 blk
->status
&= ~BlkReadable
;
324 // Here we are using forward_time, modelling the latency of
325 // a miss (outbound) just as forwardLatency, neglecting the
326 // lookupLatency component.
327 allocateMissBuffer(pkt
, forward_time
);
333 BaseCache::recvTimingReq(PacketPtr pkt
)
335 // anything that is merely forwarded pays for the forward latency and
336 // the delay provided by the crossbar
337 Tick forward_time
= clockEdge(forwardLatency
) + pkt
->headerDelay
;
339 // We use lookupLatency here because it is used to specify the latency
341 Cycles lat
= lookupLatency
;
342 CacheBlk
*blk
= nullptr;
343 bool satisfied
= false;
345 PacketList writebacks
;
346 // Note that lat is passed by reference here. The function
347 // access() calls accessBlock() which can modify lat value.
348 satisfied
= access(pkt
, blk
, lat
, writebacks
);
350 // copy writebacks to write buffer here to ensure they logically
351 // proceed anything happening below
352 doWritebacks(writebacks
, forward_time
);
355 // Here we charge the headerDelay that takes into account the latencies
356 // of the bus, if the packet comes from it.
357 // The latency charged it is just lat that is the value of lookupLatency
358 // modified by access() function, or if not just lookupLatency.
359 // In case of a hit we are neglecting response latency.
360 // In case of a miss we are neglecting forward latency.
361 Tick request_time
= clockEdge(lat
) + pkt
->headerDelay
;
362 // Here we reset the timing of the packet.
363 pkt
->headerDelay
= pkt
->payloadDelay
= 0;
364 // track time of availability of next prefetch, if any
365 Tick next_pf_time
= MaxTick
;
368 // if need to notify the prefetcher we have to do it before
369 // anything else as later handleTimingReqHit might turn the
370 // packet in a response
372 (prefetchOnAccess
|| (blk
&& blk
->wasPrefetched()))) {
374 blk
->status
&= ~BlkHWPrefetched
;
376 // Don't notify on SWPrefetch
377 if (!pkt
->cmd
.isSWPrefetch()) {
378 assert(!pkt
->req
->isCacheMaintenance());
379 next_pf_time
= prefetcher
->notify(pkt
);
383 handleTimingReqHit(pkt
, blk
, request_time
);
385 handleTimingReqMiss(pkt
, blk
, forward_time
, request_time
);
387 // We should call the prefetcher reguardless if the request is
388 // satisfied or not, reguardless if the request is in the MSHR
389 // or not. The request could be a ReadReq hit, but still not
390 // satisfied (potentially because of a prior write to the same
391 // cache line. So, even when not satisfied, there is an MSHR
392 // already allocated for this, we need to let the prefetcher
393 // know about the request
395 // Don't notify prefetcher on SWPrefetch or cache maintenance
397 if (prefetcher
&& pkt
&&
398 !pkt
->cmd
.isSWPrefetch() &&
399 !pkt
->req
->isCacheMaintenance()) {
400 next_pf_time
= prefetcher
->notify(pkt
);
404 if (next_pf_time
!= MaxTick
) {
405 schedMemSideSendEvent(next_pf_time
);
410 BaseCache::handleUncacheableWriteResp(PacketPtr pkt
)
412 Tick completion_time
= clockEdge(responseLatency
) +
413 pkt
->headerDelay
+ pkt
->payloadDelay
;
415 // Reset the bus additional time as it is now accounted for
416 pkt
->headerDelay
= pkt
->payloadDelay
= 0;
418 cpuSidePort
.schedTimingResp(pkt
, completion_time
, true);
422 BaseCache::recvTimingResp(PacketPtr pkt
)
424 assert(pkt
->isResponse());
426 // all header delay should be paid for by the crossbar, unless
427 // this is a prefetch response from above
428 panic_if(pkt
->headerDelay
!= 0 && pkt
->cmd
!= MemCmd::HardPFResp
,
429 "%s saw a non-zero packet delay\n", name());
431 const bool is_error
= pkt
->isError();
434 DPRINTF(Cache
, "%s: Cache received %s with error\n", __func__
,
438 DPRINTF(Cache
, "%s: Handling response %s\n", __func__
,
441 // if this is a write, we should be looking at an uncacheable
443 if (pkt
->isWrite()) {
444 assert(pkt
->req
->isUncacheable());
445 handleUncacheableWriteResp(pkt
);
449 // we have dealt with any (uncacheable) writes above, from here on
450 // we know we are dealing with an MSHR due to a miss or a prefetch
451 MSHR
*mshr
= dynamic_cast<MSHR
*>(pkt
->popSenderState());
454 if (mshr
== noTargetMSHR
) {
455 // we always clear at least one target
456 clearBlocked(Blocked_NoTargets
);
457 noTargetMSHR
= nullptr;
460 // Initial target is used just for stats
461 MSHR::Target
*initial_tgt
= mshr
->getTarget();
462 int stats_cmd_idx
= initial_tgt
->pkt
->cmdToIndex();
463 Tick miss_latency
= curTick() - initial_tgt
->recvTime
;
465 if (pkt
->req
->isUncacheable()) {
466 assert(pkt
->req
->masterId() < system
->maxMasters());
467 mshr_uncacheable_lat
[stats_cmd_idx
][pkt
->req
->masterId()] +=
470 assert(pkt
->req
->masterId() < system
->maxMasters());
471 mshr_miss_latency
[stats_cmd_idx
][pkt
->req
->masterId()] +=
475 PacketList writebacks
;
477 bool is_fill
= !mshr
->isForward
&&
478 (pkt
->isRead() || pkt
->cmd
== MemCmd::UpgradeResp
);
480 CacheBlk
*blk
= tags
->findBlock(pkt
->getAddr(), pkt
->isSecure());
482 if (is_fill
&& !is_error
) {
483 DPRINTF(Cache
, "Block for addr %#llx being updated in Cache\n",
486 blk
= handleFill(pkt
, blk
, writebacks
, mshr
->allocOnFill());
487 assert(blk
!= nullptr);
490 if (blk
&& blk
->isValid() && pkt
->isClean() && !pkt
->isInvalidate()) {
491 // The block was marked not readable while there was a pending
492 // cache maintenance operation, restore its flag.
493 blk
->status
|= BlkReadable
;
496 if (blk
&& blk
->isWritable() && !pkt
->req
->isCacheInvalidate()) {
497 // If at this point the referenced block is writable and the
498 // response is not a cache invalidate, we promote targets that
499 // were deferred as we couldn't guarrantee a writable copy
500 mshr
->promoteWritable();
503 serviceMSHRTargets(mshr
, pkt
, blk
, writebacks
);
505 if (mshr
->promoteDeferredTargets()) {
506 // avoid later read getting stale data while write miss is
507 // outstanding.. see comment in timingAccess()
509 blk
->status
&= ~BlkReadable
;
511 mshrQueue
.markPending(mshr
);
512 schedMemSideSendEvent(clockEdge() + pkt
->payloadDelay
);
514 // while we deallocate an mshr from the queue we still have to
515 // check the isFull condition before and after as we might
516 // have been using the reserved entries already
517 const bool was_full
= mshrQueue
.isFull();
518 mshrQueue
.deallocate(mshr
);
519 if (was_full
&& !mshrQueue
.isFull()) {
520 clearBlocked(Blocked_NoMSHRs
);
523 // Request the bus for a prefetch if this deallocation freed enough
524 // MSHRs for a prefetch to take place
525 if (prefetcher
&& mshrQueue
.canPrefetch()) {
526 Tick next_pf_time
= std::max(prefetcher
->nextPrefetchReadyTime(),
528 if (next_pf_time
!= MaxTick
)
529 schedMemSideSendEvent(next_pf_time
);
533 // if we used temp block, check to see if its valid and then clear it out
534 if (blk
== tempBlock
&& tempBlock
->isValid()) {
535 evictBlock(blk
, writebacks
);
538 const Tick forward_time
= clockEdge(forwardLatency
) + pkt
->headerDelay
;
539 // copy writebacks to write buffer
540 doWritebacks(writebacks
, forward_time
);
542 DPRINTF(CacheVerbose
, "%s: Leaving with %s\n", __func__
, pkt
->print());
548 BaseCache::recvAtomic(PacketPtr pkt
)
550 // We are in atomic mode so we pay just for lookupLatency here.
551 Cycles lat
= lookupLatency
;
553 // follow the same flow as in recvTimingReq, and check if a cache
554 // above us is responding
555 if (pkt
->cacheResponding() && !pkt
->isClean()) {
556 assert(!pkt
->req
->isCacheInvalidate());
557 DPRINTF(Cache
, "Cache above responding to %s: not responding\n",
560 // if a cache is responding, and it had the line in Owned
561 // rather than Modified state, we need to invalidate any
562 // copies that are not on the same path to memory
563 assert(pkt
->needsWritable() && !pkt
->responderHadWritable());
564 lat
+= ticksToCycles(memSidePort
.sendAtomic(pkt
));
566 return lat
* clockPeriod();
569 // should assert here that there are no outstanding MSHRs or
570 // writebacks... that would mean that someone used an atomic
571 // access in timing mode
573 CacheBlk
*blk
= nullptr;
574 PacketList writebacks
;
575 bool satisfied
= access(pkt
, blk
, lat
, writebacks
);
577 if (pkt
->isClean() && blk
&& blk
->isDirty()) {
578 // A cache clean opearation is looking for a dirty
579 // block. If a dirty block is encountered a WriteClean
580 // will update any copies to the path to the memory
581 // until the point of reference.
582 DPRINTF(CacheVerbose
, "%s: packet %s found block: %s\n",
583 __func__
, pkt
->print(), blk
->print());
584 PacketPtr wb_pkt
= writecleanBlk(blk
, pkt
->req
->getDest(), pkt
->id
);
585 writebacks
.push_back(wb_pkt
);
589 // handle writebacks resulting from the access here to ensure they
590 // logically proceed anything happening below
591 doWritebacksAtomic(writebacks
);
592 assert(writebacks
.empty());
595 lat
+= handleAtomicReqMiss(pkt
, blk
, writebacks
);
598 // Note that we don't invoke the prefetcher at all in atomic mode.
599 // It's not clear how to do it properly, particularly for
600 // prefetchers that aggressively generate prefetch candidates and
601 // rely on bandwidth contention to throttle them; these will tend
602 // to pollute the cache in atomic mode since there is no bandwidth
603 // contention. If we ever do want to enable prefetching in atomic
604 // mode, though, this is the place to do it... see timingAccess()
605 // for an example (though we'd want to issue the prefetch(es)
606 // immediately rather than calling requestMemSideBus() as we do
609 // do any writebacks resulting from the response handling
610 doWritebacksAtomic(writebacks
);
612 // if we used temp block, check to see if its valid and if so
613 // clear it out, but only do so after the call to recvAtomic is
614 // finished so that any downstream observers (such as a snoop
615 // filter), first see the fill, and only then see the eviction
616 if (blk
== tempBlock
&& tempBlock
->isValid()) {
617 // the atomic CPU calls recvAtomic for fetch and load/store
618 // sequentuially, and we may already have a tempBlock
619 // writeback from the fetch that we have not yet sent
620 if (tempBlockWriteback
) {
621 // if that is the case, write the prevoius one back, and
622 // do not schedule any new event
623 writebackTempBlockAtomic();
625 // the writeback/clean eviction happens after the call to
626 // recvAtomic has finished (but before any successive
627 // calls), so that the response handling from the fill is
628 // allowed to happen first
629 schedule(writebackTempBlockAtomicEvent
, curTick());
632 tempBlockWriteback
= evictBlock(blk
);
635 if (pkt
->needsResponse()) {
636 pkt
->makeAtomicResponse();
639 return lat
* clockPeriod();
643 BaseCache::functionalAccess(PacketPtr pkt
, bool from_cpu_side
)
645 Addr blk_addr
= pkt
->getBlockAddr(blkSize
);
646 bool is_secure
= pkt
->isSecure();
647 CacheBlk
*blk
= tags
->findBlock(pkt
->getAddr(), is_secure
);
648 MSHR
*mshr
= mshrQueue
.findMatch(blk_addr
, is_secure
);
650 pkt
->pushLabel(name());
652 CacheBlkPrintWrapper
cbpw(blk
);
654 // Note that just because an L2/L3 has valid data doesn't mean an
655 // L1 doesn't have a more up-to-date modified copy that still
656 // needs to be found. As a result we always update the request if
657 // we have it, but only declare it satisfied if we are the owner.
659 // see if we have data at all (owned or otherwise)
660 bool have_data
= blk
&& blk
->isValid()
661 && pkt
->checkFunctional(&cbpw
, blk_addr
, is_secure
, blkSize
,
664 // data we have is dirty if marked as such or if we have an
665 // in-service MSHR that is pending a modified line
667 have_data
&& (blk
->isDirty() ||
668 (mshr
&& mshr
->inService
&& mshr
->isPendingModified()));
670 bool done
= have_dirty
||
671 cpuSidePort
.checkFunctional(pkt
) ||
672 mshrQueue
.checkFunctional(pkt
, blk_addr
) ||
673 writeBuffer
.checkFunctional(pkt
, blk_addr
) ||
674 memSidePort
.checkFunctional(pkt
);
676 DPRINTF(CacheVerbose
, "%s: %s %s%s%s\n", __func__
, pkt
->print(),
677 (blk
&& blk
->isValid()) ? "valid " : "",
678 have_data
? "data " : "", done
? "done " : "");
680 // We're leaving the cache, so pop cache->name() label
686 // if it came as a request from the CPU side then make sure it
687 // continues towards the memory side
689 memSidePort
.sendFunctional(pkt
);
690 } else if (cpuSidePort
.isSnooping()) {
691 // if it came from the memory side, it must be a snoop request
692 // and we should only forward it if we are forwarding snoops
693 cpuSidePort
.sendFunctionalSnoop(pkt
);
700 BaseCache::cmpAndSwap(CacheBlk
*blk
, PacketPtr pkt
)
702 assert(pkt
->isRequest());
704 uint64_t overwrite_val
;
706 uint64_t condition_val64
;
707 uint32_t condition_val32
;
709 int offset
= pkt
->getOffset(blkSize
);
710 uint8_t *blk_data
= blk
->data
+ offset
;
712 assert(sizeof(uint64_t) >= pkt
->getSize());
714 overwrite_mem
= true;
715 // keep a copy of our possible write value, and copy what is at the
716 // memory address into the packet
717 pkt
->writeData((uint8_t *)&overwrite_val
);
718 pkt
->setData(blk_data
);
720 if (pkt
->req
->isCondSwap()) {
721 if (pkt
->getSize() == sizeof(uint64_t)) {
722 condition_val64
= pkt
->req
->getExtraData();
723 overwrite_mem
= !std::memcmp(&condition_val64
, blk_data
,
725 } else if (pkt
->getSize() == sizeof(uint32_t)) {
726 condition_val32
= (uint32_t)pkt
->req
->getExtraData();
727 overwrite_mem
= !std::memcmp(&condition_val32
, blk_data
,
730 panic("Invalid size for conditional read/write\n");
734 std::memcpy(blk_data
, &overwrite_val
, pkt
->getSize());
735 blk
->status
|= BlkDirty
;
740 BaseCache::getNextQueueEntry()
742 // Check both MSHR queue and write buffer for potential requests,
743 // note that null does not mean there is no request, it could
744 // simply be that it is not ready
745 MSHR
*miss_mshr
= mshrQueue
.getNext();
746 WriteQueueEntry
*wq_entry
= writeBuffer
.getNext();
748 // If we got a write buffer request ready, first priority is a
749 // full write buffer, otherwise we favour the miss requests
750 if (wq_entry
&& (writeBuffer
.isFull() || !miss_mshr
)) {
751 // need to search MSHR queue for conflicting earlier miss.
752 MSHR
*conflict_mshr
=
753 mshrQueue
.findPending(wq_entry
->blkAddr
,
756 if (conflict_mshr
&& conflict_mshr
->order
< wq_entry
->order
) {
757 // Service misses in order until conflict is cleared.
758 return conflict_mshr
;
760 // @todo Note that we ignore the ready time of the conflict here
763 // No conflicts; issue write
765 } else if (miss_mshr
) {
766 // need to check for conflicting earlier writeback
767 WriteQueueEntry
*conflict_mshr
=
768 writeBuffer
.findPending(miss_mshr
->blkAddr
,
769 miss_mshr
->isSecure
);
771 // not sure why we don't check order here... it was in the
772 // original code but commented out.
774 // The only way this happens is if we are
775 // doing a write and we didn't have permissions
776 // then subsequently saw a writeback (owned got evicted)
777 // We need to make sure to perform the writeback first
778 // To preserve the dirty data, then we can issue the write
780 // should we return wq_entry here instead? I.e. do we
781 // have to flush writes in order? I don't think so... not
782 // for Alpha anyway. Maybe for x86?
783 return conflict_mshr
;
785 // @todo Note that we ignore the ready time of the conflict here
788 // No conflicts; issue read
792 // fall through... no pending requests. Try a prefetch.
793 assert(!miss_mshr
&& !wq_entry
);
794 if (prefetcher
&& mshrQueue
.canPrefetch()) {
795 // If we have a miss queue slot, we can try a prefetch
796 PacketPtr pkt
= prefetcher
->getPacket();
798 Addr pf_addr
= pkt
->getBlockAddr(blkSize
);
799 if (!tags
->findBlock(pf_addr
, pkt
->isSecure()) &&
800 !mshrQueue
.findMatch(pf_addr
, pkt
->isSecure()) &&
801 !writeBuffer
.findMatch(pf_addr
, pkt
->isSecure())) {
802 // Update statistic on number of prefetches issued
803 // (hwpf_mshr_misses)
804 assert(pkt
->req
->masterId() < system
->maxMasters());
805 mshr_misses
[pkt
->cmdToIndex()][pkt
->req
->masterId()]++;
807 // allocate an MSHR and return it, note
808 // that we send the packet straight away, so do not
810 return allocateMissBuffer(pkt
, curTick(), false);
812 // free the request and packet
822 BaseCache::satisfyRequest(PacketPtr pkt
, CacheBlk
*blk
, bool, bool)
824 assert(pkt
->isRequest());
826 assert(blk
&& blk
->isValid());
827 // Occasionally this is not true... if we are a lower-level cache
828 // satisfying a string of Read and ReadEx requests from
829 // upper-level caches, a Read will mark the block as shared but we
830 // can satisfy a following ReadEx anyway since we can rely on the
831 // Read requester(s) to have buffered the ReadEx snoop and to
832 // invalidate their blocks after receiving them.
833 // assert(!pkt->needsWritable() || blk->isWritable());
834 assert(pkt
->getOffset(blkSize
) + pkt
->getSize() <= blkSize
);
836 // Check RMW operations first since both isRead() and
837 // isWrite() will be true for them
838 if (pkt
->cmd
== MemCmd::SwapReq
) {
839 if (pkt
->isAtomicOp()) {
840 // extract data from cache and save it into the data field in
841 // the packet as a return value from this atomic op
843 int offset
= tags
->extractBlkOffset(pkt
->getAddr());
844 uint8_t *blk_data
= blk
->data
+ offset
;
845 std::memcpy(pkt
->getPtr
<uint8_t>(), blk_data
, pkt
->getSize());
847 // execute AMO operation
848 (*(pkt
->getAtomicOp()))(blk_data
);
850 // set block status to dirty
851 blk
->status
|= BlkDirty
;
853 cmpAndSwap(blk
, pkt
);
855 } else if (pkt
->isWrite()) {
856 // we have the block in a writable state and can go ahead,
857 // note that the line may be also be considered writable in
858 // downstream caches along the path to memory, but always
859 // Exclusive, and never Modified
860 assert(blk
->isWritable());
861 // Write or WriteLine at the first cache with block in writable state
862 if (blk
->checkWrite(pkt
)) {
863 pkt
->writeDataToBlock(blk
->data
, blkSize
);
865 // Always mark the line as dirty (and thus transition to the
866 // Modified state) even if we are a failed StoreCond so we
867 // supply data to any snoops that have appended themselves to
868 // this cache before knowing the store will fail.
869 blk
->status
|= BlkDirty
;
870 DPRINTF(CacheVerbose
, "%s for %s (write)\n", __func__
, pkt
->print());
871 } else if (pkt
->isRead()) {
873 blk
->trackLoadLocked(pkt
);
876 // all read responses have a data payload
877 assert(pkt
->hasRespData());
878 pkt
->setDataFromBlock(blk
->data
, blkSize
);
879 } else if (pkt
->isUpgrade()) {
881 assert(!pkt
->hasSharers());
883 if (blk
->isDirty()) {
884 // we were in the Owned state, and a cache above us that
885 // has the line in Shared state needs to be made aware
886 // that the data it already has is in fact dirty
887 pkt
->setCacheResponding();
888 blk
->status
&= ~BlkDirty
;
891 assert(pkt
->isInvalidate());
892 invalidateBlock(blk
);
893 DPRINTF(CacheVerbose
, "%s for %s (invalidation)\n", __func__
,
898 /////////////////////////////////////////////////////
900 // Access path: requests coming in from the CPU side
902 /////////////////////////////////////////////////////
905 BaseCache::access(PacketPtr pkt
, CacheBlk
*&blk
, Cycles
&lat
,
906 PacketList
&writebacks
)
909 assert(pkt
->isRequest());
911 chatty_assert(!(isReadOnly
&& pkt
->isWrite()),
912 "Should never see a write in a read-only cache %s\n",
915 // Here lat is the value passed as parameter to accessBlock() function
916 // that can modify its value.
917 blk
= tags
->accessBlock(pkt
->getAddr(), pkt
->isSecure(), lat
);
919 DPRINTF(Cache
, "%s for %s %s\n", __func__
, pkt
->print(),
920 blk
? "hit " + blk
->print() : "miss");
922 if (pkt
->req
->isCacheMaintenance()) {
923 // A cache maintenance operation is always forwarded to the
924 // memory below even if the block is found in dirty state.
926 // We defer any changes to the state of the block until we
927 // create and mark as in service the mshr for the downstream
932 if (pkt
->isEviction()) {
933 // We check for presence of block in above caches before issuing
934 // Writeback or CleanEvict to write buffer. Therefore the only
935 // possible cases can be of a CleanEvict packet coming from above
936 // encountering a Writeback generated in this cache peer cache and
937 // waiting in the write buffer. Cases of upper level peer caches
938 // generating CleanEvict and Writeback or simply CleanEvict and
939 // CleanEvict almost simultaneously will be caught by snoops sent out
941 WriteQueueEntry
*wb_entry
= writeBuffer
.findMatch(pkt
->getAddr(),
944 assert(wb_entry
->getNumTargets() == 1);
945 PacketPtr wbPkt
= wb_entry
->getTarget()->pkt
;
946 assert(wbPkt
->isWriteback());
948 if (pkt
->isCleanEviction()) {
949 // The CleanEvict and WritebackClean snoops into other
950 // peer caches of the same level while traversing the
951 // crossbar. If a copy of the block is found, the
952 // packet is deleted in the crossbar. Hence, none of
953 // the other upper level caches connected to this
954 // cache have the block, so we can clear the
955 // BLOCK_CACHED flag in the Writeback if set and
956 // discard the CleanEvict by returning true.
957 wbPkt
->clearBlockCached();
960 assert(pkt
->cmd
== MemCmd::WritebackDirty
);
961 // Dirty writeback from above trumps our clean
962 // writeback... discard here
963 // Note: markInService will remove entry from writeback buffer.
964 markInService(wb_entry
);
970 // Writeback handling is special case. We can write the block into
971 // the cache without having a writeable copy (or any copy at all).
972 if (pkt
->isWriteback()) {
973 assert(blkSize
== pkt
->getSize());
975 // we could get a clean writeback while we are having
976 // outstanding accesses to a block, do the simple thing for
977 // now and drop the clean writeback so that we do not upset
978 // any ordering/decisions about ownership already taken
979 if (pkt
->cmd
== MemCmd::WritebackClean
&&
980 mshrQueue
.findMatch(pkt
->getAddr(), pkt
->isSecure())) {
981 DPRINTF(Cache
, "Clean writeback %#llx to block with MSHR, "
982 "dropping\n", pkt
->getAddr());
987 // need to do a replacement
988 blk
= allocateBlock(pkt
, writebacks
);
990 // no replaceable block available: give up, fwd to next level.
995 blk
->status
|= (BlkValid
| BlkReadable
);
997 // only mark the block dirty if we got a writeback command,
998 // and leave it as is for a clean writeback
999 if (pkt
->cmd
== MemCmd::WritebackDirty
) {
1000 // TODO: the coherent cache can assert(!blk->isDirty());
1001 blk
->status
|= BlkDirty
;
1003 // if the packet does not have sharers, it is passing
1004 // writable, and we got the writeback in Modified or Exclusive
1005 // state, if not we are in the Owned or Shared state
1006 if (!pkt
->hasSharers()) {
1007 blk
->status
|= BlkWritable
;
1009 // nothing else to do; writeback doesn't expect response
1010 assert(!pkt
->needsResponse());
1011 pkt
->writeDataToBlock(blk
->data
, blkSize
);
1012 DPRINTF(Cache
, "%s new state is %s\n", __func__
, blk
->print());
1014 // populate the time when the block will be ready to access.
1015 blk
->whenReady
= clockEdge(fillLatency
) + pkt
->headerDelay
+
1018 } else if (pkt
->cmd
== MemCmd::CleanEvict
) {
1020 // Found the block in the tags, need to stop CleanEvict from
1021 // propagating further down the hierarchy. Returning true will
1022 // treat the CleanEvict like a satisfied write request and delete
1026 // We didn't find the block here, propagate the CleanEvict further
1027 // down the memory hierarchy. Returning false will treat the CleanEvict
1028 // like a Writeback which could not find a replaceable block so has to
1029 // go to next level.
1031 } else if (pkt
->cmd
== MemCmd::WriteClean
) {
1032 // WriteClean handling is a special case. We can allocate a
1033 // block directly if it doesn't exist and we can update the
1034 // block immediately. The WriteClean transfers the ownership
1035 // of the block as well.
1036 assert(blkSize
== pkt
->getSize());
1039 if (pkt
->writeThrough()) {
1040 // if this is a write through packet, we don't try to
1041 // allocate if the block is not present
1044 // a writeback that misses needs to allocate a new block
1045 blk
= allocateBlock(pkt
, writebacks
);
1047 // no replaceable block available: give up, fwd to
1053 blk
->status
|= (BlkValid
| BlkReadable
);
1057 // at this point either this is a writeback or a write-through
1058 // write clean operation and the block is already in this
1059 // cache, we need to update the data and the block flags
1061 // TODO: the coherent cache can assert(!blk->isDirty());
1062 if (!pkt
->writeThrough()) {
1063 blk
->status
|= BlkDirty
;
1065 // nothing else to do; writeback doesn't expect response
1066 assert(!pkt
->needsResponse());
1067 pkt
->writeDataToBlock(blk
->data
, blkSize
);
1068 DPRINTF(Cache
, "%s new state is %s\n", __func__
, blk
->print());
1071 // populate the time when the block will be ready to access.
1072 blk
->whenReady
= clockEdge(fillLatency
) + pkt
->headerDelay
+
1074 // if this a write-through packet it will be sent to cache
1076 return !pkt
->writeThrough();
1077 } else if (blk
&& (pkt
->needsWritable() ? blk
->isWritable() :
1078 blk
->isReadable())) {
1079 // OK to satisfy access
1081 satisfyRequest(pkt
, blk
);
1082 maintainClusivity(pkt
->fromCache(), blk
);
1087 // Can't satisfy access normally... either no block (blk == nullptr)
1088 // or have block but need writable
1092 if (!blk
&& pkt
->isLLSC() && pkt
->isWrite()) {
1093 // complete miss on store conditional... just give up now
1094 pkt
->req
->setExtraData(0);
1102 BaseCache::maintainClusivity(bool from_cache
, CacheBlk
*blk
)
1104 if (from_cache
&& blk
&& blk
->isValid() && !blk
->isDirty() &&
1105 clusivity
== Enums::mostly_excl
) {
1106 // if we have responded to a cache, and our block is still
1107 // valid, but not dirty, and this cache is mostly exclusive
1108 // with respect to the cache above, drop the block
1109 invalidateBlock(blk
);
1114 BaseCache::handleFill(PacketPtr pkt
, CacheBlk
*blk
, PacketList
&writebacks
,
1117 assert(pkt
->isResponse() || pkt
->cmd
== MemCmd::WriteLineReq
);
1118 Addr addr
= pkt
->getAddr();
1119 bool is_secure
= pkt
->isSecure();
1121 CacheBlk::State old_state
= blk
? blk
->status
: 0;
1124 // When handling a fill, we should have no writes to this line.
1125 assert(addr
== pkt
->getBlockAddr(blkSize
));
1126 assert(!writeBuffer
.findMatch(addr
, is_secure
));
1129 // better have read new data...
1130 assert(pkt
->hasData());
1132 // only read responses and write-line requests have data;
1133 // note that we don't write the data here for write-line - that
1134 // happens in the subsequent call to satisfyRequest
1135 assert(pkt
->isRead() || pkt
->cmd
== MemCmd::WriteLineReq
);
1137 // need to do a replacement if allocating, otherwise we stick
1138 // with the temporary storage
1139 blk
= allocate
? allocateBlock(pkt
, writebacks
) : nullptr;
1142 // No replaceable block or a mostly exclusive
1143 // cache... just use temporary storage to complete the
1144 // current request and then get rid of it
1145 assert(!tempBlock
->isValid());
1147 tempBlock
->insert(addr
, is_secure
);
1148 DPRINTF(Cache
, "using temp block for %#llx (%s)\n", addr
,
1149 is_secure
? "s" : "ns");
1152 // we should never be overwriting a valid block
1153 assert(!blk
->isValid());
1155 // existing block... probably an upgrade
1156 assert(regenerateBlkAddr(blk
) == addr
);
1157 assert(blk
->isSecure() == is_secure
);
1158 // either we're getting new data or the block should already be valid
1159 assert(pkt
->hasData() || blk
->isValid());
1160 // don't clear block status... if block is already dirty we
1161 // don't want to lose that
1164 blk
->status
|= BlkValid
| BlkReadable
;
1166 // sanity check for whole-line writes, which should always be
1167 // marked as writable as part of the fill, and then later marked
1168 // dirty as part of satisfyRequest
1169 if (pkt
->cmd
== MemCmd::WriteLineReq
) {
1170 assert(!pkt
->hasSharers());
1173 // here we deal with setting the appropriate state of the line,
1174 // and we start by looking at the hasSharers flag, and ignore the
1175 // cacheResponding flag (normally signalling dirty data) if the
1176 // packet has sharers, thus the line is never allocated as Owned
1177 // (dirty but not writable), and always ends up being either
1178 // Shared, Exclusive or Modified, see Packet::setCacheResponding
1180 if (!pkt
->hasSharers()) {
1181 // we could get a writable line from memory (rather than a
1182 // cache) even in a read-only cache, note that we set this bit
1183 // even for a read-only cache, possibly revisit this decision
1184 blk
->status
|= BlkWritable
;
1186 // check if we got this via cache-to-cache transfer (i.e., from a
1187 // cache that had the block in Modified or Owned state)
1188 if (pkt
->cacheResponding()) {
1189 // we got the block in Modified state, and invalidated the
1191 blk
->status
|= BlkDirty
;
1193 chatty_assert(!isReadOnly
, "Should never see dirty snoop response "
1194 "in read-only cache %s\n", name());
1198 DPRINTF(Cache
, "Block addr %#llx (%s) moving from state %x to %s\n",
1199 addr
, is_secure
? "s" : "ns", old_state
, blk
->print());
1201 // if we got new data, copy it in (checking for a read response
1202 // and a response that has data is the same in the end)
1203 if (pkt
->isRead()) {
1205 assert(pkt
->hasData());
1206 assert(pkt
->getSize() == blkSize
);
1208 pkt
->writeDataToBlock(blk
->data
, blkSize
);
1210 // We pay for fillLatency here.
1211 blk
->whenReady
= clockEdge() + fillLatency
* clockPeriod() +
1218 BaseCache::allocateBlock(const PacketPtr pkt
, PacketList
&writebacks
)
1221 const Addr addr
= pkt
->getAddr();
1224 const bool is_secure
= pkt
->isSecure();
1226 // Find replacement victim
1227 std::vector
<CacheBlk
*> evict_blks
;
1228 CacheBlk
*victim
= tags
->findVictim(addr
, is_secure
, evict_blks
);
1230 // It is valid to return nullptr if there is no victim
1234 // Check for transient state allocations. If any of the entries listed
1235 // for eviction has a transient state, the allocation fails
1236 for (const auto& blk
: evict_blks
) {
1237 if (blk
->isValid()) {
1238 Addr repl_addr
= regenerateBlkAddr(blk
);
1239 MSHR
*repl_mshr
= mshrQueue
.findMatch(repl_addr
, blk
->isSecure());
1241 // must be an outstanding upgrade or clean request
1242 // on a block we're about to replace...
1243 assert((!blk
->isWritable() && repl_mshr
->needsWritable()) ||
1244 repl_mshr
->isCleaning());
1246 // too hard to replace block with transient state
1247 // allocation failed, block not inserted
1253 // The victim will be replaced by a new entry, so increase the replacement
1254 // counter if a valid block is being replaced
1255 if (victim
->isValid()) {
1256 DPRINTF(Cache
, "replacement: replacing %#llx (%s) with %#llx "
1257 "(%s): %s\n", regenerateBlkAddr(victim
),
1258 victim
->isSecure() ? "s" : "ns",
1259 addr
, is_secure
? "s" : "ns",
1260 victim
->isDirty() ? "writeback" : "clean");
1265 // Evict valid blocks associated to this victim block
1266 for (const auto& blk
: evict_blks
) {
1267 if (blk
->isValid()) {
1268 if (blk
->wasPrefetched()) {
1272 evictBlock(blk
, writebacks
);
1276 // Insert new block at victimized entry
1277 tags
->insertBlock(pkt
, victim
);
1283 BaseCache::invalidateBlock(CacheBlk
*blk
)
1285 if (blk
!= tempBlock
)
1286 tags
->invalidate(blk
);
1291 BaseCache::writebackBlk(CacheBlk
*blk
)
1293 chatty_assert(!isReadOnly
|| writebackClean
,
1294 "Writeback from read-only cache");
1295 assert(blk
&& blk
->isValid() && (blk
->isDirty() || writebackClean
));
1297 writebacks
[Request::wbMasterId
]++;
1299 RequestPtr req
= std::make_shared
<Request
>(
1300 regenerateBlkAddr(blk
), blkSize
, 0, Request::wbMasterId
);
1302 if (blk
->isSecure())
1303 req
->setFlags(Request::SECURE
);
1305 req
->taskId(blk
->task_id
);
1308 new Packet(req
, blk
->isDirty() ?
1309 MemCmd::WritebackDirty
: MemCmd::WritebackClean
);
1311 DPRINTF(Cache
, "Create Writeback %s writable: %d, dirty: %d\n",
1312 pkt
->print(), blk
->isWritable(), blk
->isDirty());
1314 if (blk
->isWritable()) {
1315 // not asserting shared means we pass the block in modified
1316 // state, mark our own block non-writeable
1317 blk
->status
&= ~BlkWritable
;
1319 // we are in the Owned state, tell the receiver
1320 pkt
->setHasSharers();
1323 // make sure the block is not marked dirty
1324 blk
->status
&= ~BlkDirty
;
1327 pkt
->setDataFromBlock(blk
->data
, blkSize
);
1333 BaseCache::writecleanBlk(CacheBlk
*blk
, Request::Flags dest
, PacketId id
)
1335 RequestPtr req
= std::make_shared
<Request
>(
1336 regenerateBlkAddr(blk
), blkSize
, 0, Request::wbMasterId
);
1338 if (blk
->isSecure()) {
1339 req
->setFlags(Request::SECURE
);
1341 req
->taskId(blk
->task_id
);
1343 PacketPtr pkt
= new Packet(req
, MemCmd::WriteClean
, blkSize
, id
);
1346 req
->setFlags(dest
);
1347 pkt
->setWriteThrough();
1350 DPRINTF(Cache
, "Create %s writable: %d, dirty: %d\n", pkt
->print(),
1351 blk
->isWritable(), blk
->isDirty());
1353 if (blk
->isWritable()) {
1354 // not asserting shared means we pass the block in modified
1355 // state, mark our own block non-writeable
1356 blk
->status
&= ~BlkWritable
;
1358 // we are in the Owned state, tell the receiver
1359 pkt
->setHasSharers();
1362 // make sure the block is not marked dirty
1363 blk
->status
&= ~BlkDirty
;
1366 pkt
->setDataFromBlock(blk
->data
, blkSize
);
1373 BaseCache::memWriteback()
1375 tags
->forEachBlk([this](CacheBlk
&blk
) { writebackVisitor(blk
); });
1379 BaseCache::memInvalidate()
1381 tags
->forEachBlk([this](CacheBlk
&blk
) { invalidateVisitor(blk
); });
1385 BaseCache::isDirty() const
1387 return tags
->anyBlk([](CacheBlk
&blk
) { return blk
.isDirty(); });
1391 BaseCache::writebackVisitor(CacheBlk
&blk
)
1393 if (blk
.isDirty()) {
1394 assert(blk
.isValid());
1396 RequestPtr request
= std::make_shared
<Request
>(
1397 regenerateBlkAddr(&blk
), blkSize
, 0, Request::funcMasterId
);
1399 request
->taskId(blk
.task_id
);
1400 if (blk
.isSecure()) {
1401 request
->setFlags(Request::SECURE
);
1404 Packet
packet(request
, MemCmd::WriteReq
);
1405 packet
.dataStatic(blk
.data
);
1407 memSidePort
.sendFunctional(&packet
);
1409 blk
.status
&= ~BlkDirty
;
1414 BaseCache::invalidateVisitor(CacheBlk
&blk
)
1417 warn_once("Invalidating dirty cache lines. " \
1418 "Expect things to break.\n");
1420 if (blk
.isValid()) {
1421 assert(!blk
.isDirty());
1422 invalidateBlock(&blk
);
1427 BaseCache::nextQueueReadyTime() const
1429 Tick nextReady
= std::min(mshrQueue
.nextReadyTime(),
1430 writeBuffer
.nextReadyTime());
1432 // Don't signal prefetch ready time if no MSHRs available
1433 // Will signal once enoguh MSHRs are deallocated
1434 if (prefetcher
&& mshrQueue
.canPrefetch()) {
1435 nextReady
= std::min(nextReady
,
1436 prefetcher
->nextPrefetchReadyTime());
1444 BaseCache::sendMSHRQueuePacket(MSHR
* mshr
)
1448 // use request from 1st target
1449 PacketPtr tgt_pkt
= mshr
->getTarget()->pkt
;
1451 DPRINTF(Cache
, "%s: MSHR %s\n", __func__
, tgt_pkt
->print());
1453 CacheBlk
*blk
= tags
->findBlock(mshr
->blkAddr
, mshr
->isSecure
);
1455 // either a prefetch that is not present upstream, or a normal
1456 // MSHR request, proceed to get the packet to send downstream
1457 PacketPtr pkt
= createMissPacket(tgt_pkt
, blk
, mshr
->needsWritable());
1459 mshr
->isForward
= (pkt
== nullptr);
1461 if (mshr
->isForward
) {
1462 // not a cache block request, but a response is expected
1463 // make copy of current packet to forward, keep current
1464 // copy for response handling
1465 pkt
= new Packet(tgt_pkt
, false, true);
1466 assert(!pkt
->isWrite());
1469 // play it safe and append (rather than set) the sender state,
1470 // as forwarded packets may already have existing state
1471 pkt
->pushSenderState(mshr
);
1473 if (pkt
->isClean() && blk
&& blk
->isDirty()) {
1474 // A cache clean opearation is looking for a dirty block. Mark
1475 // the packet so that the destination xbar can determine that
1476 // there will be a follow-up write packet as well.
1477 pkt
->setSatisfied();
1480 if (!memSidePort
.sendTimingReq(pkt
)) {
1481 // we are awaiting a retry, but we
1482 // delete the packet and will be creating a new packet
1483 // when we get the opportunity
1486 // note that we have now masked any requestBus and
1487 // schedSendEvent (we will wait for a retry before
1488 // doing anything), and this is so even if we do not
1489 // care about this packet and might override it before
1493 // As part of the call to sendTimingReq the packet is
1494 // forwarded to all neighbouring caches (and any caches
1495 // above them) as a snoop. Thus at this point we know if
1496 // any of the neighbouring caches are responding, and if
1497 // so, we know it is dirty, and we can determine if it is
1498 // being passed as Modified, making our MSHR the ordering
1500 bool pending_modified_resp
= !pkt
->hasSharers() &&
1501 pkt
->cacheResponding();
1502 markInService(mshr
, pending_modified_resp
);
1504 if (pkt
->isClean() && blk
&& blk
->isDirty()) {
1505 // A cache clean opearation is looking for a dirty
1506 // block. If a dirty block is encountered a WriteClean
1507 // will update any copies to the path to the memory
1508 // until the point of reference.
1509 DPRINTF(CacheVerbose
, "%s: packet %s found block: %s\n",
1510 __func__
, pkt
->print(), blk
->print());
1511 PacketPtr wb_pkt
= writecleanBlk(blk
, pkt
->req
->getDest(),
1513 PacketList writebacks
;
1514 writebacks
.push_back(wb_pkt
);
1515 doWritebacks(writebacks
, 0);
1523 BaseCache::sendWriteQueuePacket(WriteQueueEntry
* wq_entry
)
1527 // always a single target for write queue entries
1528 PacketPtr tgt_pkt
= wq_entry
->getTarget()->pkt
;
1530 DPRINTF(Cache
, "%s: write %s\n", __func__
, tgt_pkt
->print());
1532 // forward as is, both for evictions and uncacheable writes
1533 if (!memSidePort
.sendTimingReq(tgt_pkt
)) {
1534 // note that we have now masked any requestBus and
1535 // schedSendEvent (we will wait for a retry before
1536 // doing anything), and this is so even if we do not
1537 // care about this packet and might override it before
1541 markInService(wq_entry
);
1547 BaseCache::serialize(CheckpointOut
&cp
) const
1549 bool dirty(isDirty());
1552 warn("*** The cache still contains dirty data. ***\n");
1553 warn(" Make sure to drain the system using the correct flags.\n");
1554 warn(" This checkpoint will not restore correctly " \
1555 "and dirty data in the cache will be lost!\n");
1558 // Since we don't checkpoint the data in the cache, any dirty data
1559 // will be lost when restoring from a checkpoint of a system that
1560 // wasn't drained properly. Flag the checkpoint as invalid if the
1561 // cache contains dirty data.
1562 bool bad_checkpoint(dirty
);
1563 SERIALIZE_SCALAR(bad_checkpoint
);
1567 BaseCache::unserialize(CheckpointIn
&cp
)
1569 bool bad_checkpoint
;
1570 UNSERIALIZE_SCALAR(bad_checkpoint
);
1571 if (bad_checkpoint
) {
1572 fatal("Restoring from checkpoints with dirty caches is not "
1573 "supported in the classic memory system. Please remove any "
1574 "caches or drain them properly before taking checkpoints.\n");
1579 BaseCache::regStats()
1581 MemObject::regStats();
1583 using namespace Stats
;
1586 for (int access_idx
= 0; access_idx
< MemCmd::NUM_MEM_CMDS
; ++access_idx
) {
1587 MemCmd
cmd(access_idx
);
1588 const string
&cstr
= cmd
.toString();
1591 .init(system
->maxMasters())
1592 .name(name() + "." + cstr
+ "_hits")
1593 .desc("number of " + cstr
+ " hits")
1594 .flags(total
| nozero
| nonan
)
1596 for (int i
= 0; i
< system
->maxMasters(); i
++) {
1597 hits
[access_idx
].subname(i
, system
->getMasterName(i
));
1601 // These macros make it easier to sum the right subset of commands and
1602 // to change the subset of commands that are considered "demand" vs
1604 #define SUM_DEMAND(s) \
1605 (s[MemCmd::ReadReq] + s[MemCmd::WriteReq] + s[MemCmd::WriteLineReq] + \
1606 s[MemCmd::ReadExReq] + s[MemCmd::ReadCleanReq] + s[MemCmd::ReadSharedReq])
1608 // should writebacks be included here? prior code was inconsistent...
1609 #define SUM_NON_DEMAND(s) \
1610 (s[MemCmd::SoftPFReq] + s[MemCmd::HardPFReq])
1613 .name(name() + ".demand_hits")
1614 .desc("number of demand (read+write) hits")
1615 .flags(total
| nozero
| nonan
)
1617 demandHits
= SUM_DEMAND(hits
);
1618 for (int i
= 0; i
< system
->maxMasters(); i
++) {
1619 demandHits
.subname(i
, system
->getMasterName(i
));
1623 .name(name() + ".overall_hits")
1624 .desc("number of overall hits")
1625 .flags(total
| nozero
| nonan
)
1627 overallHits
= demandHits
+ SUM_NON_DEMAND(hits
);
1628 for (int i
= 0; i
< system
->maxMasters(); i
++) {
1629 overallHits
.subname(i
, system
->getMasterName(i
));
1633 for (int access_idx
= 0; access_idx
< MemCmd::NUM_MEM_CMDS
; ++access_idx
) {
1634 MemCmd
cmd(access_idx
);
1635 const string
&cstr
= cmd
.toString();
1638 .init(system
->maxMasters())
1639 .name(name() + "." + cstr
+ "_misses")
1640 .desc("number of " + cstr
+ " misses")
1641 .flags(total
| nozero
| nonan
)
1643 for (int i
= 0; i
< system
->maxMasters(); i
++) {
1644 misses
[access_idx
].subname(i
, system
->getMasterName(i
));
1649 .name(name() + ".demand_misses")
1650 .desc("number of demand (read+write) misses")
1651 .flags(total
| nozero
| nonan
)
1653 demandMisses
= SUM_DEMAND(misses
);
1654 for (int i
= 0; i
< system
->maxMasters(); i
++) {
1655 demandMisses
.subname(i
, system
->getMasterName(i
));
1659 .name(name() + ".overall_misses")
1660 .desc("number of overall misses")
1661 .flags(total
| nozero
| nonan
)
1663 overallMisses
= demandMisses
+ SUM_NON_DEMAND(misses
);
1664 for (int i
= 0; i
< system
->maxMasters(); i
++) {
1665 overallMisses
.subname(i
, system
->getMasterName(i
));
1668 // Miss latency statistics
1669 for (int access_idx
= 0; access_idx
< MemCmd::NUM_MEM_CMDS
; ++access_idx
) {
1670 MemCmd
cmd(access_idx
);
1671 const string
&cstr
= cmd
.toString();
1673 missLatency
[access_idx
]
1674 .init(system
->maxMasters())
1675 .name(name() + "." + cstr
+ "_miss_latency")
1676 .desc("number of " + cstr
+ " miss cycles")
1677 .flags(total
| nozero
| nonan
)
1679 for (int i
= 0; i
< system
->maxMasters(); i
++) {
1680 missLatency
[access_idx
].subname(i
, system
->getMasterName(i
));
1685 .name(name() + ".demand_miss_latency")
1686 .desc("number of demand (read+write) miss cycles")
1687 .flags(total
| nozero
| nonan
)
1689 demandMissLatency
= SUM_DEMAND(missLatency
);
1690 for (int i
= 0; i
< system
->maxMasters(); i
++) {
1691 demandMissLatency
.subname(i
, system
->getMasterName(i
));
1695 .name(name() + ".overall_miss_latency")
1696 .desc("number of overall miss cycles")
1697 .flags(total
| nozero
| nonan
)
1699 overallMissLatency
= demandMissLatency
+ SUM_NON_DEMAND(missLatency
);
1700 for (int i
= 0; i
< system
->maxMasters(); i
++) {
1701 overallMissLatency
.subname(i
, system
->getMasterName(i
));
1705 for (int access_idx
= 0; access_idx
< MemCmd::NUM_MEM_CMDS
; ++access_idx
) {
1706 MemCmd
cmd(access_idx
);
1707 const string
&cstr
= cmd
.toString();
1709 accesses
[access_idx
]
1710 .name(name() + "." + cstr
+ "_accesses")
1711 .desc("number of " + cstr
+ " accesses(hits+misses)")
1712 .flags(total
| nozero
| nonan
)
1714 accesses
[access_idx
] = hits
[access_idx
] + misses
[access_idx
];
1716 for (int i
= 0; i
< system
->maxMasters(); i
++) {
1717 accesses
[access_idx
].subname(i
, system
->getMasterName(i
));
1722 .name(name() + ".demand_accesses")
1723 .desc("number of demand (read+write) accesses")
1724 .flags(total
| nozero
| nonan
)
1726 demandAccesses
= demandHits
+ demandMisses
;
1727 for (int i
= 0; i
< system
->maxMasters(); i
++) {
1728 demandAccesses
.subname(i
, system
->getMasterName(i
));
1732 .name(name() + ".overall_accesses")
1733 .desc("number of overall (read+write) accesses")
1734 .flags(total
| nozero
| nonan
)
1736 overallAccesses
= overallHits
+ overallMisses
;
1737 for (int i
= 0; i
< system
->maxMasters(); i
++) {
1738 overallAccesses
.subname(i
, system
->getMasterName(i
));
1741 // miss rate formulas
1742 for (int access_idx
= 0; access_idx
< MemCmd::NUM_MEM_CMDS
; ++access_idx
) {
1743 MemCmd
cmd(access_idx
);
1744 const string
&cstr
= cmd
.toString();
1746 missRate
[access_idx
]
1747 .name(name() + "." + cstr
+ "_miss_rate")
1748 .desc("miss rate for " + cstr
+ " accesses")
1749 .flags(total
| nozero
| nonan
)
1751 missRate
[access_idx
] = misses
[access_idx
] / accesses
[access_idx
];
1753 for (int i
= 0; i
< system
->maxMasters(); i
++) {
1754 missRate
[access_idx
].subname(i
, system
->getMasterName(i
));
1759 .name(name() + ".demand_miss_rate")
1760 .desc("miss rate for demand accesses")
1761 .flags(total
| nozero
| nonan
)
1763 demandMissRate
= demandMisses
/ demandAccesses
;
1764 for (int i
= 0; i
< system
->maxMasters(); i
++) {
1765 demandMissRate
.subname(i
, system
->getMasterName(i
));
1769 .name(name() + ".overall_miss_rate")
1770 .desc("miss rate for overall accesses")
1771 .flags(total
| nozero
| nonan
)
1773 overallMissRate
= overallMisses
/ overallAccesses
;
1774 for (int i
= 0; i
< system
->maxMasters(); i
++) {
1775 overallMissRate
.subname(i
, system
->getMasterName(i
));
1778 // miss latency formulas
1779 for (int access_idx
= 0; access_idx
< MemCmd::NUM_MEM_CMDS
; ++access_idx
) {
1780 MemCmd
cmd(access_idx
);
1781 const string
&cstr
= cmd
.toString();
1783 avgMissLatency
[access_idx
]
1784 .name(name() + "." + cstr
+ "_avg_miss_latency")
1785 .desc("average " + cstr
+ " miss latency")
1786 .flags(total
| nozero
| nonan
)
1788 avgMissLatency
[access_idx
] =
1789 missLatency
[access_idx
] / misses
[access_idx
];
1791 for (int i
= 0; i
< system
->maxMasters(); i
++) {
1792 avgMissLatency
[access_idx
].subname(i
, system
->getMasterName(i
));
1796 demandAvgMissLatency
1797 .name(name() + ".demand_avg_miss_latency")
1798 .desc("average overall miss latency")
1799 .flags(total
| nozero
| nonan
)
1801 demandAvgMissLatency
= demandMissLatency
/ demandMisses
;
1802 for (int i
= 0; i
< system
->maxMasters(); i
++) {
1803 demandAvgMissLatency
.subname(i
, system
->getMasterName(i
));
1806 overallAvgMissLatency
1807 .name(name() + ".overall_avg_miss_latency")
1808 .desc("average overall miss latency")
1809 .flags(total
| nozero
| nonan
)
1811 overallAvgMissLatency
= overallMissLatency
/ overallMisses
;
1812 for (int i
= 0; i
< system
->maxMasters(); i
++) {
1813 overallAvgMissLatency
.subname(i
, system
->getMasterName(i
));
1816 blocked_cycles
.init(NUM_BLOCKED_CAUSES
);
1818 .name(name() + ".blocked_cycles")
1819 .desc("number of cycles access was blocked")
1820 .subname(Blocked_NoMSHRs
, "no_mshrs")
1821 .subname(Blocked_NoTargets
, "no_targets")
1825 blocked_causes
.init(NUM_BLOCKED_CAUSES
);
1827 .name(name() + ".blocked")
1828 .desc("number of cycles access was blocked")
1829 .subname(Blocked_NoMSHRs
, "no_mshrs")
1830 .subname(Blocked_NoTargets
, "no_targets")
1834 .name(name() + ".avg_blocked_cycles")
1835 .desc("average number of cycles each access was blocked")
1836 .subname(Blocked_NoMSHRs
, "no_mshrs")
1837 .subname(Blocked_NoTargets
, "no_targets")
1840 avg_blocked
= blocked_cycles
/ blocked_causes
;
1843 .name(name() + ".unused_prefetches")
1844 .desc("number of HardPF blocks evicted w/o reference")
1849 .init(system
->maxMasters())
1850 .name(name() + ".writebacks")
1851 .desc("number of writebacks")
1852 .flags(total
| nozero
| nonan
)
1854 for (int i
= 0; i
< system
->maxMasters(); i
++) {
1855 writebacks
.subname(i
, system
->getMasterName(i
));
1859 // MSHR hit statistics
1860 for (int access_idx
= 0; access_idx
< MemCmd::NUM_MEM_CMDS
; ++access_idx
) {
1861 MemCmd
cmd(access_idx
);
1862 const string
&cstr
= cmd
.toString();
1864 mshr_hits
[access_idx
]
1865 .init(system
->maxMasters())
1866 .name(name() + "." + cstr
+ "_mshr_hits")
1867 .desc("number of " + cstr
+ " MSHR hits")
1868 .flags(total
| nozero
| nonan
)
1870 for (int i
= 0; i
< system
->maxMasters(); i
++) {
1871 mshr_hits
[access_idx
].subname(i
, system
->getMasterName(i
));
1876 .name(name() + ".demand_mshr_hits")
1877 .desc("number of demand (read+write) MSHR hits")
1878 .flags(total
| nozero
| nonan
)
1880 demandMshrHits
= SUM_DEMAND(mshr_hits
);
1881 for (int i
= 0; i
< system
->maxMasters(); i
++) {
1882 demandMshrHits
.subname(i
, system
->getMasterName(i
));
1886 .name(name() + ".overall_mshr_hits")
1887 .desc("number of overall MSHR hits")
1888 .flags(total
| nozero
| nonan
)
1890 overallMshrHits
= demandMshrHits
+ SUM_NON_DEMAND(mshr_hits
);
1891 for (int i
= 0; i
< system
->maxMasters(); i
++) {
1892 overallMshrHits
.subname(i
, system
->getMasterName(i
));
1895 // MSHR miss statistics
1896 for (int access_idx
= 0; access_idx
< MemCmd::NUM_MEM_CMDS
; ++access_idx
) {
1897 MemCmd
cmd(access_idx
);
1898 const string
&cstr
= cmd
.toString();
1900 mshr_misses
[access_idx
]
1901 .init(system
->maxMasters())
1902 .name(name() + "." + cstr
+ "_mshr_misses")
1903 .desc("number of " + cstr
+ " MSHR misses")
1904 .flags(total
| nozero
| nonan
)
1906 for (int i
= 0; i
< system
->maxMasters(); i
++) {
1907 mshr_misses
[access_idx
].subname(i
, system
->getMasterName(i
));
1912 .name(name() + ".demand_mshr_misses")
1913 .desc("number of demand (read+write) MSHR misses")
1914 .flags(total
| nozero
| nonan
)
1916 demandMshrMisses
= SUM_DEMAND(mshr_misses
);
1917 for (int i
= 0; i
< system
->maxMasters(); i
++) {
1918 demandMshrMisses
.subname(i
, system
->getMasterName(i
));
1922 .name(name() + ".overall_mshr_misses")
1923 .desc("number of overall MSHR misses")
1924 .flags(total
| nozero
| nonan
)
1926 overallMshrMisses
= demandMshrMisses
+ SUM_NON_DEMAND(mshr_misses
);
1927 for (int i
= 0; i
< system
->maxMasters(); i
++) {
1928 overallMshrMisses
.subname(i
, system
->getMasterName(i
));
1931 // MSHR miss latency statistics
1932 for (int access_idx
= 0; access_idx
< MemCmd::NUM_MEM_CMDS
; ++access_idx
) {
1933 MemCmd
cmd(access_idx
);
1934 const string
&cstr
= cmd
.toString();
1936 mshr_miss_latency
[access_idx
]
1937 .init(system
->maxMasters())
1938 .name(name() + "." + cstr
+ "_mshr_miss_latency")
1939 .desc("number of " + cstr
+ " MSHR miss cycles")
1940 .flags(total
| nozero
| nonan
)
1942 for (int i
= 0; i
< system
->maxMasters(); i
++) {
1943 mshr_miss_latency
[access_idx
].subname(i
, system
->getMasterName(i
));
1947 demandMshrMissLatency
1948 .name(name() + ".demand_mshr_miss_latency")
1949 .desc("number of demand (read+write) MSHR miss cycles")
1950 .flags(total
| nozero
| nonan
)
1952 demandMshrMissLatency
= SUM_DEMAND(mshr_miss_latency
);
1953 for (int i
= 0; i
< system
->maxMasters(); i
++) {
1954 demandMshrMissLatency
.subname(i
, system
->getMasterName(i
));
1957 overallMshrMissLatency
1958 .name(name() + ".overall_mshr_miss_latency")
1959 .desc("number of overall MSHR miss cycles")
1960 .flags(total
| nozero
| nonan
)
1962 overallMshrMissLatency
=
1963 demandMshrMissLatency
+ SUM_NON_DEMAND(mshr_miss_latency
);
1964 for (int i
= 0; i
< system
->maxMasters(); i
++) {
1965 overallMshrMissLatency
.subname(i
, system
->getMasterName(i
));
1968 // MSHR uncacheable statistics
1969 for (int access_idx
= 0; access_idx
< MemCmd::NUM_MEM_CMDS
; ++access_idx
) {
1970 MemCmd
cmd(access_idx
);
1971 const string
&cstr
= cmd
.toString();
1973 mshr_uncacheable
[access_idx
]
1974 .init(system
->maxMasters())
1975 .name(name() + "." + cstr
+ "_mshr_uncacheable")
1976 .desc("number of " + cstr
+ " MSHR uncacheable")
1977 .flags(total
| nozero
| nonan
)
1979 for (int i
= 0; i
< system
->maxMasters(); i
++) {
1980 mshr_uncacheable
[access_idx
].subname(i
, system
->getMasterName(i
));
1984 overallMshrUncacheable
1985 .name(name() + ".overall_mshr_uncacheable_misses")
1986 .desc("number of overall MSHR uncacheable misses")
1987 .flags(total
| nozero
| nonan
)
1989 overallMshrUncacheable
=
1990 SUM_DEMAND(mshr_uncacheable
) + SUM_NON_DEMAND(mshr_uncacheable
);
1991 for (int i
= 0; i
< system
->maxMasters(); i
++) {
1992 overallMshrUncacheable
.subname(i
, system
->getMasterName(i
));
1995 // MSHR miss latency statistics
1996 for (int access_idx
= 0; access_idx
< MemCmd::NUM_MEM_CMDS
; ++access_idx
) {
1997 MemCmd
cmd(access_idx
);
1998 const string
&cstr
= cmd
.toString();
2000 mshr_uncacheable_lat
[access_idx
]
2001 .init(system
->maxMasters())
2002 .name(name() + "." + cstr
+ "_mshr_uncacheable_latency")
2003 .desc("number of " + cstr
+ " MSHR uncacheable cycles")
2004 .flags(total
| nozero
| nonan
)
2006 for (int i
= 0; i
< system
->maxMasters(); i
++) {
2007 mshr_uncacheable_lat
[access_idx
].subname(
2008 i
, system
->getMasterName(i
));
2012 overallMshrUncacheableLatency
2013 .name(name() + ".overall_mshr_uncacheable_latency")
2014 .desc("number of overall MSHR uncacheable cycles")
2015 .flags(total
| nozero
| nonan
)
2017 overallMshrUncacheableLatency
=
2018 SUM_DEMAND(mshr_uncacheable_lat
) +
2019 SUM_NON_DEMAND(mshr_uncacheable_lat
);
2020 for (int i
= 0; i
< system
->maxMasters(); i
++) {
2021 overallMshrUncacheableLatency
.subname(i
, system
->getMasterName(i
));
2025 // MSHR access formulas
2026 for (int access_idx
= 0; access_idx
< MemCmd::NUM_MEM_CMDS
; ++access_idx
) {
2027 MemCmd
cmd(access_idx
);
2028 const string
&cstr
= cmd
.toString();
2030 mshrAccesses
[access_idx
]
2031 .name(name() + "." + cstr
+ "_mshr_accesses")
2032 .desc("number of " + cstr
+ " mshr accesses(hits+misses)")
2033 .flags(total
| nozero
| nonan
)
2035 mshrAccesses
[access_idx
] =
2036 mshr_hits
[access_idx
] + mshr_misses
[access_idx
]
2037 + mshr_uncacheable
[access_idx
];
2041 .name(name() + ".demand_mshr_accesses")
2042 .desc("number of demand (read+write) mshr accesses")
2043 .flags(total
| nozero
| nonan
)
2045 demandMshrAccesses
= demandMshrHits
+ demandMshrMisses
;
2048 .name(name() + ".overall_mshr_accesses")
2049 .desc("number of overall (read+write) mshr accesses")
2050 .flags(total
| nozero
| nonan
)
2052 overallMshrAccesses
= overallMshrHits
+ overallMshrMisses
2053 + overallMshrUncacheable
;
2056 // MSHR miss rate formulas
2057 for (int access_idx
= 0; access_idx
< MemCmd::NUM_MEM_CMDS
; ++access_idx
) {
2058 MemCmd
cmd(access_idx
);
2059 const string
&cstr
= cmd
.toString();
2061 mshrMissRate
[access_idx
]
2062 .name(name() + "." + cstr
+ "_mshr_miss_rate")
2063 .desc("mshr miss rate for " + cstr
+ " accesses")
2064 .flags(total
| nozero
| nonan
)
2066 mshrMissRate
[access_idx
] =
2067 mshr_misses
[access_idx
] / accesses
[access_idx
];
2069 for (int i
= 0; i
< system
->maxMasters(); i
++) {
2070 mshrMissRate
[access_idx
].subname(i
, system
->getMasterName(i
));
2075 .name(name() + ".demand_mshr_miss_rate")
2076 .desc("mshr miss rate for demand accesses")
2077 .flags(total
| nozero
| nonan
)
2079 demandMshrMissRate
= demandMshrMisses
/ demandAccesses
;
2080 for (int i
= 0; i
< system
->maxMasters(); i
++) {
2081 demandMshrMissRate
.subname(i
, system
->getMasterName(i
));
2085 .name(name() + ".overall_mshr_miss_rate")
2086 .desc("mshr miss rate for overall accesses")
2087 .flags(total
| nozero
| nonan
)
2089 overallMshrMissRate
= overallMshrMisses
/ overallAccesses
;
2090 for (int i
= 0; i
< system
->maxMasters(); i
++) {
2091 overallMshrMissRate
.subname(i
, system
->getMasterName(i
));
2094 // mshrMiss latency formulas
2095 for (int access_idx
= 0; access_idx
< MemCmd::NUM_MEM_CMDS
; ++access_idx
) {
2096 MemCmd
cmd(access_idx
);
2097 const string
&cstr
= cmd
.toString();
2099 avgMshrMissLatency
[access_idx
]
2100 .name(name() + "." + cstr
+ "_avg_mshr_miss_latency")
2101 .desc("average " + cstr
+ " mshr miss latency")
2102 .flags(total
| nozero
| nonan
)
2104 avgMshrMissLatency
[access_idx
] =
2105 mshr_miss_latency
[access_idx
] / mshr_misses
[access_idx
];
2107 for (int i
= 0; i
< system
->maxMasters(); i
++) {
2108 avgMshrMissLatency
[access_idx
].subname(
2109 i
, system
->getMasterName(i
));
2113 demandAvgMshrMissLatency
2114 .name(name() + ".demand_avg_mshr_miss_latency")
2115 .desc("average overall mshr miss latency")
2116 .flags(total
| nozero
| nonan
)
2118 demandAvgMshrMissLatency
= demandMshrMissLatency
/ demandMshrMisses
;
2119 for (int i
= 0; i
< system
->maxMasters(); i
++) {
2120 demandAvgMshrMissLatency
.subname(i
, system
->getMasterName(i
));
2123 overallAvgMshrMissLatency
2124 .name(name() + ".overall_avg_mshr_miss_latency")
2125 .desc("average overall mshr miss latency")
2126 .flags(total
| nozero
| nonan
)
2128 overallAvgMshrMissLatency
= overallMshrMissLatency
/ overallMshrMisses
;
2129 for (int i
= 0; i
< system
->maxMasters(); i
++) {
2130 overallAvgMshrMissLatency
.subname(i
, system
->getMasterName(i
));
2133 // mshrUncacheable latency formulas
2134 for (int access_idx
= 0; access_idx
< MemCmd::NUM_MEM_CMDS
; ++access_idx
) {
2135 MemCmd
cmd(access_idx
);
2136 const string
&cstr
= cmd
.toString();
2138 avgMshrUncacheableLatency
[access_idx
]
2139 .name(name() + "." + cstr
+ "_avg_mshr_uncacheable_latency")
2140 .desc("average " + cstr
+ " mshr uncacheable latency")
2141 .flags(total
| nozero
| nonan
)
2143 avgMshrUncacheableLatency
[access_idx
] =
2144 mshr_uncacheable_lat
[access_idx
] / mshr_uncacheable
[access_idx
];
2146 for (int i
= 0; i
< system
->maxMasters(); i
++) {
2147 avgMshrUncacheableLatency
[access_idx
].subname(
2148 i
, system
->getMasterName(i
));
2152 overallAvgMshrUncacheableLatency
2153 .name(name() + ".overall_avg_mshr_uncacheable_latency")
2154 .desc("average overall mshr uncacheable latency")
2155 .flags(total
| nozero
| nonan
)
2157 overallAvgMshrUncacheableLatency
=
2158 overallMshrUncacheableLatency
/ overallMshrUncacheable
;
2159 for (int i
= 0; i
< system
->maxMasters(); i
++) {
2160 overallAvgMshrUncacheableLatency
.subname(i
, system
->getMasterName(i
));
2164 .name(name() + ".replacements")
2165 .desc("number of replacements")
2175 BaseCache::CpuSidePort::recvTimingSnoopResp(PacketPtr pkt
)
2177 // Snoops shouldn't happen when bypassing caches
2178 assert(!cache
->system
->bypassCaches());
2180 assert(pkt
->isResponse());
2182 // Express snoop responses from master to slave, e.g., from L1 to L2
2183 cache
->recvTimingSnoopResp(pkt
);
2189 BaseCache::CpuSidePort::tryTiming(PacketPtr pkt
)
2191 if (cache
->system
->bypassCaches() || pkt
->isExpressSnoop()) {
2192 // always let express snoop packets through even if blocked
2194 } else if (blocked
|| mustSendRetry
) {
2195 // either already committed to send a retry, or blocked
2196 mustSendRetry
= true;
2199 mustSendRetry
= false;
2204 BaseCache::CpuSidePort::recvTimingReq(PacketPtr pkt
)
2206 assert(pkt
->isRequest());
2208 if (cache
->system
->bypassCaches()) {
2209 // Just forward the packet if caches are disabled.
2210 // @todo This should really enqueue the packet rather
2211 bool M5_VAR_USED success
= cache
->memSidePort
.sendTimingReq(pkt
);
2214 } else if (tryTiming(pkt
)) {
2215 cache
->recvTimingReq(pkt
);
2222 BaseCache::CpuSidePort::recvAtomic(PacketPtr pkt
)
2224 if (cache
->system
->bypassCaches()) {
2225 // Forward the request if the system is in cache bypass mode.
2226 return cache
->memSidePort
.sendAtomic(pkt
);
2228 return cache
->recvAtomic(pkt
);
2233 BaseCache::CpuSidePort::recvFunctional(PacketPtr pkt
)
2235 if (cache
->system
->bypassCaches()) {
2236 // The cache should be flushed if we are in cache bypass mode,
2237 // so we don't need to check if we need to update anything.
2238 cache
->memSidePort
.sendFunctional(pkt
);
2242 // functional request
2243 cache
->functionalAccess(pkt
, true);
2247 BaseCache::CpuSidePort::getAddrRanges() const
2249 return cache
->getAddrRanges();
2254 CpuSidePort::CpuSidePort(const std::string
&_name
, BaseCache
*_cache
,
2255 const std::string
&_label
)
2256 : CacheSlavePort(_name
, _cache
, _label
), cache(_cache
)
2266 BaseCache::MemSidePort::recvTimingResp(PacketPtr pkt
)
2268 cache
->recvTimingResp(pkt
);
2272 // Express snooping requests to memside port
2274 BaseCache::MemSidePort::recvTimingSnoopReq(PacketPtr pkt
)
2276 // Snoops shouldn't happen when bypassing caches
2277 assert(!cache
->system
->bypassCaches());
2279 // handle snooping requests
2280 cache
->recvTimingSnoopReq(pkt
);
2284 BaseCache::MemSidePort::recvAtomicSnoop(PacketPtr pkt
)
2286 // Snoops shouldn't happen when bypassing caches
2287 assert(!cache
->system
->bypassCaches());
2289 return cache
->recvAtomicSnoop(pkt
);
2293 BaseCache::MemSidePort::recvFunctionalSnoop(PacketPtr pkt
)
2295 // Snoops shouldn't happen when bypassing caches
2296 assert(!cache
->system
->bypassCaches());
2298 // functional snoop (note that in contrast to atomic we don't have
2299 // a specific functionalSnoop method, as they have the same
2300 // behaviour regardless)
2301 cache
->functionalAccess(pkt
, false);
2305 BaseCache::CacheReqPacketQueue::sendDeferredPacket()
2308 assert(!waitingOnRetry
);
2310 // there should never be any deferred request packets in the
2311 // queue, instead we resly on the cache to provide the packets
2312 // from the MSHR queue or write queue
2313 assert(deferredPacketReadyTime() == MaxTick
);
2315 // check for request packets (requests & writebacks)
2316 QueueEntry
* entry
= cache
.getNextQueueEntry();
2319 // can happen if e.g. we attempt a writeback and fail, but
2320 // before the retry, the writeback is eliminated because
2321 // we snoop another cache's ReadEx.
2323 // let our snoop responses go first if there are responses to
2324 // the same addresses
2325 if (checkConflictingSnoop(entry
->blkAddr
)) {
2328 waitingOnRetry
= entry
->sendPacket(cache
);
2331 // if we succeeded and are not waiting for a retry, schedule the
2332 // next send considering when the next queue is ready, note that
2333 // snoop responses have their own packet queue and thus schedule
2335 if (!waitingOnRetry
) {
2336 schedSendEvent(cache
.nextQueueReadyTime());
2340 BaseCache::MemSidePort::MemSidePort(const std::string
&_name
,
2342 const std::string
&_label
)
2343 : CacheMasterPort(_name
, _cache
, _reqQueue
, _snoopRespQueue
),
2344 _reqQueue(*_cache
, *this, _snoopRespQueue
, _label
),
2345 _snoopRespQueue(*_cache
, *this, _label
), cache(_cache
)