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40 * Authors: Erik Hallnor
46 * Definition of BaseCache functions.
49 #include "mem/cache/base.hh"
51 #include "base/compiler.hh"
52 #include "base/logging.hh"
53 #include "debug/Cache.hh"
54 #include "debug/CachePort.hh"
55 #include "debug/CacheVerbose.hh"
56 #include "mem/cache/mshr.hh"
57 #include "mem/cache/prefetch/base.hh"
58 #include "mem/cache/queue_entry.hh"
59 #include "params/BaseCache.hh"
60 #include "sim/core.hh"
67 BaseCache::CacheSlavePort::CacheSlavePort(const std::string
&_name
,
69 const std::string
&_label
)
70 : QueuedSlavePort(_name
, _cache
, queue
), queue(*_cache
, *this, _label
),
71 blocked(false), mustSendRetry(false),
72 sendRetryEvent([this]{ processSendRetry(); }, _name
)
76 BaseCache::BaseCache(const BaseCacheParams
*p
, unsigned blk_size
)
78 cpuSidePort (p
->name
+ ".cpu_side", this, "CpuSidePort"),
79 memSidePort(p
->name
+ ".mem_side", this, "MemSidePort"),
80 mshrQueue("MSHRs", p
->mshrs
, 0, p
->demand_mshr_reserve
), // see below
81 writeBuffer("write buffer", p
->write_buffers
, p
->mshrs
), // see below
83 prefetcher(p
->prefetcher
),
84 prefetchOnAccess(p
->prefetch_on_access
),
85 writebackClean(p
->writeback_clean
),
86 tempBlockWriteback(nullptr),
87 writebackTempBlockAtomicEvent([this]{ writebackTempBlockAtomic(); },
89 EventBase::Delayed_Writeback_Pri
),
91 lookupLatency(p
->tag_latency
),
92 dataLatency(p
->data_latency
),
93 forwardLatency(p
->tag_latency
),
94 fillLatency(p
->data_latency
),
95 responseLatency(p
->response_latency
),
96 numTarget(p
->tgts_per_mshr
),
98 clusivity(p
->clusivity
),
99 isReadOnly(p
->is_read_only
),
102 noTargetMSHR(nullptr),
103 missCount(p
->max_miss_count
),
104 addrRanges(p
->addr_ranges
.begin(), p
->addr_ranges
.end()),
107 // the MSHR queue has no reserve entries as we check the MSHR
108 // queue on every single allocation, whereas the write queue has
109 // as many reserve entries as we have MSHRs, since every MSHR may
110 // eventually require a writeback, and we do not check the write
111 // buffer before committing to an MSHR
113 // forward snoops is overridden in init() once we can query
114 // whether the connected master is actually snooping or not
116 tempBlock
= new CacheBlk();
117 tempBlock
->data
= new uint8_t[blkSize
];
119 tags
->setCache(this);
121 prefetcher
->setCache(this);
124 BaseCache::~BaseCache()
126 delete [] tempBlock
->data
;
131 BaseCache::CacheSlavePort::setBlocked()
134 DPRINTF(CachePort
, "Port is blocking new requests\n");
136 // if we already scheduled a retry in this cycle, but it has not yet
137 // happened, cancel it
138 if (sendRetryEvent
.scheduled()) {
139 owner
.deschedule(sendRetryEvent
);
140 DPRINTF(CachePort
, "Port descheduled retry\n");
141 mustSendRetry
= true;
146 BaseCache::CacheSlavePort::clearBlocked()
149 DPRINTF(CachePort
, "Port is accepting new requests\n");
152 // @TODO: need to find a better time (next cycle?)
153 owner
.schedule(sendRetryEvent
, curTick() + 1);
158 BaseCache::CacheSlavePort::processSendRetry()
160 DPRINTF(CachePort
, "Port is sending retry\n");
162 // reset the flag and call retry
163 mustSendRetry
= false;
170 if (!cpuSidePort
.isConnected() || !memSidePort
.isConnected())
171 fatal("Cache ports on %s are not connected\n", name());
172 cpuSidePort
.sendRangeChange();
173 forwardSnoops
= cpuSidePort
.isSnooping();
177 BaseCache::getMasterPort(const std::string
&if_name
, PortID idx
)
179 if (if_name
== "mem_side") {
182 return MemObject::getMasterPort(if_name
, idx
);
187 BaseCache::getSlavePort(const std::string
&if_name
, PortID idx
)
189 if (if_name
== "cpu_side") {
192 return MemObject::getSlavePort(if_name
, idx
);
197 BaseCache::inRange(Addr addr
) const
199 for (const auto& r
: addrRanges
) {
200 if (r
.contains(addr
)) {
208 BaseCache::handleTimingReqHit(PacketPtr pkt
, CacheBlk
*blk
, Tick request_time
)
210 if (pkt
->needsResponse()) {
211 pkt
->makeTimingResponse();
212 // @todo: Make someone pay for this
213 pkt
->headerDelay
= pkt
->payloadDelay
= 0;
215 // In this case we are considering request_time that takes
216 // into account the delay of the xbar, if any, and just
217 // lat, neglecting responseLatency, modelling hit latency
218 // just as lookupLatency or or the value of lat overriden
219 // by access(), that calls accessBlock() function.
220 cpuSidePort
.schedTimingResp(pkt
, request_time
, true);
222 DPRINTF(Cache
, "%s satisfied %s, no response needed\n", __func__
,
225 // queue the packet for deletion, as the sending cache is
226 // still relying on it; if the block is found in access(),
227 // CleanEvict and Writeback messages will be deleted
229 pendingDelete
.reset(pkt
);
234 BaseCache::handleTimingReqMiss(PacketPtr pkt
, MSHR
*mshr
, CacheBlk
*blk
,
235 Tick forward_time
, Tick request_time
)
239 /// @note writebacks will be checked in getNextMSHR()
240 /// for any conflicting requests to the same block
242 //@todo remove hw_pf here
244 // Coalesce unless it was a software prefetch (see above).
246 assert(!pkt
->isWriteback());
247 // CleanEvicts corresponding to blocks which have
248 // outstanding requests in MSHRs are simply sunk here
249 if (pkt
->cmd
== MemCmd::CleanEvict
) {
250 pendingDelete
.reset(pkt
);
251 } else if (pkt
->cmd
== MemCmd::WriteClean
) {
252 // A WriteClean should never coalesce with any
253 // outstanding cache maintenance requests.
255 // We use forward_time here because there is an
256 // uncached memory write, forwarded to WriteBuffer.
257 allocateWriteBuffer(pkt
, forward_time
);
259 DPRINTF(Cache
, "%s coalescing MSHR for %s\n", __func__
,
262 assert(pkt
->req
->masterId() < system
->maxMasters());
263 mshr_hits
[pkt
->cmdToIndex()][pkt
->req
->masterId()]++;
265 // We use forward_time here because it is the same
266 // considering new targets. We have multiple
267 // requests for the same address here. It
268 // specifies the latency to allocate an internal
269 // buffer and to schedule an event to the queued
270 // port and also takes into account the additional
271 // delay of the xbar.
272 mshr
->allocateTarget(pkt
, forward_time
, order
++,
273 allocOnFill(pkt
->cmd
));
274 if (mshr
->getNumTargets() == numTarget
) {
276 setBlocked(Blocked_NoTargets
);
277 // need to be careful with this... if this mshr isn't
278 // ready yet (i.e. time > curTick()), we don't want to
279 // move it ahead of mshrs that are ready
280 // mshrQueue.moveToFront(mshr);
286 assert(pkt
->req
->masterId() < system
->maxMasters());
287 mshr_misses
[pkt
->cmdToIndex()][pkt
->req
->masterId()]++;
289 if (pkt
->isEviction() || pkt
->cmd
== MemCmd::WriteClean
) {
290 // We use forward_time here because there is an
291 // writeback or writeclean, forwarded to WriteBuffer.
292 allocateWriteBuffer(pkt
, forward_time
);
294 if (blk
&& blk
->isValid()) {
295 // If we have a write miss to a valid block, we
296 // need to mark the block non-readable. Otherwise
297 // if we allow reads while there's an outstanding
298 // write miss, the read could return stale data
299 // out of the cache block... a more aggressive
300 // system could detect the overlap (if any) and
301 // forward data out of the MSHRs, but we don't do
302 // that yet. Note that we do need to leave the
303 // block valid so that it stays in the cache, in
304 // case we get an upgrade response (and hence no
305 // new data) when the write miss completes.
306 // As long as CPUs do proper store/load forwarding
307 // internally, and have a sufficiently weak memory
308 // model, this is probably unnecessary, but at some
309 // point it must have seemed like we needed it...
310 assert((pkt
->needsWritable() && !blk
->isWritable()) ||
311 pkt
->req
->isCacheMaintenance());
312 blk
->status
&= ~BlkReadable
;
314 // Here we are using forward_time, modelling the latency of
315 // a miss (outbound) just as forwardLatency, neglecting the
316 // lookupLatency component.
317 allocateMissBuffer(pkt
, forward_time
);
323 BaseCache::recvTimingReq(PacketPtr pkt
)
325 // anything that is merely forwarded pays for the forward latency and
326 // the delay provided by the crossbar
327 Tick forward_time
= clockEdge(forwardLatency
) + pkt
->headerDelay
;
329 // We use lookupLatency here because it is used to specify the latency
331 Cycles lat
= lookupLatency
;
332 CacheBlk
*blk
= nullptr;
333 bool satisfied
= false;
335 PacketList writebacks
;
336 // Note that lat is passed by reference here. The function
337 // access() calls accessBlock() which can modify lat value.
338 satisfied
= access(pkt
, blk
, lat
, writebacks
);
340 // copy writebacks to write buffer here to ensure they logically
341 // proceed anything happening below
342 doWritebacks(writebacks
, forward_time
);
345 // Here we charge the headerDelay that takes into account the latencies
346 // of the bus, if the packet comes from it.
347 // The latency charged it is just lat that is the value of lookupLatency
348 // modified by access() function, or if not just lookupLatency.
349 // In case of a hit we are neglecting response latency.
350 // In case of a miss we are neglecting forward latency.
351 Tick request_time
= clockEdge(lat
) + pkt
->headerDelay
;
352 // Here we reset the timing of the packet.
353 pkt
->headerDelay
= pkt
->payloadDelay
= 0;
354 // track time of availability of next prefetch, if any
355 Tick next_pf_time
= MaxTick
;
358 // if need to notify the prefetcher we have to do it before
359 // anything else as later handleTimingReqHit might turn the
360 // packet in a response
362 (prefetchOnAccess
|| (blk
&& blk
->wasPrefetched()))) {
364 blk
->status
&= ~BlkHWPrefetched
;
366 // Don't notify on SWPrefetch
367 if (!pkt
->cmd
.isSWPrefetch()) {
368 assert(!pkt
->req
->isCacheMaintenance());
369 next_pf_time
= prefetcher
->notify(pkt
);
373 handleTimingReqHit(pkt
, blk
, request_time
);
375 handleTimingReqMiss(pkt
, blk
, forward_time
, request_time
);
377 // We should call the prefetcher reguardless if the request is
378 // satisfied or not, reguardless if the request is in the MSHR
379 // or not. The request could be a ReadReq hit, but still not
380 // satisfied (potentially because of a prior write to the same
381 // cache line. So, even when not satisfied, there is an MSHR
382 // already allocated for this, we need to let the prefetcher
383 // know about the request
385 // Don't notify prefetcher on SWPrefetch or cache maintenance
387 if (prefetcher
&& pkt
&&
388 !pkt
->cmd
.isSWPrefetch() &&
389 !pkt
->req
->isCacheMaintenance()) {
390 next_pf_time
= prefetcher
->notify(pkt
);
394 if (next_pf_time
!= MaxTick
) {
395 schedMemSideSendEvent(next_pf_time
);
400 BaseCache::handleUncacheableWriteResp(PacketPtr pkt
)
402 Tick completion_time
= clockEdge(responseLatency
) +
403 pkt
->headerDelay
+ pkt
->payloadDelay
;
405 // Reset the bus additional time as it is now accounted for
406 pkt
->headerDelay
= pkt
->payloadDelay
= 0;
408 cpuSidePort
.schedTimingResp(pkt
, completion_time
, true);
412 BaseCache::recvTimingResp(PacketPtr pkt
)
414 assert(pkt
->isResponse());
416 // all header delay should be paid for by the crossbar, unless
417 // this is a prefetch response from above
418 panic_if(pkt
->headerDelay
!= 0 && pkt
->cmd
!= MemCmd::HardPFResp
,
419 "%s saw a non-zero packet delay\n", name());
421 const bool is_error
= pkt
->isError();
424 DPRINTF(Cache
, "%s: Cache received %s with error\n", __func__
,
428 DPRINTF(Cache
, "%s: Handling response %s\n", __func__
,
431 // if this is a write, we should be looking at an uncacheable
433 if (pkt
->isWrite()) {
434 assert(pkt
->req
->isUncacheable());
435 handleUncacheableWriteResp(pkt
);
439 // we have dealt with any (uncacheable) writes above, from here on
440 // we know we are dealing with an MSHR due to a miss or a prefetch
441 MSHR
*mshr
= dynamic_cast<MSHR
*>(pkt
->popSenderState());
444 if (mshr
== noTargetMSHR
) {
445 // we always clear at least one target
446 clearBlocked(Blocked_NoTargets
);
447 noTargetMSHR
= nullptr;
450 // Initial target is used just for stats
451 MSHR::Target
*initial_tgt
= mshr
->getTarget();
452 int stats_cmd_idx
= initial_tgt
->pkt
->cmdToIndex();
453 Tick miss_latency
= curTick() - initial_tgt
->recvTime
;
455 if (pkt
->req
->isUncacheable()) {
456 assert(pkt
->req
->masterId() < system
->maxMasters());
457 mshr_uncacheable_lat
[stats_cmd_idx
][pkt
->req
->masterId()] +=
460 assert(pkt
->req
->masterId() < system
->maxMasters());
461 mshr_miss_latency
[stats_cmd_idx
][pkt
->req
->masterId()] +=
465 PacketList writebacks
;
467 bool is_fill
= !mshr
->isForward
&&
468 (pkt
->isRead() || pkt
->cmd
== MemCmd::UpgradeResp
);
470 CacheBlk
*blk
= tags
->findBlock(pkt
->getAddr(), pkt
->isSecure());
472 if (is_fill
&& !is_error
) {
473 DPRINTF(Cache
, "Block for addr %#llx being updated in Cache\n",
476 blk
= handleFill(pkt
, blk
, writebacks
, mshr
->allocOnFill());
477 assert(blk
!= nullptr);
480 if (blk
&& blk
->isValid() && pkt
->isClean() && !pkt
->isInvalidate()) {
481 // The block was marked not readable while there was a pending
482 // cache maintenance operation, restore its flag.
483 blk
->status
|= BlkReadable
;
486 if (blk
&& blk
->isWritable() && !pkt
->req
->isCacheInvalidate()) {
487 // If at this point the referenced block is writable and the
488 // response is not a cache invalidate, we promote targets that
489 // were deferred as we couldn't guarrantee a writable copy
490 mshr
->promoteWritable();
493 serviceMSHRTargets(mshr
, pkt
, blk
, writebacks
);
495 if (mshr
->promoteDeferredTargets()) {
496 // avoid later read getting stale data while write miss is
497 // outstanding.. see comment in timingAccess()
499 blk
->status
&= ~BlkReadable
;
501 mshrQueue
.markPending(mshr
);
502 schedMemSideSendEvent(clockEdge() + pkt
->payloadDelay
);
504 // while we deallocate an mshr from the queue we still have to
505 // check the isFull condition before and after as we might
506 // have been using the reserved entries already
507 const bool was_full
= mshrQueue
.isFull();
508 mshrQueue
.deallocate(mshr
);
509 if (was_full
&& !mshrQueue
.isFull()) {
510 clearBlocked(Blocked_NoMSHRs
);
513 // Request the bus for a prefetch if this deallocation freed enough
514 // MSHRs for a prefetch to take place
515 if (prefetcher
&& mshrQueue
.canPrefetch()) {
516 Tick next_pf_time
= std::max(prefetcher
->nextPrefetchReadyTime(),
518 if (next_pf_time
!= MaxTick
)
519 schedMemSideSendEvent(next_pf_time
);
523 // if we used temp block, check to see if its valid and then clear it out
524 if (blk
== tempBlock
&& tempBlock
->isValid()) {
525 evictBlock(blk
, writebacks
);
528 const Tick forward_time
= clockEdge(forwardLatency
) + pkt
->headerDelay
;
529 // copy writebacks to write buffer
530 doWritebacks(writebacks
, forward_time
);
532 DPRINTF(CacheVerbose
, "%s: Leaving with %s\n", __func__
, pkt
->print());
538 BaseCache::recvAtomic(PacketPtr pkt
)
540 // We are in atomic mode so we pay just for lookupLatency here.
541 Cycles lat
= lookupLatency
;
543 // follow the same flow as in recvTimingReq, and check if a cache
544 // above us is responding
545 if (pkt
->cacheResponding() && !pkt
->isClean()) {
546 assert(!pkt
->req
->isCacheInvalidate());
547 DPRINTF(Cache
, "Cache above responding to %s: not responding\n",
550 // if a cache is responding, and it had the line in Owned
551 // rather than Modified state, we need to invalidate any
552 // copies that are not on the same path to memory
553 assert(pkt
->needsWritable() && !pkt
->responderHadWritable());
554 lat
+= ticksToCycles(memSidePort
.sendAtomic(pkt
));
556 return lat
* clockPeriod();
559 // should assert here that there are no outstanding MSHRs or
560 // writebacks... that would mean that someone used an atomic
561 // access in timing mode
563 CacheBlk
*blk
= nullptr;
564 PacketList writebacks
;
565 bool satisfied
= access(pkt
, blk
, lat
, writebacks
);
567 if (pkt
->isClean() && blk
&& blk
->isDirty()) {
568 // A cache clean opearation is looking for a dirty
569 // block. If a dirty block is encountered a WriteClean
570 // will update any copies to the path to the memory
571 // until the point of reference.
572 DPRINTF(CacheVerbose
, "%s: packet %s found block: %s\n",
573 __func__
, pkt
->print(), blk
->print());
574 PacketPtr wb_pkt
= writecleanBlk(blk
, pkt
->req
->getDest(), pkt
->id
);
575 writebacks
.push_back(wb_pkt
);
579 // handle writebacks resulting from the access here to ensure they
580 // logically proceed anything happening below
581 doWritebacksAtomic(writebacks
);
582 assert(writebacks
.empty());
585 lat
+= handleAtomicReqMiss(pkt
, blk
, writebacks
);
588 // Note that we don't invoke the prefetcher at all in atomic mode.
589 // It's not clear how to do it properly, particularly for
590 // prefetchers that aggressively generate prefetch candidates and
591 // rely on bandwidth contention to throttle them; these will tend
592 // to pollute the cache in atomic mode since there is no bandwidth
593 // contention. If we ever do want to enable prefetching in atomic
594 // mode, though, this is the place to do it... see timingAccess()
595 // for an example (though we'd want to issue the prefetch(es)
596 // immediately rather than calling requestMemSideBus() as we do
599 // do any writebacks resulting from the response handling
600 doWritebacksAtomic(writebacks
);
602 // if we used temp block, check to see if its valid and if so
603 // clear it out, but only do so after the call to recvAtomic is
604 // finished so that any downstream observers (such as a snoop
605 // filter), first see the fill, and only then see the eviction
606 if (blk
== tempBlock
&& tempBlock
->isValid()) {
607 // the atomic CPU calls recvAtomic for fetch and load/store
608 // sequentuially, and we may already have a tempBlock
609 // writeback from the fetch that we have not yet sent
610 if (tempBlockWriteback
) {
611 // if that is the case, write the prevoius one back, and
612 // do not schedule any new event
613 writebackTempBlockAtomic();
615 // the writeback/clean eviction happens after the call to
616 // recvAtomic has finished (but before any successive
617 // calls), so that the response handling from the fill is
618 // allowed to happen first
619 schedule(writebackTempBlockAtomicEvent
, curTick());
622 tempBlockWriteback
= evictBlock(blk
);
625 if (pkt
->needsResponse()) {
626 pkt
->makeAtomicResponse();
629 return lat
* clockPeriod();
633 BaseCache::functionalAccess(PacketPtr pkt
, bool from_cpu_side
)
635 Addr blk_addr
= pkt
->getBlockAddr(blkSize
);
636 bool is_secure
= pkt
->isSecure();
637 CacheBlk
*blk
= tags
->findBlock(pkt
->getAddr(), is_secure
);
638 MSHR
*mshr
= mshrQueue
.findMatch(blk_addr
, is_secure
);
640 pkt
->pushLabel(name());
642 CacheBlkPrintWrapper
cbpw(blk
);
644 // Note that just because an L2/L3 has valid data doesn't mean an
645 // L1 doesn't have a more up-to-date modified copy that still
646 // needs to be found. As a result we always update the request if
647 // we have it, but only declare it satisfied if we are the owner.
649 // see if we have data at all (owned or otherwise)
650 bool have_data
= blk
&& blk
->isValid()
651 && pkt
->checkFunctional(&cbpw
, blk_addr
, is_secure
, blkSize
,
654 // data we have is dirty if marked as such or if we have an
655 // in-service MSHR that is pending a modified line
657 have_data
&& (blk
->isDirty() ||
658 (mshr
&& mshr
->inService
&& mshr
->isPendingModified()));
660 bool done
= have_dirty
||
661 cpuSidePort
.checkFunctional(pkt
) ||
662 mshrQueue
.checkFunctional(pkt
, blk_addr
) ||
663 writeBuffer
.checkFunctional(pkt
, blk_addr
) ||
664 memSidePort
.checkFunctional(pkt
);
666 DPRINTF(CacheVerbose
, "%s: %s %s%s%s\n", __func__
, pkt
->print(),
667 (blk
&& blk
->isValid()) ? "valid " : "",
668 have_data
? "data " : "", done
? "done " : "");
670 // We're leaving the cache, so pop cache->name() label
676 // if it came as a request from the CPU side then make sure it
677 // continues towards the memory side
679 memSidePort
.sendFunctional(pkt
);
680 } else if (cpuSidePort
.isSnooping()) {
681 // if it came from the memory side, it must be a snoop request
682 // and we should only forward it if we are forwarding snoops
683 cpuSidePort
.sendFunctionalSnoop(pkt
);
690 BaseCache::cmpAndSwap(CacheBlk
*blk
, PacketPtr pkt
)
692 assert(pkt
->isRequest());
694 uint64_t overwrite_val
;
696 uint64_t condition_val64
;
697 uint32_t condition_val32
;
699 int offset
= pkt
->getOffset(blkSize
);
700 uint8_t *blk_data
= blk
->data
+ offset
;
702 assert(sizeof(uint64_t) >= pkt
->getSize());
704 overwrite_mem
= true;
705 // keep a copy of our possible write value, and copy what is at the
706 // memory address into the packet
707 pkt
->writeData((uint8_t *)&overwrite_val
);
708 pkt
->setData(blk_data
);
710 if (pkt
->req
->isCondSwap()) {
711 if (pkt
->getSize() == sizeof(uint64_t)) {
712 condition_val64
= pkt
->req
->getExtraData();
713 overwrite_mem
= !std::memcmp(&condition_val64
, blk_data
,
715 } else if (pkt
->getSize() == sizeof(uint32_t)) {
716 condition_val32
= (uint32_t)pkt
->req
->getExtraData();
717 overwrite_mem
= !std::memcmp(&condition_val32
, blk_data
,
720 panic("Invalid size for conditional read/write\n");
724 std::memcpy(blk_data
, &overwrite_val
, pkt
->getSize());
725 blk
->status
|= BlkDirty
;
730 BaseCache::getNextQueueEntry()
732 // Check both MSHR queue and write buffer for potential requests,
733 // note that null does not mean there is no request, it could
734 // simply be that it is not ready
735 MSHR
*miss_mshr
= mshrQueue
.getNext();
736 WriteQueueEntry
*wq_entry
= writeBuffer
.getNext();
738 // If we got a write buffer request ready, first priority is a
739 // full write buffer, otherwise we favour the miss requests
740 if (wq_entry
&& (writeBuffer
.isFull() || !miss_mshr
)) {
741 // need to search MSHR queue for conflicting earlier miss.
742 MSHR
*conflict_mshr
=
743 mshrQueue
.findPending(wq_entry
->blkAddr
,
746 if (conflict_mshr
&& conflict_mshr
->order
< wq_entry
->order
) {
747 // Service misses in order until conflict is cleared.
748 return conflict_mshr
;
750 // @todo Note that we ignore the ready time of the conflict here
753 // No conflicts; issue write
755 } else if (miss_mshr
) {
756 // need to check for conflicting earlier writeback
757 WriteQueueEntry
*conflict_mshr
=
758 writeBuffer
.findPending(miss_mshr
->blkAddr
,
759 miss_mshr
->isSecure
);
761 // not sure why we don't check order here... it was in the
762 // original code but commented out.
764 // The only way this happens is if we are
765 // doing a write and we didn't have permissions
766 // then subsequently saw a writeback (owned got evicted)
767 // We need to make sure to perform the writeback first
768 // To preserve the dirty data, then we can issue the write
770 // should we return wq_entry here instead? I.e. do we
771 // have to flush writes in order? I don't think so... not
772 // for Alpha anyway. Maybe for x86?
773 return conflict_mshr
;
775 // @todo Note that we ignore the ready time of the conflict here
778 // No conflicts; issue read
782 // fall through... no pending requests. Try a prefetch.
783 assert(!miss_mshr
&& !wq_entry
);
784 if (prefetcher
&& mshrQueue
.canPrefetch()) {
785 // If we have a miss queue slot, we can try a prefetch
786 PacketPtr pkt
= prefetcher
->getPacket();
788 Addr pf_addr
= pkt
->getBlockAddr(blkSize
);
789 if (!tags
->findBlock(pf_addr
, pkt
->isSecure()) &&
790 !mshrQueue
.findMatch(pf_addr
, pkt
->isSecure()) &&
791 !writeBuffer
.findMatch(pf_addr
, pkt
->isSecure())) {
792 // Update statistic on number of prefetches issued
793 // (hwpf_mshr_misses)
794 assert(pkt
->req
->masterId() < system
->maxMasters());
795 mshr_misses
[pkt
->cmdToIndex()][pkt
->req
->masterId()]++;
797 // allocate an MSHR and return it, note
798 // that we send the packet straight away, so do not
800 return allocateMissBuffer(pkt
, curTick(), false);
802 // free the request and packet
813 BaseCache::satisfyRequest(PacketPtr pkt
, CacheBlk
*blk
, bool, bool)
815 assert(pkt
->isRequest());
817 assert(blk
&& blk
->isValid());
818 // Occasionally this is not true... if we are a lower-level cache
819 // satisfying a string of Read and ReadEx requests from
820 // upper-level caches, a Read will mark the block as shared but we
821 // can satisfy a following ReadEx anyway since we can rely on the
822 // Read requester(s) to have buffered the ReadEx snoop and to
823 // invalidate their blocks after receiving them.
824 // assert(!pkt->needsWritable() || blk->isWritable());
825 assert(pkt
->getOffset(blkSize
) + pkt
->getSize() <= blkSize
);
827 // Check RMW operations first since both isRead() and
828 // isWrite() will be true for them
829 if (pkt
->cmd
== MemCmd::SwapReq
) {
830 cmpAndSwap(blk
, pkt
);
831 } else if (pkt
->isWrite()) {
832 // we have the block in a writable state and can go ahead,
833 // note that the line may be also be considered writable in
834 // downstream caches along the path to memory, but always
835 // Exclusive, and never Modified
836 assert(blk
->isWritable());
837 // Write or WriteLine at the first cache with block in writable state
838 if (blk
->checkWrite(pkt
)) {
839 pkt
->writeDataToBlock(blk
->data
, blkSize
);
841 // Always mark the line as dirty (and thus transition to the
842 // Modified state) even if we are a failed StoreCond so we
843 // supply data to any snoops that have appended themselves to
844 // this cache before knowing the store will fail.
845 blk
->status
|= BlkDirty
;
846 DPRINTF(CacheVerbose
, "%s for %s (write)\n", __func__
, pkt
->print());
847 } else if (pkt
->isRead()) {
849 blk
->trackLoadLocked(pkt
);
852 // all read responses have a data payload
853 assert(pkt
->hasRespData());
854 pkt
->setDataFromBlock(blk
->data
, blkSize
);
855 } else if (pkt
->isUpgrade()) {
857 assert(!pkt
->hasSharers());
859 if (blk
->isDirty()) {
860 // we were in the Owned state, and a cache above us that
861 // has the line in Shared state needs to be made aware
862 // that the data it already has is in fact dirty
863 pkt
->setCacheResponding();
864 blk
->status
&= ~BlkDirty
;
867 assert(pkt
->isInvalidate());
868 invalidateBlock(blk
);
869 DPRINTF(CacheVerbose
, "%s for %s (invalidation)\n", __func__
,
874 /////////////////////////////////////////////////////
876 // Access path: requests coming in from the CPU side
878 /////////////////////////////////////////////////////
881 BaseCache::access(PacketPtr pkt
, CacheBlk
*&blk
, Cycles
&lat
,
882 PacketList
&writebacks
)
885 assert(pkt
->isRequest());
887 chatty_assert(!(isReadOnly
&& pkt
->isWrite()),
888 "Should never see a write in a read-only cache %s\n",
891 // Here lat is the value passed as parameter to accessBlock() function
892 // that can modify its value.
893 blk
= tags
->accessBlock(pkt
->getAddr(), pkt
->isSecure(), lat
);
895 DPRINTF(Cache
, "%s for %s %s\n", __func__
, pkt
->print(),
896 blk
? "hit " + blk
->print() : "miss");
898 if (pkt
->req
->isCacheMaintenance()) {
899 // A cache maintenance operation is always forwarded to the
900 // memory below even if the block is found in dirty state.
902 // We defer any changes to the state of the block until we
903 // create and mark as in service the mshr for the downstream
908 if (pkt
->isEviction()) {
909 // We check for presence of block in above caches before issuing
910 // Writeback or CleanEvict to write buffer. Therefore the only
911 // possible cases can be of a CleanEvict packet coming from above
912 // encountering a Writeback generated in this cache peer cache and
913 // waiting in the write buffer. Cases of upper level peer caches
914 // generating CleanEvict and Writeback or simply CleanEvict and
915 // CleanEvict almost simultaneously will be caught by snoops sent out
917 WriteQueueEntry
*wb_entry
= writeBuffer
.findMatch(pkt
->getAddr(),
920 assert(wb_entry
->getNumTargets() == 1);
921 PacketPtr wbPkt
= wb_entry
->getTarget()->pkt
;
922 assert(wbPkt
->isWriteback());
924 if (pkt
->isCleanEviction()) {
925 // The CleanEvict and WritebackClean snoops into other
926 // peer caches of the same level while traversing the
927 // crossbar. If a copy of the block is found, the
928 // packet is deleted in the crossbar. Hence, none of
929 // the other upper level caches connected to this
930 // cache have the block, so we can clear the
931 // BLOCK_CACHED flag in the Writeback if set and
932 // discard the CleanEvict by returning true.
933 wbPkt
->clearBlockCached();
936 assert(pkt
->cmd
== MemCmd::WritebackDirty
);
937 // Dirty writeback from above trumps our clean
938 // writeback... discard here
939 // Note: markInService will remove entry from writeback buffer.
940 markInService(wb_entry
);
946 // Writeback handling is special case. We can write the block into
947 // the cache without having a writeable copy (or any copy at all).
948 if (pkt
->isWriteback()) {
949 assert(blkSize
== pkt
->getSize());
951 // we could get a clean writeback while we are having
952 // outstanding accesses to a block, do the simple thing for
953 // now and drop the clean writeback so that we do not upset
954 // any ordering/decisions about ownership already taken
955 if (pkt
->cmd
== MemCmd::WritebackClean
&&
956 mshrQueue
.findMatch(pkt
->getAddr(), pkt
->isSecure())) {
957 DPRINTF(Cache
, "Clean writeback %#llx to block with MSHR, "
958 "dropping\n", pkt
->getAddr());
963 // need to do a replacement
964 blk
= allocateBlock(pkt
->getAddr(), pkt
->isSecure(), writebacks
);
966 // no replaceable block available: give up, fwd to next level.
970 tags
->insertBlock(pkt
, blk
);
972 blk
->status
|= (BlkValid
| BlkReadable
);
974 // only mark the block dirty if we got a writeback command,
975 // and leave it as is for a clean writeback
976 if (pkt
->cmd
== MemCmd::WritebackDirty
) {
977 // TODO: the coherent cache can assert(!blk->isDirty());
978 blk
->status
|= BlkDirty
;
980 // if the packet does not have sharers, it is passing
981 // writable, and we got the writeback in Modified or Exclusive
982 // state, if not we are in the Owned or Shared state
983 if (!pkt
->hasSharers()) {
984 blk
->status
|= BlkWritable
;
986 // nothing else to do; writeback doesn't expect response
987 assert(!pkt
->needsResponse());
988 pkt
->writeDataToBlock(blk
->data
, blkSize
);
989 DPRINTF(Cache
, "%s new state is %s\n", __func__
, blk
->print());
991 // populate the time when the block will be ready to access.
992 blk
->whenReady
= clockEdge(fillLatency
) + pkt
->headerDelay
+
995 } else if (pkt
->cmd
== MemCmd::CleanEvict
) {
997 // Found the block in the tags, need to stop CleanEvict from
998 // propagating further down the hierarchy. Returning true will
999 // treat the CleanEvict like a satisfied write request and delete
1003 // We didn't find the block here, propagate the CleanEvict further
1004 // down the memory hierarchy. Returning false will treat the CleanEvict
1005 // like a Writeback which could not find a replaceable block so has to
1006 // go to next level.
1008 } else if (pkt
->cmd
== MemCmd::WriteClean
) {
1009 // WriteClean handling is a special case. We can allocate a
1010 // block directly if it doesn't exist and we can update the
1011 // block immediately. The WriteClean transfers the ownership
1012 // of the block as well.
1013 assert(blkSize
== pkt
->getSize());
1016 if (pkt
->writeThrough()) {
1017 // if this is a write through packet, we don't try to
1018 // allocate if the block is not present
1021 // a writeback that misses needs to allocate a new block
1022 blk
= allocateBlock(pkt
->getAddr(), pkt
->isSecure(),
1025 // no replaceable block available: give up, fwd to
1030 tags
->insertBlock(pkt
, blk
);
1032 blk
->status
|= (BlkValid
| BlkReadable
);
1036 // at this point either this is a writeback or a write-through
1037 // write clean operation and the block is already in this
1038 // cache, we need to update the data and the block flags
1040 // TODO: the coherent cache can assert(!blk->isDirty());
1041 if (!pkt
->writeThrough()) {
1042 blk
->status
|= BlkDirty
;
1044 // nothing else to do; writeback doesn't expect response
1045 assert(!pkt
->needsResponse());
1046 pkt
->writeDataToBlock(blk
->data
, blkSize
);
1047 DPRINTF(Cache
, "%s new state is %s\n", __func__
, blk
->print());
1050 // populate the time when the block will be ready to access.
1051 blk
->whenReady
= clockEdge(fillLatency
) + pkt
->headerDelay
+
1053 // if this a write-through packet it will be sent to cache
1055 return !pkt
->writeThrough();
1056 } else if (blk
&& (pkt
->needsWritable() ? blk
->isWritable() :
1057 blk
->isReadable())) {
1058 // OK to satisfy access
1060 satisfyRequest(pkt
, blk
);
1061 maintainClusivity(pkt
->fromCache(), blk
);
1066 // Can't satisfy access normally... either no block (blk == nullptr)
1067 // or have block but need writable
1071 if (!blk
&& pkt
->isLLSC() && pkt
->isWrite()) {
1072 // complete miss on store conditional... just give up now
1073 pkt
->req
->setExtraData(0);
1081 BaseCache::maintainClusivity(bool from_cache
, CacheBlk
*blk
)
1083 if (from_cache
&& blk
&& blk
->isValid() && !blk
->isDirty() &&
1084 clusivity
== Enums::mostly_excl
) {
1085 // if we have responded to a cache, and our block is still
1086 // valid, but not dirty, and this cache is mostly exclusive
1087 // with respect to the cache above, drop the block
1088 invalidateBlock(blk
);
1093 BaseCache::handleFill(PacketPtr pkt
, CacheBlk
*blk
, PacketList
&writebacks
,
1096 assert(pkt
->isResponse() || pkt
->cmd
== MemCmd::WriteLineReq
);
1097 Addr addr
= pkt
->getAddr();
1098 bool is_secure
= pkt
->isSecure();
1100 CacheBlk::State old_state
= blk
? blk
->status
: 0;
1103 // When handling a fill, we should have no writes to this line.
1104 assert(addr
== pkt
->getBlockAddr(blkSize
));
1105 assert(!writeBuffer
.findMatch(addr
, is_secure
));
1108 // better have read new data...
1109 assert(pkt
->hasData());
1111 // only read responses and write-line requests have data;
1112 // note that we don't write the data here for write-line - that
1113 // happens in the subsequent call to satisfyRequest
1114 assert(pkt
->isRead() || pkt
->cmd
== MemCmd::WriteLineReq
);
1116 // need to do a replacement if allocating, otherwise we stick
1117 // with the temporary storage
1118 blk
= allocate
? allocateBlock(addr
, is_secure
, writebacks
) : nullptr;
1121 // No replaceable block or a mostly exclusive
1122 // cache... just use temporary storage to complete the
1123 // current request and then get rid of it
1124 assert(!tempBlock
->isValid());
1126 tempBlock
->set
= tags
->extractSet(addr
);
1127 tempBlock
->tag
= tags
->extractTag(addr
);
1128 DPRINTF(Cache
, "using temp block for %#llx (%s)\n", addr
,
1129 is_secure
? "s" : "ns");
1131 tags
->insertBlock(pkt
, blk
);
1134 // we should never be overwriting a valid block
1135 assert(!blk
->isValid());
1137 // existing block... probably an upgrade
1138 assert(blk
->tag
== tags
->extractTag(addr
));
1139 // either we're getting new data or the block should already be valid
1140 assert(pkt
->hasData() || blk
->isValid());
1141 // don't clear block status... if block is already dirty we
1142 // don't want to lose that
1146 blk
->status
|= BlkSecure
;
1147 blk
->status
|= BlkValid
| BlkReadable
;
1149 // sanity check for whole-line writes, which should always be
1150 // marked as writable as part of the fill, and then later marked
1151 // dirty as part of satisfyRequest
1152 if (pkt
->cmd
== MemCmd::WriteLineReq
) {
1153 assert(!pkt
->hasSharers());
1156 // here we deal with setting the appropriate state of the line,
1157 // and we start by looking at the hasSharers flag, and ignore the
1158 // cacheResponding flag (normally signalling dirty data) if the
1159 // packet has sharers, thus the line is never allocated as Owned
1160 // (dirty but not writable), and always ends up being either
1161 // Shared, Exclusive or Modified, see Packet::setCacheResponding
1163 if (!pkt
->hasSharers()) {
1164 // we could get a writable line from memory (rather than a
1165 // cache) even in a read-only cache, note that we set this bit
1166 // even for a read-only cache, possibly revisit this decision
1167 blk
->status
|= BlkWritable
;
1169 // check if we got this via cache-to-cache transfer (i.e., from a
1170 // cache that had the block in Modified or Owned state)
1171 if (pkt
->cacheResponding()) {
1172 // we got the block in Modified state, and invalidated the
1174 blk
->status
|= BlkDirty
;
1176 chatty_assert(!isReadOnly
, "Should never see dirty snoop response "
1177 "in read-only cache %s\n", name());
1181 DPRINTF(Cache
, "Block addr %#llx (%s) moving from state %x to %s\n",
1182 addr
, is_secure
? "s" : "ns", old_state
, blk
->print());
1184 // if we got new data, copy it in (checking for a read response
1185 // and a response that has data is the same in the end)
1186 if (pkt
->isRead()) {
1188 assert(pkt
->hasData());
1189 assert(pkt
->getSize() == blkSize
);
1191 pkt
->writeDataToBlock(blk
->data
, blkSize
);
1193 // We pay for fillLatency here.
1194 blk
->whenReady
= clockEdge() + fillLatency
* clockPeriod() +
1201 BaseCache::allocateBlock(Addr addr
, bool is_secure
, PacketList
&writebacks
)
1203 // Find replacement victim
1204 CacheBlk
*blk
= tags
->findVictim(addr
);
1206 // It is valid to return nullptr if there is no victim
1210 if (blk
->isValid()) {
1211 Addr repl_addr
= tags
->regenerateBlkAddr(blk
);
1212 MSHR
*repl_mshr
= mshrQueue
.findMatch(repl_addr
, blk
->isSecure());
1214 // must be an outstanding upgrade or clean request
1215 // on a block we're about to replace...
1216 assert((!blk
->isWritable() && repl_mshr
->needsWritable()) ||
1217 repl_mshr
->isCleaning());
1218 // too hard to replace block with transient state
1219 // allocation failed, block not inserted
1222 DPRINTF(Cache
, "replacement: replacing %#llx (%s) with %#llx "
1223 "(%s): %s\n", repl_addr
, blk
->isSecure() ? "s" : "ns",
1224 addr
, is_secure
? "s" : "ns",
1225 blk
->isDirty() ? "writeback" : "clean");
1227 if (blk
->wasPrefetched()) {
1230 evictBlock(blk
, writebacks
);
1239 BaseCache::invalidateBlock(CacheBlk
*blk
)
1241 if (blk
!= tempBlock
)
1242 tags
->invalidate(blk
);
1247 BaseCache::writebackBlk(CacheBlk
*blk
)
1249 chatty_assert(!isReadOnly
|| writebackClean
,
1250 "Writeback from read-only cache");
1251 assert(blk
&& blk
->isValid() && (blk
->isDirty() || writebackClean
));
1253 writebacks
[Request::wbMasterId
]++;
1255 Request
*req
= new Request(tags
->regenerateBlkAddr(blk
), blkSize
, 0,
1256 Request::wbMasterId
);
1257 if (blk
->isSecure())
1258 req
->setFlags(Request::SECURE
);
1260 req
->taskId(blk
->task_id
);
1263 new Packet(req
, blk
->isDirty() ?
1264 MemCmd::WritebackDirty
: MemCmd::WritebackClean
);
1266 DPRINTF(Cache
, "Create Writeback %s writable: %d, dirty: %d\n",
1267 pkt
->print(), blk
->isWritable(), blk
->isDirty());
1269 if (blk
->isWritable()) {
1270 // not asserting shared means we pass the block in modified
1271 // state, mark our own block non-writeable
1272 blk
->status
&= ~BlkWritable
;
1274 // we are in the Owned state, tell the receiver
1275 pkt
->setHasSharers();
1278 // make sure the block is not marked dirty
1279 blk
->status
&= ~BlkDirty
;
1282 pkt
->setDataFromBlock(blk
->data
, blkSize
);
1288 BaseCache::writecleanBlk(CacheBlk
*blk
, Request::Flags dest
, PacketId id
)
1290 Request
*req
= new Request(tags
->regenerateBlkAddr(blk
), blkSize
, 0,
1291 Request::wbMasterId
);
1292 if (blk
->isSecure()) {
1293 req
->setFlags(Request::SECURE
);
1295 req
->taskId(blk
->task_id
);
1297 PacketPtr pkt
= new Packet(req
, MemCmd::WriteClean
, blkSize
, id
);
1300 req
->setFlags(dest
);
1301 pkt
->setWriteThrough();
1304 DPRINTF(Cache
, "Create %s writable: %d, dirty: %d\n", pkt
->print(),
1305 blk
->isWritable(), blk
->isDirty());
1307 if (blk
->isWritable()) {
1308 // not asserting shared means we pass the block in modified
1309 // state, mark our own block non-writeable
1310 blk
->status
&= ~BlkWritable
;
1312 // we are in the Owned state, tell the receiver
1313 pkt
->setHasSharers();
1316 // make sure the block is not marked dirty
1317 blk
->status
&= ~BlkDirty
;
1320 pkt
->setDataFromBlock(blk
->data
, blkSize
);
1327 BaseCache::memWriteback()
1329 tags
->forEachBlk([this](CacheBlk
&blk
) { writebackVisitor(blk
); });
1333 BaseCache::memInvalidate()
1335 tags
->forEachBlk([this](CacheBlk
&blk
) { invalidateVisitor(blk
); });
1339 BaseCache::isDirty() const
1341 return tags
->anyBlk([](CacheBlk
&blk
) { return blk
.isDirty(); });
1345 BaseCache::writebackVisitor(CacheBlk
&blk
)
1347 if (blk
.isDirty()) {
1348 assert(blk
.isValid());
1350 Request
request(tags
->regenerateBlkAddr(&blk
),
1351 blkSize
, 0, Request::funcMasterId
);
1352 request
.taskId(blk
.task_id
);
1353 if (blk
.isSecure()) {
1354 request
.setFlags(Request::SECURE
);
1357 Packet
packet(&request
, MemCmd::WriteReq
);
1358 packet
.dataStatic(blk
.data
);
1360 memSidePort
.sendFunctional(&packet
);
1362 blk
.status
&= ~BlkDirty
;
1367 BaseCache::invalidateVisitor(CacheBlk
&blk
)
1370 warn_once("Invalidating dirty cache lines. " \
1371 "Expect things to break.\n");
1373 if (blk
.isValid()) {
1374 assert(!blk
.isDirty());
1375 invalidateBlock(&blk
);
1380 BaseCache::nextQueueReadyTime() const
1382 Tick nextReady
= std::min(mshrQueue
.nextReadyTime(),
1383 writeBuffer
.nextReadyTime());
1385 // Don't signal prefetch ready time if no MSHRs available
1386 // Will signal once enoguh MSHRs are deallocated
1387 if (prefetcher
&& mshrQueue
.canPrefetch()) {
1388 nextReady
= std::min(nextReady
,
1389 prefetcher
->nextPrefetchReadyTime());
1397 BaseCache::sendMSHRQueuePacket(MSHR
* mshr
)
1401 // use request from 1st target
1402 PacketPtr tgt_pkt
= mshr
->getTarget()->pkt
;
1404 DPRINTF(Cache
, "%s: MSHR %s\n", __func__
, tgt_pkt
->print());
1406 CacheBlk
*blk
= tags
->findBlock(mshr
->blkAddr
, mshr
->isSecure
);
1408 // either a prefetch that is not present upstream, or a normal
1409 // MSHR request, proceed to get the packet to send downstream
1410 PacketPtr pkt
= createMissPacket(tgt_pkt
, blk
, mshr
->needsWritable());
1412 mshr
->isForward
= (pkt
== nullptr);
1414 if (mshr
->isForward
) {
1415 // not a cache block request, but a response is expected
1416 // make copy of current packet to forward, keep current
1417 // copy for response handling
1418 pkt
= new Packet(tgt_pkt
, false, true);
1419 assert(!pkt
->isWrite());
1422 // play it safe and append (rather than set) the sender state,
1423 // as forwarded packets may already have existing state
1424 pkt
->pushSenderState(mshr
);
1426 if (pkt
->isClean() && blk
&& blk
->isDirty()) {
1427 // A cache clean opearation is looking for a dirty block. Mark
1428 // the packet so that the destination xbar can determine that
1429 // there will be a follow-up write packet as well.
1430 pkt
->setSatisfied();
1433 if (!memSidePort
.sendTimingReq(pkt
)) {
1434 // we are awaiting a retry, but we
1435 // delete the packet and will be creating a new packet
1436 // when we get the opportunity
1439 // note that we have now masked any requestBus and
1440 // schedSendEvent (we will wait for a retry before
1441 // doing anything), and this is so even if we do not
1442 // care about this packet and might override it before
1446 // As part of the call to sendTimingReq the packet is
1447 // forwarded to all neighbouring caches (and any caches
1448 // above them) as a snoop. Thus at this point we know if
1449 // any of the neighbouring caches are responding, and if
1450 // so, we know it is dirty, and we can determine if it is
1451 // being passed as Modified, making our MSHR the ordering
1453 bool pending_modified_resp
= !pkt
->hasSharers() &&
1454 pkt
->cacheResponding();
1455 markInService(mshr
, pending_modified_resp
);
1457 if (pkt
->isClean() && blk
&& blk
->isDirty()) {
1458 // A cache clean opearation is looking for a dirty
1459 // block. If a dirty block is encountered a WriteClean
1460 // will update any copies to the path to the memory
1461 // until the point of reference.
1462 DPRINTF(CacheVerbose
, "%s: packet %s found block: %s\n",
1463 __func__
, pkt
->print(), blk
->print());
1464 PacketPtr wb_pkt
= writecleanBlk(blk
, pkt
->req
->getDest(),
1466 PacketList writebacks
;
1467 writebacks
.push_back(wb_pkt
);
1468 doWritebacks(writebacks
, 0);
1476 BaseCache::sendWriteQueuePacket(WriteQueueEntry
* wq_entry
)
1480 // always a single target for write queue entries
1481 PacketPtr tgt_pkt
= wq_entry
->getTarget()->pkt
;
1483 DPRINTF(Cache
, "%s: write %s\n", __func__
, tgt_pkt
->print());
1485 // forward as is, both for evictions and uncacheable writes
1486 if (!memSidePort
.sendTimingReq(tgt_pkt
)) {
1487 // note that we have now masked any requestBus and
1488 // schedSendEvent (we will wait for a retry before
1489 // doing anything), and this is so even if we do not
1490 // care about this packet and might override it before
1494 markInService(wq_entry
);
1500 BaseCache::serialize(CheckpointOut
&cp
) const
1502 bool dirty(isDirty());
1505 warn("*** The cache still contains dirty data. ***\n");
1506 warn(" Make sure to drain the system using the correct flags.\n");
1507 warn(" This checkpoint will not restore correctly " \
1508 "and dirty data in the cache will be lost!\n");
1511 // Since we don't checkpoint the data in the cache, any dirty data
1512 // will be lost when restoring from a checkpoint of a system that
1513 // wasn't drained properly. Flag the checkpoint as invalid if the
1514 // cache contains dirty data.
1515 bool bad_checkpoint(dirty
);
1516 SERIALIZE_SCALAR(bad_checkpoint
);
1520 BaseCache::unserialize(CheckpointIn
&cp
)
1522 bool bad_checkpoint
;
1523 UNSERIALIZE_SCALAR(bad_checkpoint
);
1524 if (bad_checkpoint
) {
1525 fatal("Restoring from checkpoints with dirty caches is not "
1526 "supported in the classic memory system. Please remove any "
1527 "caches or drain them properly before taking checkpoints.\n");
1532 BaseCache::regStats()
1534 MemObject::regStats();
1536 using namespace Stats
;
1539 for (int access_idx
= 0; access_idx
< MemCmd::NUM_MEM_CMDS
; ++access_idx
) {
1540 MemCmd
cmd(access_idx
);
1541 const string
&cstr
= cmd
.toString();
1544 .init(system
->maxMasters())
1545 .name(name() + "." + cstr
+ "_hits")
1546 .desc("number of " + cstr
+ " hits")
1547 .flags(total
| nozero
| nonan
)
1549 for (int i
= 0; i
< system
->maxMasters(); i
++) {
1550 hits
[access_idx
].subname(i
, system
->getMasterName(i
));
1554 // These macros make it easier to sum the right subset of commands and
1555 // to change the subset of commands that are considered "demand" vs
1557 #define SUM_DEMAND(s) \
1558 (s[MemCmd::ReadReq] + s[MemCmd::WriteReq] + s[MemCmd::WriteLineReq] + \
1559 s[MemCmd::ReadExReq] + s[MemCmd::ReadCleanReq] + s[MemCmd::ReadSharedReq])
1561 // should writebacks be included here? prior code was inconsistent...
1562 #define SUM_NON_DEMAND(s) \
1563 (s[MemCmd::SoftPFReq] + s[MemCmd::HardPFReq])
1566 .name(name() + ".demand_hits")
1567 .desc("number of demand (read+write) hits")
1568 .flags(total
| nozero
| nonan
)
1570 demandHits
= SUM_DEMAND(hits
);
1571 for (int i
= 0; i
< system
->maxMasters(); i
++) {
1572 demandHits
.subname(i
, system
->getMasterName(i
));
1576 .name(name() + ".overall_hits")
1577 .desc("number of overall hits")
1578 .flags(total
| nozero
| nonan
)
1580 overallHits
= demandHits
+ SUM_NON_DEMAND(hits
);
1581 for (int i
= 0; i
< system
->maxMasters(); i
++) {
1582 overallHits
.subname(i
, system
->getMasterName(i
));
1586 for (int access_idx
= 0; access_idx
< MemCmd::NUM_MEM_CMDS
; ++access_idx
) {
1587 MemCmd
cmd(access_idx
);
1588 const string
&cstr
= cmd
.toString();
1591 .init(system
->maxMasters())
1592 .name(name() + "." + cstr
+ "_misses")
1593 .desc("number of " + cstr
+ " misses")
1594 .flags(total
| nozero
| nonan
)
1596 for (int i
= 0; i
< system
->maxMasters(); i
++) {
1597 misses
[access_idx
].subname(i
, system
->getMasterName(i
));
1602 .name(name() + ".demand_misses")
1603 .desc("number of demand (read+write) misses")
1604 .flags(total
| nozero
| nonan
)
1606 demandMisses
= SUM_DEMAND(misses
);
1607 for (int i
= 0; i
< system
->maxMasters(); i
++) {
1608 demandMisses
.subname(i
, system
->getMasterName(i
));
1612 .name(name() + ".overall_misses")
1613 .desc("number of overall misses")
1614 .flags(total
| nozero
| nonan
)
1616 overallMisses
= demandMisses
+ SUM_NON_DEMAND(misses
);
1617 for (int i
= 0; i
< system
->maxMasters(); i
++) {
1618 overallMisses
.subname(i
, system
->getMasterName(i
));
1621 // Miss latency statistics
1622 for (int access_idx
= 0; access_idx
< MemCmd::NUM_MEM_CMDS
; ++access_idx
) {
1623 MemCmd
cmd(access_idx
);
1624 const string
&cstr
= cmd
.toString();
1626 missLatency
[access_idx
]
1627 .init(system
->maxMasters())
1628 .name(name() + "." + cstr
+ "_miss_latency")
1629 .desc("number of " + cstr
+ " miss cycles")
1630 .flags(total
| nozero
| nonan
)
1632 for (int i
= 0; i
< system
->maxMasters(); i
++) {
1633 missLatency
[access_idx
].subname(i
, system
->getMasterName(i
));
1638 .name(name() + ".demand_miss_latency")
1639 .desc("number of demand (read+write) miss cycles")
1640 .flags(total
| nozero
| nonan
)
1642 demandMissLatency
= SUM_DEMAND(missLatency
);
1643 for (int i
= 0; i
< system
->maxMasters(); i
++) {
1644 demandMissLatency
.subname(i
, system
->getMasterName(i
));
1648 .name(name() + ".overall_miss_latency")
1649 .desc("number of overall miss cycles")
1650 .flags(total
| nozero
| nonan
)
1652 overallMissLatency
= demandMissLatency
+ SUM_NON_DEMAND(missLatency
);
1653 for (int i
= 0; i
< system
->maxMasters(); i
++) {
1654 overallMissLatency
.subname(i
, system
->getMasterName(i
));
1658 for (int access_idx
= 0; access_idx
< MemCmd::NUM_MEM_CMDS
; ++access_idx
) {
1659 MemCmd
cmd(access_idx
);
1660 const string
&cstr
= cmd
.toString();
1662 accesses
[access_idx
]
1663 .name(name() + "." + cstr
+ "_accesses")
1664 .desc("number of " + cstr
+ " accesses(hits+misses)")
1665 .flags(total
| nozero
| nonan
)
1667 accesses
[access_idx
] = hits
[access_idx
] + misses
[access_idx
];
1669 for (int i
= 0; i
< system
->maxMasters(); i
++) {
1670 accesses
[access_idx
].subname(i
, system
->getMasterName(i
));
1675 .name(name() + ".demand_accesses")
1676 .desc("number of demand (read+write) accesses")
1677 .flags(total
| nozero
| nonan
)
1679 demandAccesses
= demandHits
+ demandMisses
;
1680 for (int i
= 0; i
< system
->maxMasters(); i
++) {
1681 demandAccesses
.subname(i
, system
->getMasterName(i
));
1685 .name(name() + ".overall_accesses")
1686 .desc("number of overall (read+write) accesses")
1687 .flags(total
| nozero
| nonan
)
1689 overallAccesses
= overallHits
+ overallMisses
;
1690 for (int i
= 0; i
< system
->maxMasters(); i
++) {
1691 overallAccesses
.subname(i
, system
->getMasterName(i
));
1694 // miss rate formulas
1695 for (int access_idx
= 0; access_idx
< MemCmd::NUM_MEM_CMDS
; ++access_idx
) {
1696 MemCmd
cmd(access_idx
);
1697 const string
&cstr
= cmd
.toString();
1699 missRate
[access_idx
]
1700 .name(name() + "." + cstr
+ "_miss_rate")
1701 .desc("miss rate for " + cstr
+ " accesses")
1702 .flags(total
| nozero
| nonan
)
1704 missRate
[access_idx
] = misses
[access_idx
] / accesses
[access_idx
];
1706 for (int i
= 0; i
< system
->maxMasters(); i
++) {
1707 missRate
[access_idx
].subname(i
, system
->getMasterName(i
));
1712 .name(name() + ".demand_miss_rate")
1713 .desc("miss rate for demand accesses")
1714 .flags(total
| nozero
| nonan
)
1716 demandMissRate
= demandMisses
/ demandAccesses
;
1717 for (int i
= 0; i
< system
->maxMasters(); i
++) {
1718 demandMissRate
.subname(i
, system
->getMasterName(i
));
1722 .name(name() + ".overall_miss_rate")
1723 .desc("miss rate for overall accesses")
1724 .flags(total
| nozero
| nonan
)
1726 overallMissRate
= overallMisses
/ overallAccesses
;
1727 for (int i
= 0; i
< system
->maxMasters(); i
++) {
1728 overallMissRate
.subname(i
, system
->getMasterName(i
));
1731 // miss latency formulas
1732 for (int access_idx
= 0; access_idx
< MemCmd::NUM_MEM_CMDS
; ++access_idx
) {
1733 MemCmd
cmd(access_idx
);
1734 const string
&cstr
= cmd
.toString();
1736 avgMissLatency
[access_idx
]
1737 .name(name() + "." + cstr
+ "_avg_miss_latency")
1738 .desc("average " + cstr
+ " miss latency")
1739 .flags(total
| nozero
| nonan
)
1741 avgMissLatency
[access_idx
] =
1742 missLatency
[access_idx
] / misses
[access_idx
];
1744 for (int i
= 0; i
< system
->maxMasters(); i
++) {
1745 avgMissLatency
[access_idx
].subname(i
, system
->getMasterName(i
));
1749 demandAvgMissLatency
1750 .name(name() + ".demand_avg_miss_latency")
1751 .desc("average overall miss latency")
1752 .flags(total
| nozero
| nonan
)
1754 demandAvgMissLatency
= demandMissLatency
/ demandMisses
;
1755 for (int i
= 0; i
< system
->maxMasters(); i
++) {
1756 demandAvgMissLatency
.subname(i
, system
->getMasterName(i
));
1759 overallAvgMissLatency
1760 .name(name() + ".overall_avg_miss_latency")
1761 .desc("average overall miss latency")
1762 .flags(total
| nozero
| nonan
)
1764 overallAvgMissLatency
= overallMissLatency
/ overallMisses
;
1765 for (int i
= 0; i
< system
->maxMasters(); i
++) {
1766 overallAvgMissLatency
.subname(i
, system
->getMasterName(i
));
1769 blocked_cycles
.init(NUM_BLOCKED_CAUSES
);
1771 .name(name() + ".blocked_cycles")
1772 .desc("number of cycles access was blocked")
1773 .subname(Blocked_NoMSHRs
, "no_mshrs")
1774 .subname(Blocked_NoTargets
, "no_targets")
1778 blocked_causes
.init(NUM_BLOCKED_CAUSES
);
1780 .name(name() + ".blocked")
1781 .desc("number of cycles access was blocked")
1782 .subname(Blocked_NoMSHRs
, "no_mshrs")
1783 .subname(Blocked_NoTargets
, "no_targets")
1787 .name(name() + ".avg_blocked_cycles")
1788 .desc("average number of cycles each access was blocked")
1789 .subname(Blocked_NoMSHRs
, "no_mshrs")
1790 .subname(Blocked_NoTargets
, "no_targets")
1793 avg_blocked
= blocked_cycles
/ blocked_causes
;
1796 .name(name() + ".unused_prefetches")
1797 .desc("number of HardPF blocks evicted w/o reference")
1802 .init(system
->maxMasters())
1803 .name(name() + ".writebacks")
1804 .desc("number of writebacks")
1805 .flags(total
| nozero
| nonan
)
1807 for (int i
= 0; i
< system
->maxMasters(); i
++) {
1808 writebacks
.subname(i
, system
->getMasterName(i
));
1812 // MSHR hit statistics
1813 for (int access_idx
= 0; access_idx
< MemCmd::NUM_MEM_CMDS
; ++access_idx
) {
1814 MemCmd
cmd(access_idx
);
1815 const string
&cstr
= cmd
.toString();
1817 mshr_hits
[access_idx
]
1818 .init(system
->maxMasters())
1819 .name(name() + "." + cstr
+ "_mshr_hits")
1820 .desc("number of " + cstr
+ " MSHR hits")
1821 .flags(total
| nozero
| nonan
)
1823 for (int i
= 0; i
< system
->maxMasters(); i
++) {
1824 mshr_hits
[access_idx
].subname(i
, system
->getMasterName(i
));
1829 .name(name() + ".demand_mshr_hits")
1830 .desc("number of demand (read+write) MSHR hits")
1831 .flags(total
| nozero
| nonan
)
1833 demandMshrHits
= SUM_DEMAND(mshr_hits
);
1834 for (int i
= 0; i
< system
->maxMasters(); i
++) {
1835 demandMshrHits
.subname(i
, system
->getMasterName(i
));
1839 .name(name() + ".overall_mshr_hits")
1840 .desc("number of overall MSHR hits")
1841 .flags(total
| nozero
| nonan
)
1843 overallMshrHits
= demandMshrHits
+ SUM_NON_DEMAND(mshr_hits
);
1844 for (int i
= 0; i
< system
->maxMasters(); i
++) {
1845 overallMshrHits
.subname(i
, system
->getMasterName(i
));
1848 // MSHR miss statistics
1849 for (int access_idx
= 0; access_idx
< MemCmd::NUM_MEM_CMDS
; ++access_idx
) {
1850 MemCmd
cmd(access_idx
);
1851 const string
&cstr
= cmd
.toString();
1853 mshr_misses
[access_idx
]
1854 .init(system
->maxMasters())
1855 .name(name() + "." + cstr
+ "_mshr_misses")
1856 .desc("number of " + cstr
+ " MSHR misses")
1857 .flags(total
| nozero
| nonan
)
1859 for (int i
= 0; i
< system
->maxMasters(); i
++) {
1860 mshr_misses
[access_idx
].subname(i
, system
->getMasterName(i
));
1865 .name(name() + ".demand_mshr_misses")
1866 .desc("number of demand (read+write) MSHR misses")
1867 .flags(total
| nozero
| nonan
)
1869 demandMshrMisses
= SUM_DEMAND(mshr_misses
);
1870 for (int i
= 0; i
< system
->maxMasters(); i
++) {
1871 demandMshrMisses
.subname(i
, system
->getMasterName(i
));
1875 .name(name() + ".overall_mshr_misses")
1876 .desc("number of overall MSHR misses")
1877 .flags(total
| nozero
| nonan
)
1879 overallMshrMisses
= demandMshrMisses
+ SUM_NON_DEMAND(mshr_misses
);
1880 for (int i
= 0; i
< system
->maxMasters(); i
++) {
1881 overallMshrMisses
.subname(i
, system
->getMasterName(i
));
1884 // MSHR miss latency statistics
1885 for (int access_idx
= 0; access_idx
< MemCmd::NUM_MEM_CMDS
; ++access_idx
) {
1886 MemCmd
cmd(access_idx
);
1887 const string
&cstr
= cmd
.toString();
1889 mshr_miss_latency
[access_idx
]
1890 .init(system
->maxMasters())
1891 .name(name() + "." + cstr
+ "_mshr_miss_latency")
1892 .desc("number of " + cstr
+ " MSHR miss cycles")
1893 .flags(total
| nozero
| nonan
)
1895 for (int i
= 0; i
< system
->maxMasters(); i
++) {
1896 mshr_miss_latency
[access_idx
].subname(i
, system
->getMasterName(i
));
1900 demandMshrMissLatency
1901 .name(name() + ".demand_mshr_miss_latency")
1902 .desc("number of demand (read+write) MSHR miss cycles")
1903 .flags(total
| nozero
| nonan
)
1905 demandMshrMissLatency
= SUM_DEMAND(mshr_miss_latency
);
1906 for (int i
= 0; i
< system
->maxMasters(); i
++) {
1907 demandMshrMissLatency
.subname(i
, system
->getMasterName(i
));
1910 overallMshrMissLatency
1911 .name(name() + ".overall_mshr_miss_latency")
1912 .desc("number of overall MSHR miss cycles")
1913 .flags(total
| nozero
| nonan
)
1915 overallMshrMissLatency
=
1916 demandMshrMissLatency
+ SUM_NON_DEMAND(mshr_miss_latency
);
1917 for (int i
= 0; i
< system
->maxMasters(); i
++) {
1918 overallMshrMissLatency
.subname(i
, system
->getMasterName(i
));
1921 // MSHR uncacheable statistics
1922 for (int access_idx
= 0; access_idx
< MemCmd::NUM_MEM_CMDS
; ++access_idx
) {
1923 MemCmd
cmd(access_idx
);
1924 const string
&cstr
= cmd
.toString();
1926 mshr_uncacheable
[access_idx
]
1927 .init(system
->maxMasters())
1928 .name(name() + "." + cstr
+ "_mshr_uncacheable")
1929 .desc("number of " + cstr
+ " MSHR uncacheable")
1930 .flags(total
| nozero
| nonan
)
1932 for (int i
= 0; i
< system
->maxMasters(); i
++) {
1933 mshr_uncacheable
[access_idx
].subname(i
, system
->getMasterName(i
));
1937 overallMshrUncacheable
1938 .name(name() + ".overall_mshr_uncacheable_misses")
1939 .desc("number of overall MSHR uncacheable misses")
1940 .flags(total
| nozero
| nonan
)
1942 overallMshrUncacheable
=
1943 SUM_DEMAND(mshr_uncacheable
) + SUM_NON_DEMAND(mshr_uncacheable
);
1944 for (int i
= 0; i
< system
->maxMasters(); i
++) {
1945 overallMshrUncacheable
.subname(i
, system
->getMasterName(i
));
1948 // MSHR miss latency statistics
1949 for (int access_idx
= 0; access_idx
< MemCmd::NUM_MEM_CMDS
; ++access_idx
) {
1950 MemCmd
cmd(access_idx
);
1951 const string
&cstr
= cmd
.toString();
1953 mshr_uncacheable_lat
[access_idx
]
1954 .init(system
->maxMasters())
1955 .name(name() + "." + cstr
+ "_mshr_uncacheable_latency")
1956 .desc("number of " + cstr
+ " MSHR uncacheable cycles")
1957 .flags(total
| nozero
| nonan
)
1959 for (int i
= 0; i
< system
->maxMasters(); i
++) {
1960 mshr_uncacheable_lat
[access_idx
].subname(
1961 i
, system
->getMasterName(i
));
1965 overallMshrUncacheableLatency
1966 .name(name() + ".overall_mshr_uncacheable_latency")
1967 .desc("number of overall MSHR uncacheable cycles")
1968 .flags(total
| nozero
| nonan
)
1970 overallMshrUncacheableLatency
=
1971 SUM_DEMAND(mshr_uncacheable_lat
) +
1972 SUM_NON_DEMAND(mshr_uncacheable_lat
);
1973 for (int i
= 0; i
< system
->maxMasters(); i
++) {
1974 overallMshrUncacheableLatency
.subname(i
, system
->getMasterName(i
));
1978 // MSHR access formulas
1979 for (int access_idx
= 0; access_idx
< MemCmd::NUM_MEM_CMDS
; ++access_idx
) {
1980 MemCmd
cmd(access_idx
);
1981 const string
&cstr
= cmd
.toString();
1983 mshrAccesses
[access_idx
]
1984 .name(name() + "." + cstr
+ "_mshr_accesses")
1985 .desc("number of " + cstr
+ " mshr accesses(hits+misses)")
1986 .flags(total
| nozero
| nonan
)
1988 mshrAccesses
[access_idx
] =
1989 mshr_hits
[access_idx
] + mshr_misses
[access_idx
]
1990 + mshr_uncacheable
[access_idx
];
1994 .name(name() + ".demand_mshr_accesses")
1995 .desc("number of demand (read+write) mshr accesses")
1996 .flags(total
| nozero
| nonan
)
1998 demandMshrAccesses
= demandMshrHits
+ demandMshrMisses
;
2001 .name(name() + ".overall_mshr_accesses")
2002 .desc("number of overall (read+write) mshr accesses")
2003 .flags(total
| nozero
| nonan
)
2005 overallMshrAccesses
= overallMshrHits
+ overallMshrMisses
2006 + overallMshrUncacheable
;
2009 // MSHR miss rate formulas
2010 for (int access_idx
= 0; access_idx
< MemCmd::NUM_MEM_CMDS
; ++access_idx
) {
2011 MemCmd
cmd(access_idx
);
2012 const string
&cstr
= cmd
.toString();
2014 mshrMissRate
[access_idx
]
2015 .name(name() + "." + cstr
+ "_mshr_miss_rate")
2016 .desc("mshr miss rate for " + cstr
+ " accesses")
2017 .flags(total
| nozero
| nonan
)
2019 mshrMissRate
[access_idx
] =
2020 mshr_misses
[access_idx
] / accesses
[access_idx
];
2022 for (int i
= 0; i
< system
->maxMasters(); i
++) {
2023 mshrMissRate
[access_idx
].subname(i
, system
->getMasterName(i
));
2028 .name(name() + ".demand_mshr_miss_rate")
2029 .desc("mshr miss rate for demand accesses")
2030 .flags(total
| nozero
| nonan
)
2032 demandMshrMissRate
= demandMshrMisses
/ demandAccesses
;
2033 for (int i
= 0; i
< system
->maxMasters(); i
++) {
2034 demandMshrMissRate
.subname(i
, system
->getMasterName(i
));
2038 .name(name() + ".overall_mshr_miss_rate")
2039 .desc("mshr miss rate for overall accesses")
2040 .flags(total
| nozero
| nonan
)
2042 overallMshrMissRate
= overallMshrMisses
/ overallAccesses
;
2043 for (int i
= 0; i
< system
->maxMasters(); i
++) {
2044 overallMshrMissRate
.subname(i
, system
->getMasterName(i
));
2047 // mshrMiss latency formulas
2048 for (int access_idx
= 0; access_idx
< MemCmd::NUM_MEM_CMDS
; ++access_idx
) {
2049 MemCmd
cmd(access_idx
);
2050 const string
&cstr
= cmd
.toString();
2052 avgMshrMissLatency
[access_idx
]
2053 .name(name() + "." + cstr
+ "_avg_mshr_miss_latency")
2054 .desc("average " + cstr
+ " mshr miss latency")
2055 .flags(total
| nozero
| nonan
)
2057 avgMshrMissLatency
[access_idx
] =
2058 mshr_miss_latency
[access_idx
] / mshr_misses
[access_idx
];
2060 for (int i
= 0; i
< system
->maxMasters(); i
++) {
2061 avgMshrMissLatency
[access_idx
].subname(
2062 i
, system
->getMasterName(i
));
2066 demandAvgMshrMissLatency
2067 .name(name() + ".demand_avg_mshr_miss_latency")
2068 .desc("average overall mshr miss latency")
2069 .flags(total
| nozero
| nonan
)
2071 demandAvgMshrMissLatency
= demandMshrMissLatency
/ demandMshrMisses
;
2072 for (int i
= 0; i
< system
->maxMasters(); i
++) {
2073 demandAvgMshrMissLatency
.subname(i
, system
->getMasterName(i
));
2076 overallAvgMshrMissLatency
2077 .name(name() + ".overall_avg_mshr_miss_latency")
2078 .desc("average overall mshr miss latency")
2079 .flags(total
| nozero
| nonan
)
2081 overallAvgMshrMissLatency
= overallMshrMissLatency
/ overallMshrMisses
;
2082 for (int i
= 0; i
< system
->maxMasters(); i
++) {
2083 overallAvgMshrMissLatency
.subname(i
, system
->getMasterName(i
));
2086 // mshrUncacheable latency formulas
2087 for (int access_idx
= 0; access_idx
< MemCmd::NUM_MEM_CMDS
; ++access_idx
) {
2088 MemCmd
cmd(access_idx
);
2089 const string
&cstr
= cmd
.toString();
2091 avgMshrUncacheableLatency
[access_idx
]
2092 .name(name() + "." + cstr
+ "_avg_mshr_uncacheable_latency")
2093 .desc("average " + cstr
+ " mshr uncacheable latency")
2094 .flags(total
| nozero
| nonan
)
2096 avgMshrUncacheableLatency
[access_idx
] =
2097 mshr_uncacheable_lat
[access_idx
] / mshr_uncacheable
[access_idx
];
2099 for (int i
= 0; i
< system
->maxMasters(); i
++) {
2100 avgMshrUncacheableLatency
[access_idx
].subname(
2101 i
, system
->getMasterName(i
));
2105 overallAvgMshrUncacheableLatency
2106 .name(name() + ".overall_avg_mshr_uncacheable_latency")
2107 .desc("average overall mshr uncacheable latency")
2108 .flags(total
| nozero
| nonan
)
2110 overallAvgMshrUncacheableLatency
=
2111 overallMshrUncacheableLatency
/ overallMshrUncacheable
;
2112 for (int i
= 0; i
< system
->maxMasters(); i
++) {
2113 overallAvgMshrUncacheableLatency
.subname(i
, system
->getMasterName(i
));
2117 .name(name() + ".replacements")
2118 .desc("number of replacements")
2128 BaseCache::CpuSidePort::recvTimingSnoopResp(PacketPtr pkt
)
2130 // Snoops shouldn't happen when bypassing caches
2131 assert(!cache
->system
->bypassCaches());
2133 assert(pkt
->isResponse());
2135 // Express snoop responses from master to slave, e.g., from L1 to L2
2136 cache
->recvTimingSnoopResp(pkt
);
2142 BaseCache::CpuSidePort::tryTiming(PacketPtr pkt
)
2144 if (cache
->system
->bypassCaches() || pkt
->isExpressSnoop()) {
2145 // always let express snoop packets through even if blocked
2147 } else if (blocked
|| mustSendRetry
) {
2148 // either already committed to send a retry, or blocked
2149 mustSendRetry
= true;
2152 mustSendRetry
= false;
2157 BaseCache::CpuSidePort::recvTimingReq(PacketPtr pkt
)
2159 assert(pkt
->isRequest());
2161 if (cache
->system
->bypassCaches()) {
2162 // Just forward the packet if caches are disabled.
2163 // @todo This should really enqueue the packet rather
2164 bool M5_VAR_USED success
= cache
->memSidePort
.sendTimingReq(pkt
);
2167 } else if (tryTiming(pkt
)) {
2168 cache
->recvTimingReq(pkt
);
2175 BaseCache::CpuSidePort::recvAtomic(PacketPtr pkt
)
2177 if (cache
->system
->bypassCaches()) {
2178 // Forward the request if the system is in cache bypass mode.
2179 return cache
->memSidePort
.sendAtomic(pkt
);
2181 return cache
->recvAtomic(pkt
);
2186 BaseCache::CpuSidePort::recvFunctional(PacketPtr pkt
)
2188 if (cache
->system
->bypassCaches()) {
2189 // The cache should be flushed if we are in cache bypass mode,
2190 // so we don't need to check if we need to update anything.
2191 cache
->memSidePort
.sendFunctional(pkt
);
2195 // functional request
2196 cache
->functionalAccess(pkt
, true);
2200 BaseCache::CpuSidePort::getAddrRanges() const
2202 return cache
->getAddrRanges();
2207 CpuSidePort::CpuSidePort(const std::string
&_name
, BaseCache
*_cache
,
2208 const std::string
&_label
)
2209 : CacheSlavePort(_name
, _cache
, _label
), cache(_cache
)
2219 BaseCache::MemSidePort::recvTimingResp(PacketPtr pkt
)
2221 cache
->recvTimingResp(pkt
);
2225 // Express snooping requests to memside port
2227 BaseCache::MemSidePort::recvTimingSnoopReq(PacketPtr pkt
)
2229 // Snoops shouldn't happen when bypassing caches
2230 assert(!cache
->system
->bypassCaches());
2232 // handle snooping requests
2233 cache
->recvTimingSnoopReq(pkt
);
2237 BaseCache::MemSidePort::recvAtomicSnoop(PacketPtr pkt
)
2239 // Snoops shouldn't happen when bypassing caches
2240 assert(!cache
->system
->bypassCaches());
2242 return cache
->recvAtomicSnoop(pkt
);
2246 BaseCache::MemSidePort::recvFunctionalSnoop(PacketPtr pkt
)
2248 // Snoops shouldn't happen when bypassing caches
2249 assert(!cache
->system
->bypassCaches());
2251 // functional snoop (note that in contrast to atomic we don't have
2252 // a specific functionalSnoop method, as they have the same
2253 // behaviour regardless)
2254 cache
->functionalAccess(pkt
, false);
2258 BaseCache::CacheReqPacketQueue::sendDeferredPacket()
2261 assert(!waitingOnRetry
);
2263 // there should never be any deferred request packets in the
2264 // queue, instead we resly on the cache to provide the packets
2265 // from the MSHR queue or write queue
2266 assert(deferredPacketReadyTime() == MaxTick
);
2268 // check for request packets (requests & writebacks)
2269 QueueEntry
* entry
= cache
.getNextQueueEntry();
2272 // can happen if e.g. we attempt a writeback and fail, but
2273 // before the retry, the writeback is eliminated because
2274 // we snoop another cache's ReadEx.
2276 // let our snoop responses go first if there are responses to
2277 // the same addresses
2278 if (checkConflictingSnoop(entry
->blkAddr
)) {
2281 waitingOnRetry
= entry
->sendPacket(cache
);
2284 // if we succeeded and are not waiting for a retry, schedule the
2285 // next send considering when the next queue is ready, note that
2286 // snoop responses have their own packet queue and thus schedule
2288 if (!waitingOnRetry
) {
2289 schedSendEvent(cache
.nextQueueReadyTime());
2293 BaseCache::MemSidePort::MemSidePort(const std::string
&_name
,
2295 const std::string
&_label
)
2296 : CacheMasterPort(_name
, _cache
, _reqQueue
, _snoopRespQueue
),
2297 _reqQueue(*_cache
, *this, _snoopRespQueue
, _label
),
2298 _snoopRespQueue(*_cache
, *this, _label
), cache(_cache
)