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40 * Authors: Erik Hallnor
47 * Declares a basic cache interface BaseCache.
50 #ifndef __BASE_CACHE_HH__
51 #define __BASE_CACHE_HH__
58 #include "base/misc.hh"
59 #include "base/statistics.hh"
60 #include "base/trace.hh"
61 #include "base/types.hh"
62 #include "debug/Cache.hh"
63 #include "debug/CachePort.hh"
64 #include "mem/cache/mshr_queue.hh"
65 #include "mem/mem_object.hh"
66 #include "mem/packet.hh"
67 #include "mem/qport.hh"
68 #include "mem/request.hh"
69 #include "params/BaseCache.hh"
70 #include "sim/eventq.hh"
71 #include "sim/full_system.hh"
72 #include "sim/sim_exit.hh"
73 #include "sim/system.hh"
77 * A basic cache interface. Implements some common functions for speed.
79 class BaseCache : public MemObject
82 * Indexes to enumerate the MSHR queues.
91 * Reasons for caches to be blocked.
94 Blocked_NoMSHRs = MSHRQueue_MSHRs,
95 Blocked_NoWBBuffers = MSHRQueue_WriteBuffer,
97 Blocked_PendingWriteInvalidate,
102 * Reasons for cache to request a bus.
105 Request_MSHR = MSHRQueue_MSHRs,
106 Request_WB = MSHRQueue_WriteBuffer,
114 * A cache master port is used for the memory-side port of the
115 * cache, and in addition to the basic timing port that only sends
116 * response packets through a transmit list, it also offers the
117 * ability to schedule and send request packets (requests &
118 * writebacks). The send event is scheduled through requestBus,
119 * and the sendDeferredPacket of the timing port is modified to
120 * consider both the transmit list and the requests from the MSHR.
122 class CacheMasterPort : public QueuedMasterPort
128 * Schedule a send of a request packet (from the MSHR). Note
129 * that we could already have a retry or a transmit list of
130 * responses outstanding.
132 void requestBus(RequestCause cause, Tick time)
134 DPRINTF(CachePort, "Asserting bus request for cause %d\n", cause);
135 queue.schedSendEvent(time);
140 CacheMasterPort(const std::string &_name, BaseCache *_cache,
141 MasterPacketQueue &_queue) :
142 QueuedMasterPort(_name, _cache, _queue)
146 * Memory-side port always snoops.
148 * @return always true
150 virtual bool isSnooping() const { return true; }
154 * A cache slave port is used for the CPU-side port of the cache,
155 * and it is basically a simple timing port that uses a transmit
156 * list for responses to the CPU (or connected master). In
157 * addition, it has the functionality to block the port for
158 * incoming requests. If blocked, the port will issue a retry once
161 class CacheSlavePort : public QueuedSlavePort
166 /** Do not accept any new requests. */
169 /** Return to normal operation and accept new requests. */
172 bool isBlocked() const { return blocked; }
176 CacheSlavePort(const std::string &_name, BaseCache *_cache,
177 const std::string &_label);
179 /** A normal packet queue used to store responses. */
180 SlavePacketQueue queue;
188 void processSendRetry();
190 EventWrapper<CacheSlavePort,
191 &CacheSlavePort::processSendRetry> sendRetryEvent;
195 CacheSlavePort *cpuSidePort;
196 CacheMasterPort *memSidePort;
200 /** Miss status registers */
203 /** Write/writeback buffer */
204 MSHRQueue writeBuffer;
206 MSHR *allocateBufferInternal(MSHRQueue *mq, Addr addr, int size,
207 PacketPtr pkt, Tick time, bool requestBus)
209 MSHR *mshr = mq->allocate(addr, size, pkt, time, order++);
212 setBlocked((BlockedCause)mq->index);
216 requestMemSideBus((RequestCause)mq->index, time);
222 void markInServiceInternal(MSHR *mshr, PacketPtr pkt)
224 MSHRQueue *mq = mshr->queue;
225 bool wasFull = mq->isFull();
226 mq->markInService(mshr, pkt);
227 if (wasFull && !mq->isFull()) {
228 clearBlocked((BlockedCause)mq->index);
233 * Write back dirty blocks in the cache using functional accesses.
235 virtual void memWriteback() = 0;
237 * Invalidates all blocks in the cache.
239 * @warn Dirty cache lines will not be written back to
240 * memory. Make sure to call functionalWriteback() first if you
241 * want the to write them to memory.
243 virtual void memInvalidate() = 0;
245 * Determine if there are any dirty blocks in the cache.
247 * \return true if at least one block is dirty, false otherwise.
249 virtual bool isDirty() const = 0;
251 /** Block size of this cache */
252 const unsigned blkSize;
255 * The latency of a hit in this device.
257 const Cycles hitLatency;
260 * The latency of sending reponse to its upper level cache/core on a
261 * linefill. In most contemporary processors, the return path on a cache
262 * miss is much quicker that the hit latency. The responseLatency parameter
263 * tries to capture this latency.
265 const Cycles responseLatency;
267 /** The number of targets for each MSHR. */
270 /** Do we forward snoops from mem side port through to cpu side port? */
271 const bool forwardSnoops;
273 /** Is this cache a toplevel cache (e.g. L1, I/O cache). If so we should
274 * never try to forward ownership and similar optimizations to the cpu
276 const bool isTopLevel;
279 * Bit vector of the blocking reasons for the access path.
284 /** Increasing order number assigned to each incoming request. */
287 /** Stores time the cache blocked for statistics. */
290 /** Pointer to the MSHR that has no targets. */
293 /** The number of misses to trigger an exit event. */
297 * The address range to which the cache responds on the CPU side.
298 * Normally this is all possible memory addresses. */
299 const AddrRangeList addrRanges;
302 /** System we are currently operating in. */
307 * @addtogroup CacheStatistics
311 /** Number of hits per thread for each type of command. @sa Packet::Command */
312 Stats::Vector hits[MemCmd::NUM_MEM_CMDS];
313 /** Number of hits for demand accesses. */
314 Stats::Formula demandHits;
315 /** Number of hit for all accesses. */
316 Stats::Formula overallHits;
318 /** Number of misses per thread for each type of command. @sa Packet::Command */
319 Stats::Vector misses[MemCmd::NUM_MEM_CMDS];
320 /** Number of misses for demand accesses. */
321 Stats::Formula demandMisses;
322 /** Number of misses for all accesses. */
323 Stats::Formula overallMisses;
326 * Total number of cycles per thread/command spent waiting for a miss.
327 * Used to calculate the average miss latency.
329 Stats::Vector missLatency[MemCmd::NUM_MEM_CMDS];
330 /** Total number of cycles spent waiting for demand misses. */
331 Stats::Formula demandMissLatency;
332 /** Total number of cycles spent waiting for all misses. */
333 Stats::Formula overallMissLatency;
335 /** The number of accesses per command and thread. */
336 Stats::Formula accesses[MemCmd::NUM_MEM_CMDS];
337 /** The number of demand accesses. */
338 Stats::Formula demandAccesses;
339 /** The number of overall accesses. */
340 Stats::Formula overallAccesses;
342 /** The miss rate per command and thread. */
343 Stats::Formula missRate[MemCmd::NUM_MEM_CMDS];
344 /** The miss rate of all demand accesses. */
345 Stats::Formula demandMissRate;
346 /** The miss rate for all accesses. */
347 Stats::Formula overallMissRate;
349 /** The average miss latency per command and thread. */
350 Stats::Formula avgMissLatency[MemCmd::NUM_MEM_CMDS];
351 /** The average miss latency for demand misses. */
352 Stats::Formula demandAvgMissLatency;
353 /** The average miss latency for all misses. */
354 Stats::Formula overallAvgMissLatency;
356 /** The total number of cycles blocked for each blocked cause. */
357 Stats::Vector blocked_cycles;
358 /** The number of times this cache blocked for each blocked cause. */
359 Stats::Vector blocked_causes;
361 /** The average number of cycles blocked for each blocked cause. */
362 Stats::Formula avg_blocked;
364 /** The number of fast writes (WH64) performed. */
365 Stats::Scalar fastWrites;
367 /** The number of cache copies performed. */
368 Stats::Scalar cacheCopies;
370 /** Number of blocks written back per thread. */
371 Stats::Vector writebacks;
373 /** Number of misses that hit in the MSHRs per command and thread. */
374 Stats::Vector mshr_hits[MemCmd::NUM_MEM_CMDS];
375 /** Demand misses that hit in the MSHRs. */
376 Stats::Formula demandMshrHits;
377 /** Total number of misses that hit in the MSHRs. */
378 Stats::Formula overallMshrHits;
380 /** Number of misses that miss in the MSHRs, per command and thread. */
381 Stats::Vector mshr_misses[MemCmd::NUM_MEM_CMDS];
382 /** Demand misses that miss in the MSHRs. */
383 Stats::Formula demandMshrMisses;
384 /** Total number of misses that miss in the MSHRs. */
385 Stats::Formula overallMshrMisses;
387 /** Number of misses that miss in the MSHRs, per command and thread. */
388 Stats::Vector mshr_uncacheable[MemCmd::NUM_MEM_CMDS];
389 /** Total number of misses that miss in the MSHRs. */
390 Stats::Formula overallMshrUncacheable;
392 /** Total cycle latency of each MSHR miss, per command and thread. */
393 Stats::Vector mshr_miss_latency[MemCmd::NUM_MEM_CMDS];
394 /** Total cycle latency of demand MSHR misses. */
395 Stats::Formula demandMshrMissLatency;
396 /** Total cycle latency of overall MSHR misses. */
397 Stats::Formula overallMshrMissLatency;
399 /** Total cycle latency of each MSHR miss, per command and thread. */
400 Stats::Vector mshr_uncacheable_lat[MemCmd::NUM_MEM_CMDS];
401 /** Total cycle latency of overall MSHR misses. */
402 Stats::Formula overallMshrUncacheableLatency;
405 /** The total number of MSHR accesses per command and thread. */
406 Stats::Formula mshrAccesses[MemCmd::NUM_MEM_CMDS];
407 /** The total number of demand MSHR accesses. */
408 Stats::Formula demandMshrAccesses;
409 /** The total number of MSHR accesses. */
410 Stats::Formula overallMshrAccesses;
413 /** The miss rate in the MSHRs pre command and thread. */
414 Stats::Formula mshrMissRate[MemCmd::NUM_MEM_CMDS];
415 /** The demand miss rate in the MSHRs. */
416 Stats::Formula demandMshrMissRate;
417 /** The overall miss rate in the MSHRs. */
418 Stats::Formula overallMshrMissRate;
420 /** The average latency of an MSHR miss, per command and thread. */
421 Stats::Formula avgMshrMissLatency[MemCmd::NUM_MEM_CMDS];
422 /** The average latency of a demand MSHR miss. */
423 Stats::Formula demandAvgMshrMissLatency;
424 /** The average overall latency of an MSHR miss. */
425 Stats::Formula overallAvgMshrMissLatency;
427 /** The average latency of an MSHR miss, per command and thread. */
428 Stats::Formula avgMshrUncacheableLatency[MemCmd::NUM_MEM_CMDS];
429 /** The average overall latency of an MSHR miss. */
430 Stats::Formula overallAvgMshrUncacheableLatency;
432 /** The number of times a thread hit its MSHR cap. */
433 Stats::Vector mshr_cap_events;
434 /** The number of times software prefetches caused the MSHR to block. */
435 Stats::Vector soft_prefetch_mshr_full;
437 Stats::Scalar mshr_no_allocate_misses;
444 * Register stats for this object.
446 virtual void regStats();
449 typedef BaseCacheParams Params;
450 BaseCache(const Params *p);
455 virtual BaseMasterPort &getMasterPort(const std::string &if_name,
456 PortID idx = InvalidPortID);
457 virtual BaseSlavePort &getSlavePort(const std::string &if_name,
458 PortID idx = InvalidPortID);
461 * Query block size of a cache.
462 * @return The block size
471 Addr blockAlign(Addr addr) const { return (addr & ~(Addr(blkSize - 1))); }
474 const AddrRangeList &getAddrRanges() const { return addrRanges; }
476 MSHR *allocateMissBuffer(PacketPtr pkt, Tick time, bool requestBus)
478 assert(!pkt->req->isUncacheable());
479 return allocateBufferInternal(&mshrQueue,
480 blockAlign(pkt->getAddr()), blkSize,
481 pkt, time, requestBus);
484 MSHR *allocateWriteBuffer(PacketPtr pkt, Tick time, bool requestBus)
486 assert(pkt->isWrite() && !pkt->isRead());
487 return allocateBufferInternal(&writeBuffer,
488 pkt->getAddr(), pkt->getSize(),
489 pkt, time, requestBus);
492 MSHR *allocateUncachedReadBuffer(PacketPtr pkt, Tick time, bool requestBus)
494 assert(pkt->req->isUncacheable());
495 assert(pkt->isRead());
496 return allocateBufferInternal(&mshrQueue,
497 pkt->getAddr(), pkt->getSize(),
498 pkt, time, requestBus);
502 * Returns true if the cache is blocked for accesses.
504 bool isBlocked() const
510 * Marks the access path of the cache as blocked for the given cause. This
511 * also sets the blocked flag in the slave interface.
512 * @param cause The reason for the cache blocking.
514 void setBlocked(BlockedCause cause)
516 uint8_t flag = 1 << cause;
518 blocked_causes[cause]++;
519 blockedCycle = curCycle();
520 cpuSidePort->setBlocked();
523 DPRINTF(Cache,"Blocking for cause %d, mask=%d\n", cause, blocked);
527 * Marks the cache as unblocked for the given cause. This also clears the
528 * blocked flags in the appropriate interfaces.
529 * @param cause The newly unblocked cause.
530 * @warning Calling this function can cause a blocked request on the bus to
531 * access the cache. The cache must be in a state to handle that request.
533 void clearBlocked(BlockedCause cause)
535 uint8_t flag = 1 << cause;
537 DPRINTF(Cache,"Unblocking for cause %d, mask=%d\n", cause, blocked);
539 blocked_cycles[cause] += curCycle() - blockedCycle;
540 cpuSidePort->clearBlocked();
545 * Request the master bus for the given cause and time.
546 * @param cause The reason for the request.
547 * @param time The time to make the request.
549 void requestMemSideBus(RequestCause cause, Tick time)
551 memSidePort->requestBus(cause, time);
555 * Clear the master bus request for the given cause.
556 * @param cause The request reason to clear.
558 void deassertMemSideBusRequest(RequestCause cause)
560 // Obsolete... we no longer signal bus requests explicitly so
561 // we can't deassert them. Leaving this in as a no-op since
562 // the prefetcher calls it to indicate that it no longer wants
563 // to request a prefetch, and someday that might be
564 // interesting again.
567 virtual unsigned int drain(DrainManager *dm);
569 virtual bool inCache(Addr addr, bool is_secure) const = 0;
571 virtual bool inMissQueue(Addr addr, bool is_secure) const = 0;
573 void incMissCount(PacketPtr pkt)
575 assert(pkt->req->masterId() < system->maxMasters());
576 misses[pkt->cmdToIndex()][pkt->req->masterId()]++;
577 pkt->req->incAccessDepth();
581 exitSimLoop("A cache reached the maximum miss count");
584 void incHitCount(PacketPtr pkt)
586 assert(pkt->req->masterId() < system->maxMasters());
587 hits[pkt->cmdToIndex()][pkt->req->masterId()]++;
593 #endif //__BASE_CACHE_HH__