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40 * Authors: Erik Hallnor
47 * Declares a basic cache interface BaseCache.
50 #ifndef __BASE_CACHE_HH__
51 #define __BASE_CACHE_HH__
58 #include "base/misc.hh"
59 #include "base/statistics.hh"
60 #include "base/trace.hh"
61 #include "base/types.hh"
62 #include "debug/Cache.hh"
63 #include "debug/CachePort.hh"
64 #include "mem/cache/mshr_queue.hh"
65 #include "mem/mem_object.hh"
66 #include "mem/packet.hh"
67 #include "mem/qport.hh"
68 #include "mem/request.hh"
69 #include "params/BaseCache.hh"
70 #include "sim/eventq.hh"
71 #include "sim/full_system.hh"
72 #include "sim/sim_exit.hh"
73 #include "sim/system.hh"
77 * A basic cache interface. Implements some common functions for speed.
79 class BaseCache : public MemObject
82 * Indexes to enumerate the MSHR queues.
91 * Reasons for caches to be blocked.
94 Blocked_NoMSHRs = MSHRQueue_MSHRs,
95 Blocked_NoWBBuffers = MSHRQueue_WriteBuffer,
101 * Reasons for cache to request a bus.
104 Request_MSHR = MSHRQueue_MSHRs,
105 Request_WB = MSHRQueue_WriteBuffer,
113 * A cache master port is used for the memory-side port of the
114 * cache, and in addition to the basic timing port that only sends
115 * response packets through a transmit list, it also offers the
116 * ability to schedule and send request packets (requests &
117 * writebacks). The send event is scheduled through requestBus,
118 * and the sendDeferredPacket of the timing port is modified to
119 * consider both the transmit list and the requests from the MSHR.
121 class CacheMasterPort : public QueuedMasterPort
127 * Schedule a send of a request packet (from the MSHR). Note
128 * that we could already have a retry or a transmit list of
129 * responses outstanding.
131 void requestBus(RequestCause cause, Tick time)
133 DPRINTF(CachePort, "Asserting bus request for cause %d\n", cause);
134 queue.schedSendEvent(time);
139 CacheMasterPort(const std::string &_name, BaseCache *_cache,
140 MasterPacketQueue &_queue) :
141 QueuedMasterPort(_name, _cache, _queue)
145 * Memory-side port always snoops.
147 * @return always true
149 virtual bool isSnooping() const { return true; }
153 * A cache slave port is used for the CPU-side port of the cache,
154 * and it is basically a simple timing port that uses a transmit
155 * list for responses to the CPU (or connected master). In
156 * addition, it has the functionality to block the port for
157 * incoming requests. If blocked, the port will issue a retry once
160 class CacheSlavePort : public QueuedSlavePort
165 /** Do not accept any new requests. */
168 /** Return to normal operation and accept new requests. */
173 CacheSlavePort(const std::string &_name, BaseCache *_cache,
174 const std::string &_label);
176 /** A normal packet queue used to store responses. */
177 SlavePacketQueue queue;
185 EventWrapper<SlavePort, &SlavePort::sendRetry> sendRetryEvent;
189 CacheSlavePort *cpuSidePort;
190 CacheMasterPort *memSidePort;
194 /** Miss status registers */
197 /** Write/writeback buffer */
198 MSHRQueue writeBuffer;
200 MSHR *allocateBufferInternal(MSHRQueue *mq, Addr addr, int size,
201 PacketPtr pkt, Tick time, bool requestBus)
203 MSHR *mshr = mq->allocate(addr, size, pkt, time, order++);
206 setBlocked((BlockedCause)mq->index);
210 requestMemSideBus((RequestCause)mq->index, time);
216 void markInServiceInternal(MSHR *mshr, PacketPtr pkt)
218 MSHRQueue *mq = mshr->queue;
219 bool wasFull = mq->isFull();
220 mq->markInService(mshr, pkt);
221 if (wasFull && !mq->isFull()) {
222 clearBlocked((BlockedCause)mq->index);
226 /** Block size of this cache */
227 const unsigned blkSize;
230 * The latency of a hit in this device.
232 const Cycles hitLatency;
235 * The latency of sending reponse to its upper level cache/core on a
236 * linefill. In most contemporary processors, the return path on a cache
237 * miss is much quicker that the hit latency. The responseLatency parameter
238 * tries to capture this latency.
240 const Cycles responseLatency;
242 /** The number of targets for each MSHR. */
245 /** Do we forward snoops from mem side port through to cpu side port? */
248 /** Is this cache a toplevel cache (e.g. L1, I/O cache). If so we should
249 * never try to forward ownership and similar optimizations to the cpu
254 * Bit vector of the blocking reasons for the access path.
259 /** Increasing order number assigned to each incoming request. */
262 /** Stores time the cache blocked for statistics. */
265 /** Pointer to the MSHR that has no targets. */
268 /** The number of misses to trigger an exit event. */
271 /** The drain event. */
275 * The address range to which the cache responds on the CPU side.
276 * Normally this is all possible memory addresses. */
277 AddrRangeList addrRanges;
280 /** System we are currently operating in. */
285 * @addtogroup CacheStatistics
289 /** Number of hits per thread for each type of command. @sa Packet::Command */
290 Stats::Vector hits[MemCmd::NUM_MEM_CMDS];
291 /** Number of hits for demand accesses. */
292 Stats::Formula demandHits;
293 /** Number of hit for all accesses. */
294 Stats::Formula overallHits;
296 /** Number of misses per thread for each type of command. @sa Packet::Command */
297 Stats::Vector misses[MemCmd::NUM_MEM_CMDS];
298 /** Number of misses for demand accesses. */
299 Stats::Formula demandMisses;
300 /** Number of misses for all accesses. */
301 Stats::Formula overallMisses;
304 * Total number of cycles per thread/command spent waiting for a miss.
305 * Used to calculate the average miss latency.
307 Stats::Vector missLatency[MemCmd::NUM_MEM_CMDS];
308 /** Total number of cycles spent waiting for demand misses. */
309 Stats::Formula demandMissLatency;
310 /** Total number of cycles spent waiting for all misses. */
311 Stats::Formula overallMissLatency;
313 /** The number of accesses per command and thread. */
314 Stats::Formula accesses[MemCmd::NUM_MEM_CMDS];
315 /** The number of demand accesses. */
316 Stats::Formula demandAccesses;
317 /** The number of overall accesses. */
318 Stats::Formula overallAccesses;
320 /** The miss rate per command and thread. */
321 Stats::Formula missRate[MemCmd::NUM_MEM_CMDS];
322 /** The miss rate of all demand accesses. */
323 Stats::Formula demandMissRate;
324 /** The miss rate for all accesses. */
325 Stats::Formula overallMissRate;
327 /** The average miss latency per command and thread. */
328 Stats::Formula avgMissLatency[MemCmd::NUM_MEM_CMDS];
329 /** The average miss latency for demand misses. */
330 Stats::Formula demandAvgMissLatency;
331 /** The average miss latency for all misses. */
332 Stats::Formula overallAvgMissLatency;
334 /** The total number of cycles blocked for each blocked cause. */
335 Stats::Vector blocked_cycles;
336 /** The number of times this cache blocked for each blocked cause. */
337 Stats::Vector blocked_causes;
339 /** The average number of cycles blocked for each blocked cause. */
340 Stats::Formula avg_blocked;
342 /** The number of fast writes (WH64) performed. */
343 Stats::Scalar fastWrites;
345 /** The number of cache copies performed. */
346 Stats::Scalar cacheCopies;
348 /** Number of blocks written back per thread. */
349 Stats::Vector writebacks;
351 /** Number of misses that hit in the MSHRs per command and thread. */
352 Stats::Vector mshr_hits[MemCmd::NUM_MEM_CMDS];
353 /** Demand misses that hit in the MSHRs. */
354 Stats::Formula demandMshrHits;
355 /** Total number of misses that hit in the MSHRs. */
356 Stats::Formula overallMshrHits;
358 /** Number of misses that miss in the MSHRs, per command and thread. */
359 Stats::Vector mshr_misses[MemCmd::NUM_MEM_CMDS];
360 /** Demand misses that miss in the MSHRs. */
361 Stats::Formula demandMshrMisses;
362 /** Total number of misses that miss in the MSHRs. */
363 Stats::Formula overallMshrMisses;
365 /** Number of misses that miss in the MSHRs, per command and thread. */
366 Stats::Vector mshr_uncacheable[MemCmd::NUM_MEM_CMDS];
367 /** Total number of misses that miss in the MSHRs. */
368 Stats::Formula overallMshrUncacheable;
370 /** Total cycle latency of each MSHR miss, per command and thread. */
371 Stats::Vector mshr_miss_latency[MemCmd::NUM_MEM_CMDS];
372 /** Total cycle latency of demand MSHR misses. */
373 Stats::Formula demandMshrMissLatency;
374 /** Total cycle latency of overall MSHR misses. */
375 Stats::Formula overallMshrMissLatency;
377 /** Total cycle latency of each MSHR miss, per command and thread. */
378 Stats::Vector mshr_uncacheable_lat[MemCmd::NUM_MEM_CMDS];
379 /** Total cycle latency of overall MSHR misses. */
380 Stats::Formula overallMshrUncacheableLatency;
383 /** The total number of MSHR accesses per command and thread. */
384 Stats::Formula mshrAccesses[MemCmd::NUM_MEM_CMDS];
385 /** The total number of demand MSHR accesses. */
386 Stats::Formula demandMshrAccesses;
387 /** The total number of MSHR accesses. */
388 Stats::Formula overallMshrAccesses;
391 /** The miss rate in the MSHRs pre command and thread. */
392 Stats::Formula mshrMissRate[MemCmd::NUM_MEM_CMDS];
393 /** The demand miss rate in the MSHRs. */
394 Stats::Formula demandMshrMissRate;
395 /** The overall miss rate in the MSHRs. */
396 Stats::Formula overallMshrMissRate;
398 /** The average latency of an MSHR miss, per command and thread. */
399 Stats::Formula avgMshrMissLatency[MemCmd::NUM_MEM_CMDS];
400 /** The average latency of a demand MSHR miss. */
401 Stats::Formula demandAvgMshrMissLatency;
402 /** The average overall latency of an MSHR miss. */
403 Stats::Formula overallAvgMshrMissLatency;
405 /** The average latency of an MSHR miss, per command and thread. */
406 Stats::Formula avgMshrUncacheableLatency[MemCmd::NUM_MEM_CMDS];
407 /** The average overall latency of an MSHR miss. */
408 Stats::Formula overallAvgMshrUncacheableLatency;
410 /** The number of times a thread hit its MSHR cap. */
411 Stats::Vector mshr_cap_events;
412 /** The number of times software prefetches caused the MSHR to block. */
413 Stats::Vector soft_prefetch_mshr_full;
415 Stats::Scalar mshr_no_allocate_misses;
422 * Register stats for this object.
424 virtual void regStats();
427 typedef BaseCacheParams Params;
428 BaseCache(const Params *p);
433 virtual MasterPort &getMasterPort(const std::string &if_name, int idx = -1);
434 virtual SlavePort &getSlavePort(const std::string &if_name, int idx = -1);
437 * Query block size of a cache.
438 * @return The block size
447 Addr blockAlign(Addr addr) const { return (addr & ~(Addr(blkSize - 1))); }
450 const AddrRangeList &getAddrRanges() const { return addrRanges; }
452 MSHR *allocateMissBuffer(PacketPtr pkt, Tick time, bool requestBus)
454 assert(!pkt->req->isUncacheable());
455 return allocateBufferInternal(&mshrQueue,
456 blockAlign(pkt->getAddr()), blkSize,
457 pkt, time, requestBus);
460 MSHR *allocateWriteBuffer(PacketPtr pkt, Tick time, bool requestBus)
462 assert(pkt->isWrite() && !pkt->isRead());
463 return allocateBufferInternal(&writeBuffer,
464 pkt->getAddr(), pkt->getSize(),
465 pkt, time, requestBus);
468 MSHR *allocateUncachedReadBuffer(PacketPtr pkt, Tick time, bool requestBus)
470 assert(pkt->req->isUncacheable());
471 assert(pkt->isRead());
472 return allocateBufferInternal(&mshrQueue,
473 pkt->getAddr(), pkt->getSize(),
474 pkt, time, requestBus);
478 * Returns true if the cache is blocked for accesses.
486 * Marks the access path of the cache as blocked for the given cause. This
487 * also sets the blocked flag in the slave interface.
488 * @param cause The reason for the cache blocking.
490 void setBlocked(BlockedCause cause)
492 uint8_t flag = 1 << cause;
494 blocked_causes[cause]++;
495 blockedCycle = curCycle();
496 cpuSidePort->setBlocked();
499 DPRINTF(Cache,"Blocking for cause %d, mask=%d\n", cause, blocked);
503 * Marks the cache as unblocked for the given cause. This also clears the
504 * blocked flags in the appropriate interfaces.
505 * @param cause The newly unblocked cause.
506 * @warning Calling this function can cause a blocked request on the bus to
507 * access the cache. The cache must be in a state to handle that request.
509 void clearBlocked(BlockedCause cause)
511 uint8_t flag = 1 << cause;
513 DPRINTF(Cache,"Unblocking for cause %d, mask=%d\n", cause, blocked);
515 blocked_cycles[cause] += curCycle() - blockedCycle;
516 cpuSidePort->clearBlocked();
521 * Request the master bus for the given cause and time.
522 * @param cause The reason for the request.
523 * @param time The time to make the request.
525 void requestMemSideBus(RequestCause cause, Tick time)
527 memSidePort->requestBus(cause, time);
531 * Clear the master bus request for the given cause.
532 * @param cause The request reason to clear.
534 void deassertMemSideBusRequest(RequestCause cause)
536 // Obsolete... we no longer signal bus requests explicitly so
537 // we can't deassert them. Leaving this in as a no-op since
538 // the prefetcher calls it to indicate that it no longer wants
539 // to request a prefetch, and someday that might be
540 // interesting again.
543 virtual unsigned int drain(Event *de);
545 virtual bool inCache(Addr addr) = 0;
547 virtual bool inMissQueue(Addr addr) = 0;
549 void incMissCount(PacketPtr pkt)
551 assert(pkt->req->masterId() < system->maxMasters());
552 misses[pkt->cmdToIndex()][pkt->req->masterId()]++;
557 exitSimLoop("A cache reached the maximum miss count");
560 void incHitCount(PacketPtr pkt)
562 assert(pkt->req->masterId() < system->maxMasters());
563 hits[pkt->cmdToIndex()][pkt->req->masterId()]++;
569 #endif //__BASE_CACHE_HH__