src/mem/cache/base.hh

   1 /*
   2  * Copyright (c) 2012-2013, 2015 ARM Limited
   3  * All rights reserved.
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2003-2005 The Regents of The University of Michigan
  15  * All rights reserved.
  16  *
  17  * Redistribution and use in source and binary forms, with or without
  18  * modification, are permitted provided that the following conditions are
  19  * met: redistributions of source code must retain the above copyright
  20  * notice, this list of conditions and the following disclaimer;
  21  * redistributions in binary form must reproduce the above copyright
  22  * notice, this list of conditions and the following disclaimer in the
  23  * documentation and/or other materials provided with the distribution;
  24  * neither the name of the copyright holders nor the names of its
  25  * contributors may be used to endorse or promote products derived from
  26  * this software without specific prior written permission.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  33  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  34  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  35  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  36  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  37  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39  *
  40  * Authors: Erik Hallnor
  41  *          Steve Reinhardt
  42  *          Ron Dreslinski
  43  */
  44
  45 /**
  46  * @file
  47  * Declares a basic cache interface BaseCache.
  48  */
  49
  50 #ifndef __MEM_CACHE_BASE_HH__
  51 #define __MEM_CACHE_BASE_HH__
  52
  53 #include <algorithm>
  54 #include <list>
  55 #include <string>
  56 #include <vector>
  57
  58 #include "base/misc.hh"
  59 #include "base/statistics.hh"
  60 #include "base/trace.hh"
  61 #include "base/types.hh"
  62 #include "debug/Cache.hh"
  63 #include "debug/CachePort.hh"
  64 #include "mem/cache/mshr_queue.hh"
  65 #include "mem/mem_object.hh"
  66 #include "mem/packet.hh"
  67 #include "mem/qport.hh"
  68 #include "mem/request.hh"
  69 #include "params/BaseCache.hh"
  70 #include "sim/eventq.hh"
  71 #include "sim/full_system.hh"
  72 #include "sim/sim_exit.hh"
  73 #include "sim/system.hh"
  74
  75 class MSHR;
  76 /**
  77  * A basic cache interface. Implements some common functions for speed.
  78  */
  79 class BaseCache : public MemObject
  80 {
  81     /**
  82      * Indexes to enumerate the MSHR queues.
  83      */
  84     enum MSHRQueueIndex {
  85         MSHRQueue_MSHRs,
  86         MSHRQueue_WriteBuffer
  87     };
  88
  89   public:
  90     /**
  91      * Reasons for caches to be blocked.
  92      */
  93     enum BlockedCause {
  94         Blocked_NoMSHRs = MSHRQueue_MSHRs,
  95         Blocked_NoWBBuffers = MSHRQueue_WriteBuffer,
  96         Blocked_NoTargets,
  97         NUM_BLOCKED_CAUSES
  98     };
  99
 100   protected:
 101
 102     /**
 103      * A cache master port is used for the memory-side port of the
 104      * cache, and in addition to the basic timing port that only sends
 105      * response packets through a transmit list, it also offers the
 106      * ability to schedule and send request packets (requests &
 107      * writebacks). The send event is scheduled through schedSendEvent,
 108      * and the sendDeferredPacket of the timing port is modified to
 109      * consider both the transmit list and the requests from the MSHR.
 110      */
 111     class CacheMasterPort : public QueuedMasterPort
 112     {
 113
 114       public:
 115
 116         /**
 117          * Schedule a send of a request packet (from the MSHR). Note
 118          * that we could already have a retry outstanding.
 119          */
 120         void schedSendEvent(Tick time)
 121         {
 122             DPRINTF(CachePort, "Scheduling send event at %llu\n", time);
 123             reqQueue.schedSendEvent(time);
 124         }
 125
 126       protected:
 127
 128         CacheMasterPort(const std::string &_name, BaseCache *_cache,
 129                         ReqPacketQueue &_reqQueue,
 130                         SnoopRespPacketQueue &_snoopRespQueue) :
 131             QueuedMasterPort(_name, _cache, _reqQueue, _snoopRespQueue)
 132         { }
 133
 134         /**
 135          * Memory-side port always snoops.
 136          *
 137          * @return always true
 138          */
 139         virtual bool isSnooping() const { return true; }
 140     };
 141
 142     /**
 143      * A cache slave port is used for the CPU-side port of the cache,
 144      * and it is basically a simple timing port that uses a transmit
 145      * list for responses to the CPU (or connected master). In
 146      * addition, it has the functionality to block the port for
 147      * incoming requests. If blocked, the port will issue a retry once
 148      * unblocked.
 149      */
 150     class CacheSlavePort : public QueuedSlavePort
 151     {
 152
 153       public:
 154
 155         /** Do not accept any new requests. */
 156         void setBlocked();
 157
 158         /** Return to normal operation and accept new requests. */
 159         void clearBlocked();
 160
 161         bool isBlocked() const { return blocked; }
 162
 163       protected:
 164
 165         CacheSlavePort(const std::string &_name, BaseCache *_cache,
 166                        const std::string &_label);
 167
 168         /** A normal packet queue used to store responses. */
 169         RespPacketQueue queue;
 170
 171         bool blocked;
 172
 173         bool mustSendRetry;
 174
 175       private:
 176
 177         void processSendRetry();
 178
 179         EventWrapper<CacheSlavePort,
 180                      &CacheSlavePort::processSendRetry> sendRetryEvent;
 181
 182     };
 183
 184     CacheSlavePort *cpuSidePort;
 185     CacheMasterPort *memSidePort;
 186
 187   protected:
 188
 189     /** Miss status registers */
 190     MSHRQueue mshrQueue;
 191
 192     /** Write/writeback buffer */
 193     MSHRQueue writeBuffer;
 194
 195     /**
 196      * Allocate a buffer, passing the time indicating when schedule an
 197      * event to the queued port to go and ask the MSHR and write queue
 198      * if they have packets to send.
 199      *
 200      * allocateBufferInternal() function is called in:
 201      * - MSHR allocateWriteBuffer (unchached write forwarded to WriteBuffer);
 202      * - MSHR allocateMissBuffer (miss in MSHR queue);
 203      */
 204     MSHR *allocateBufferInternal(MSHRQueue *mq, Addr addr, int size,
 205                                  PacketPtr pkt, Tick time,
 206                                  bool sched_send)
 207     {
 208         // check that the address is block aligned since we rely on
 209         // this in a number of places when checking for matches and
 210         // overlap
 211         assert(addr == blockAlign(addr));
 212
 213         MSHR *mshr = mq->allocate(addr, size, pkt, time, order++);
 214
 215         if (mq->isFull()) {
 216             setBlocked((BlockedCause)mq->index);
 217         }
 218
 219         if (sched_send)
 220             // schedule the send
 221             schedMemSideSendEvent(time);
 222
 223         return mshr;
 224     }
 225
 226     void markInServiceInternal(MSHR *mshr, bool pending_dirty_resp)
 227     {
 228         MSHRQueue *mq = mshr->queue;
 229         bool wasFull = mq->isFull();
 230         mq->markInService(mshr, pending_dirty_resp);
 231         if (wasFull && !mq->isFull()) {
 232             clearBlocked((BlockedCause)mq->index);
 233         }
 234     }
 235
 236     /**
 237      * Write back dirty blocks in the cache using functional accesses.
 238      */
 239     virtual void memWriteback() = 0;
 240     /**
 241      * Invalidates all blocks in the cache.
 242      *
 243      * @warn Dirty cache lines will not be written back to
 244      * memory. Make sure to call functionalWriteback() first if you
 245      * want the to write them to memory.
 246      */
 247     virtual void memInvalidate() = 0;
 248     /**
 249      * Determine if there are any dirty blocks in the cache.
 250      *
 251      * \return true if at least one block is dirty, false otherwise.
 252      */
 253     virtual bool isDirty() const = 0;
 254
 255     /**
 256      * Determine if an address is in the ranges covered by this
 257      * cache. This is useful to filter snoops.
 258      *
 259      * @param addr Address to check against
 260      *
 261      * @return If the address in question is in range
 262      */
 263     bool inRange(Addr addr) const;
 264
 265     /** Block size of this cache */
 266     const unsigned blkSize;
 267
 268     /**
 269      * The latency of tag lookup of a cache. It occurs when there is
 270      * an access to the cache.
 271      */
 272     const Cycles lookupLatency;
 273
 274     /**
 275      * This is the forward latency of the cache. It occurs when there
 276      * is a cache miss and a request is forwarded downstream, in
 277      * particular an outbound miss.
 278      */
 279     const Cycles forwardLatency;
 280
 281     /** The latency to fill a cache block */
 282     const Cycles fillLatency;
 283
 284     /**
 285      * The latency of sending reponse to its upper level cache/core on
 286      * a linefill. The responseLatency parameter captures this
 287      * latency.
 288      */
 289     const Cycles responseLatency;
 290
 291     /** The number of targets for each MSHR. */
 292     const int numTarget;
 293
 294     /** Do we forward snoops from mem side port through to cpu side port? */
 295     const bool forwardSnoops;
 296
 297     /**
 298      * Is this cache read only, for example the instruction cache, or
 299      * table-walker cache. A cache that is read only should never see
 300      * any writes, and should never get any dirty data (and hence
 301      * never have to do any writebacks).
 302      */
 303     const bool isReadOnly;
 304
 305     /**
 306      * Bit vector of the blocking reasons for the access path.
 307      * @sa #BlockedCause
 308      */
 309     uint8_t blocked;
 310
 311     /** Increasing order number assigned to each incoming request. */
 312     uint64_t order;
 313
 314     /** Stores time the cache blocked for statistics. */
 315     Cycles blockedCycle;
 316
 317     /** Pointer to the MSHR that has no targets. */
 318     MSHR *noTargetMSHR;
 319
 320     /** The number of misses to trigger an exit event. */
 321     Counter missCount;
 322
 323     /**
 324      * The address range to which the cache responds on the CPU side.
 325      * Normally this is all possible memory addresses. */
 326     const AddrRangeList addrRanges;
 327
 328   public:
 329     /** System we are currently operating in. */
 330     System *system;
 331
 332     // Statistics
 333     /**
 334      * @addtogroup CacheStatistics
 335      * @{
 336      */
 337
 338     /** Number of hits per thread for each type of command. @sa Packet::Command */
 339     Stats::Vector hits[MemCmd::NUM_MEM_CMDS];
 340     /** Number of hits for demand accesses. */
 341     Stats::Formula demandHits;
 342     /** Number of hit for all accesses. */
 343     Stats::Formula overallHits;
 344
 345     /** Number of misses per thread for each type of command. @sa Packet::Command */
 346     Stats::Vector misses[MemCmd::NUM_MEM_CMDS];
 347     /** Number of misses for demand accesses. */
 348     Stats::Formula demandMisses;
 349     /** Number of misses for all accesses. */
 350     Stats::Formula overallMisses;
 351
 352     /**
 353      * Total number of cycles per thread/command spent waiting for a miss.
 354      * Used to calculate the average miss latency.
 355      */
 356     Stats::Vector missLatency[MemCmd::NUM_MEM_CMDS];
 357     /** Total number of cycles spent waiting for demand misses. */
 358     Stats::Formula demandMissLatency;
 359     /** Total number of cycles spent waiting for all misses. */
 360     Stats::Formula overallMissLatency;
 361
 362     /** The number of accesses per command and thread. */
 363     Stats::Formula accesses[MemCmd::NUM_MEM_CMDS];
 364     /** The number of demand accesses. */
 365     Stats::Formula demandAccesses;
 366     /** The number of overall accesses. */
 367     Stats::Formula overallAccesses;
 368
 369     /** The miss rate per command and thread. */
 370     Stats::Formula missRate[MemCmd::NUM_MEM_CMDS];
 371     /** The miss rate of all demand accesses. */
 372     Stats::Formula demandMissRate;
 373     /** The miss rate for all accesses. */
 374     Stats::Formula overallMissRate;
 375
 376     /** The average miss latency per command and thread. */
 377     Stats::Formula avgMissLatency[MemCmd::NUM_MEM_CMDS];
 378     /** The average miss latency for demand misses. */
 379     Stats::Formula demandAvgMissLatency;
 380     /** The average miss latency for all misses. */
 381     Stats::Formula overallAvgMissLatency;
 382
 383     /** The total number of cycles blocked for each blocked cause. */
 384     Stats::Vector blocked_cycles;
 385     /** The number of times this cache blocked for each blocked cause. */
 386     Stats::Vector blocked_causes;
 387
 388     /** The average number of cycles blocked for each blocked cause. */
 389     Stats::Formula avg_blocked;
 390
 391     /** The number of fast writes (WH64) performed. */
 392     Stats::Scalar fastWrites;
 393
 394     /** The number of cache copies performed. */
 395     Stats::Scalar cacheCopies;
 396
 397     /** Number of blocks written back per thread. */
 398     Stats::Vector writebacks;
 399
 400     /** Number of misses that hit in the MSHRs per command and thread. */
 401     Stats::Vector mshr_hits[MemCmd::NUM_MEM_CMDS];
 402     /** Demand misses that hit in the MSHRs. */
 403     Stats::Formula demandMshrHits;
 404     /** Total number of misses that hit in the MSHRs. */
 405     Stats::Formula overallMshrHits;
 406
 407     /** Number of misses that miss in the MSHRs, per command and thread. */
 408     Stats::Vector mshr_misses[MemCmd::NUM_MEM_CMDS];
 409     /** Demand misses that miss in the MSHRs. */
 410     Stats::Formula demandMshrMisses;
 411     /** Total number of misses that miss in the MSHRs. */
 412     Stats::Formula overallMshrMisses;
 413
 414     /** Number of misses that miss in the MSHRs, per command and thread. */
 415     Stats::Vector mshr_uncacheable[MemCmd::NUM_MEM_CMDS];
 416     /** Total number of misses that miss in the MSHRs. */
 417     Stats::Formula overallMshrUncacheable;
 418
 419     /** Total cycle latency of each MSHR miss, per command and thread. */
 420     Stats::Vector mshr_miss_latency[MemCmd::NUM_MEM_CMDS];
 421     /** Total cycle latency of demand MSHR misses. */
 422     Stats::Formula demandMshrMissLatency;
 423     /** Total cycle latency of overall MSHR misses. */
 424     Stats::Formula overallMshrMissLatency;
 425
 426     /** Total cycle latency of each MSHR miss, per command and thread. */
 427     Stats::Vector mshr_uncacheable_lat[MemCmd::NUM_MEM_CMDS];
 428     /** Total cycle latency of overall MSHR misses. */
 429     Stats::Formula overallMshrUncacheableLatency;
 430
 431 #if 0
 432     /** The total number of MSHR accesses per command and thread. */
 433     Stats::Formula mshrAccesses[MemCmd::NUM_MEM_CMDS];
 434     /** The total number of demand MSHR accesses. */
 435     Stats::Formula demandMshrAccesses;
 436     /** The total number of MSHR accesses. */
 437     Stats::Formula overallMshrAccesses;
 438 #endif
 439
 440     /** The miss rate in the MSHRs pre command and thread. */
 441     Stats::Formula mshrMissRate[MemCmd::NUM_MEM_CMDS];
 442     /** The demand miss rate in the MSHRs. */
 443     Stats::Formula demandMshrMissRate;
 444     /** The overall miss rate in the MSHRs. */
 445     Stats::Formula overallMshrMissRate;
 446
 447     /** The average latency of an MSHR miss, per command and thread. */
 448     Stats::Formula avgMshrMissLatency[MemCmd::NUM_MEM_CMDS];
 449     /** The average latency of a demand MSHR miss. */
 450     Stats::Formula demandAvgMshrMissLatency;
 451     /** The average overall latency of an MSHR miss. */
 452     Stats::Formula overallAvgMshrMissLatency;
 453
 454     /** The average latency of an MSHR miss, per command and thread. */
 455     Stats::Formula avgMshrUncacheableLatency[MemCmd::NUM_MEM_CMDS];
 456     /** The average overall latency of an MSHR miss. */
 457     Stats::Formula overallAvgMshrUncacheableLatency;
 458
 459     /** The number of times a thread hit its MSHR cap. */
 460     Stats::Vector mshr_cap_events;
 461     /** The number of times software prefetches caused the MSHR to block. */
 462     Stats::Vector soft_prefetch_mshr_full;
 463
 464     Stats::Scalar mshr_no_allocate_misses;
 465
 466     /**
 467      * @}
 468      */
 469
 470     /**
 471      * Register stats for this object.
 472      */
 473     virtual void regStats();
 474
 475   public:
 476     BaseCache(const BaseCacheParams *p, unsigned blk_size);
 477     ~BaseCache() {}
 478
 479     virtual void init();
 480
 481     virtual BaseMasterPort &getMasterPort(const std::string &if_name,
 482                                           PortID idx = InvalidPortID);
 483     virtual BaseSlavePort &getSlavePort(const std::string &if_name,
 484                                         PortID idx = InvalidPortID);
 485
 486     /**
 487      * Query block size of a cache.
 488      * @return  The block size
 489      */
 490     unsigned
 491     getBlockSize() const
 492     {
 493         return blkSize;
 494     }
 495
 496
 497     Addr blockAlign(Addr addr) const { return (addr & ~(Addr(blkSize - 1))); }
 498
 499
 500     const AddrRangeList &getAddrRanges() const { return addrRanges; }
 501
 502     MSHR *allocateMissBuffer(PacketPtr pkt, Tick time, bool sched_send = true)
 503     {
 504         return allocateBufferInternal(&mshrQueue,
 505                                       blockAlign(pkt->getAddr()), blkSize,
 506                                       pkt, time, sched_send);
 507     }
 508
 509     MSHR *allocateWriteBuffer(PacketPtr pkt, Tick time)
 510     {
 511         // should only see clean evictions in a read-only cache
 512         assert(!isReadOnly || pkt->cmd == MemCmd::CleanEvict);
 513         assert(pkt->isWrite() && !pkt->isRead());
 514         return allocateBufferInternal(&writeBuffer,
 515                                       blockAlign(pkt->getAddr()), blkSize,
 516                                       pkt, time, true);
 517     }
 518
 519     /**
 520      * Returns true if the cache is blocked for accesses.
 521      */
 522     bool isBlocked() const
 523     {
 524         return blocked != 0;
 525     }
 526
 527     /**
 528      * Marks the access path of the cache as blocked for the given cause. This
 529      * also sets the blocked flag in the slave interface.
 530      * @param cause The reason for the cache blocking.
 531      */
 532     void setBlocked(BlockedCause cause)
 533     {
 534         uint8_t flag = 1 << cause;
 535         if (blocked == 0) {
 536             blocked_causes[cause]++;
 537             blockedCycle = curCycle();
 538             cpuSidePort->setBlocked();
 539         }
 540         blocked |= flag;
 541         DPRINTF(Cache,"Blocking for cause %d, mask=%d\n", cause, blocked);
 542     }
 543
 544     /**
 545      * Marks the cache as unblocked for the given cause. This also clears the
 546      * blocked flags in the appropriate interfaces.
 547      * @param cause The newly unblocked cause.
 548      * @warning Calling this function can cause a blocked request on the bus to
 549      * access the cache. The cache must be in a state to handle that request.
 550      */
 551     void clearBlocked(BlockedCause cause)
 552     {
 553         uint8_t flag = 1 << cause;
 554         blocked &= ~flag;
 555         DPRINTF(Cache,"Unblocking for cause %d, mask=%d\n", cause, blocked);
 556         if (blocked == 0) {
 557             blocked_cycles[cause] += curCycle() - blockedCycle;
 558             cpuSidePort->clearBlocked();
 559         }
 560     }
 561
 562     /**
 563      * Schedule a send event for the memory-side port. If already
 564      * scheduled, this may reschedule the event at an earlier
 565      * time. When the specified time is reached, the port is free to
 566      * send either a response, a request, or a prefetch request.
 567      *
 568      * @param time The time when to attempt sending a packet.
 569      */
 570     void schedMemSideSendEvent(Tick time)
 571     {
 572         memSidePort->schedSendEvent(time);
 573     }
 574
 575     virtual bool inCache(Addr addr, bool is_secure) const = 0;
 576
 577     virtual bool inMissQueue(Addr addr, bool is_secure) const = 0;
 578
 579     void incMissCount(PacketPtr pkt)
 580     {
 581         assert(pkt->req->masterId() < system->maxMasters());
 582         misses[pkt->cmdToIndex()][pkt->req->masterId()]++;
 583         pkt->req->incAccessDepth();
 584         if (missCount) {
 585             --missCount;
 586             if (missCount == 0)
 587                 exitSimLoop("A cache reached the maximum miss count");
 588         }
 589     }
 590     void incHitCount(PacketPtr pkt)
 591     {
 592         assert(pkt->req->masterId() < system->maxMasters());
 593         hits[pkt->cmdToIndex()][pkt->req->masterId()]++;
 594
 595     }
 596
 597 };
 598
 599 #endif //__MEM_CACHE_BASE_HH__