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40 * Authors: Erik Hallnor
49 * Declares a basic cache interface BaseCache.
52 #ifndef __MEM_CACHE_BASE_HH__
53 #define __MEM_CACHE_BASE_HH__
59 #include "base/addr_range.hh"
60 #include "base/statistics.hh"
61 #include "base/trace.hh"
62 #include "base/types.hh"
63 #include "debug/Cache.hh"
64 #include "debug/CachePort.hh"
65 #include "enums/Clusivity.hh"
66 #include "mem/cache/cache_blk.hh"
67 #include "mem/cache/mshr_queue.hh"
68 #include "mem/cache/tags/base.hh"
69 #include "mem/cache/write_queue.hh"
70 #include "mem/cache/write_queue_entry.hh"
71 #include "mem/mem_object.hh"
72 #include "mem/packet.hh"
73 #include "mem/packet_queue.hh"
74 #include "mem/qport.hh"
75 #include "mem/request.hh"
76 #include "sim/eventq.hh"
77 #include "sim/serialize.hh"
78 #include "sim/sim_exit.hh"
79 #include "sim/system.hh"
87 struct BaseCacheParams;
90 * A basic cache interface. Implements some common functions for speed.
92 class BaseCache : public MemObject
96 * Indexes to enumerate the MSHR queues.
100 MSHRQueue_WriteBuffer
105 * Reasons for caches to be blocked.
108 Blocked_NoMSHRs = MSHRQueue_MSHRs,
109 Blocked_NoWBBuffers = MSHRQueue_WriteBuffer,
117 * A cache master port is used for the memory-side port of the
118 * cache, and in addition to the basic timing port that only sends
119 * response packets through a transmit list, it also offers the
120 * ability to schedule and send request packets (requests &
121 * writebacks). The send event is scheduled through schedSendEvent,
122 * and the sendDeferredPacket of the timing port is modified to
123 * consider both the transmit list and the requests from the MSHR.
125 class CacheMasterPort : public QueuedMasterPort
131 * Schedule a send of a request packet (from the MSHR). Note
132 * that we could already have a retry outstanding.
134 void schedSendEvent(Tick time)
136 DPRINTF(CachePort, "Scheduling send event at %llu\n", time);
137 reqQueue.schedSendEvent(time);
142 CacheMasterPort(const std::string &_name, BaseCache *_cache,
143 ReqPacketQueue &_reqQueue,
144 SnoopRespPacketQueue &_snoopRespQueue) :
145 QueuedMasterPort(_name, _cache, _reqQueue, _snoopRespQueue)
149 * Memory-side port always snoops.
151 * @return always true
153 virtual bool isSnooping() const { return true; }
157 * Override the default behaviour of sendDeferredPacket to enable
158 * the memory-side cache port to also send requests based on the
159 * current MSHR status. This queue has a pointer to our specific
160 * cache implementation and is used by the MemSidePort.
162 class CacheReqPacketQueue : public ReqPacketQueue
168 SnoopRespPacketQueue &snoopRespQueue;
172 CacheReqPacketQueue(BaseCache &cache, MasterPort &port,
173 SnoopRespPacketQueue &snoop_resp_queue,
174 const std::string &label) :
175 ReqPacketQueue(cache, port, label), cache(cache),
176 snoopRespQueue(snoop_resp_queue) { }
179 * Override the normal sendDeferredPacket and do not only
180 * consider the transmit list (used for responses), but also
183 virtual void sendDeferredPacket();
186 * Check if there is a conflicting snoop response about to be
187 * send out, and if so simply stall any requests, and schedule
188 * a send event at the same time as the next snoop response is
191 bool checkConflictingSnoop(Addr addr)
193 if (snoopRespQueue.hasAddr(addr)) {
194 DPRINTF(CachePort, "Waiting for snoop response to be "
196 Tick when = snoopRespQueue.deferredPacketReadyTime();
197 schedSendEvent(when);
206 * The memory-side port extends the base cache master port with
207 * access functions for functional, atomic and timing snoops.
209 class MemSidePort : public CacheMasterPort
213 /** The cache-specific queue. */
214 CacheReqPacketQueue _reqQueue;
216 SnoopRespPacketQueue _snoopRespQueue;
218 // a pointer to our specific cache implementation
223 virtual void recvTimingSnoopReq(PacketPtr pkt);
225 virtual bool recvTimingResp(PacketPtr pkt);
227 virtual Tick recvAtomicSnoop(PacketPtr pkt);
229 virtual void recvFunctionalSnoop(PacketPtr pkt);
233 MemSidePort(const std::string &_name, BaseCache *_cache,
234 const std::string &_label);
238 * A cache slave port is used for the CPU-side port of the cache,
239 * and it is basically a simple timing port that uses a transmit
240 * list for responses to the CPU (or connected master). In
241 * addition, it has the functionality to block the port for
242 * incoming requests. If blocked, the port will issue a retry once
245 class CacheSlavePort : public QueuedSlavePort
250 /** Do not accept any new requests. */
253 /** Return to normal operation and accept new requests. */
256 bool isBlocked() const { return blocked; }
260 CacheSlavePort(const std::string &_name, BaseCache *_cache,
261 const std::string &_label);
263 /** A normal packet queue used to store responses. */
264 RespPacketQueue queue;
272 void processSendRetry();
274 EventFunctionWrapper sendRetryEvent;
279 * The CPU-side port extends the base cache slave port with access
280 * functions for functional, atomic and timing requests.
282 class CpuSidePort : public CacheSlavePort
286 // a pointer to our specific cache implementation
290 virtual bool recvTimingSnoopResp(PacketPtr pkt) override;
292 virtual bool tryTiming(PacketPtr pkt) override;
294 virtual bool recvTimingReq(PacketPtr pkt) override;
296 virtual Tick recvAtomic(PacketPtr pkt) override;
298 virtual void recvFunctional(PacketPtr pkt) override;
300 virtual AddrRangeList getAddrRanges() const override;
304 CpuSidePort(const std::string &_name, BaseCache *_cache,
305 const std::string &_label);
309 CpuSidePort cpuSidePort;
310 MemSidePort memSidePort;
314 /** Miss status registers */
317 /** Write/writeback buffer */
318 WriteQueue writeBuffer;
320 /** Tag and data Storage */
324 BasePrefetcher *prefetcher;
327 * Notify the prefetcher on every access, not just misses.
329 const bool prefetchOnAccess;
332 * Temporary cache block for occasional transitory use. We use
333 * the tempBlock to fill when allocation fails (e.g., when there
334 * is an outstanding request that accesses the victim block) or
335 * when we want to avoid allocation (e.g., exclusive caches)
337 TempCacheBlk *tempBlock;
340 * Upstream caches need this packet until true is returned, so
341 * hold it for deletion until a subsequent call
343 std::unique_ptr<Packet> pendingDelete;
346 * Mark a request as in service (sent downstream in the memory
347 * system), effectively making this MSHR the ordering point.
349 void markInService(MSHR *mshr, bool pending_modified_resp)
351 bool wasFull = mshrQueue.isFull();
352 mshrQueue.markInService(mshr, pending_modified_resp);
354 if (wasFull && !mshrQueue.isFull()) {
355 clearBlocked(Blocked_NoMSHRs);
359 void markInService(WriteQueueEntry *entry)
361 bool wasFull = writeBuffer.isFull();
362 writeBuffer.markInService(entry);
364 if (wasFull && !writeBuffer.isFull()) {
365 clearBlocked(Blocked_NoWBBuffers);
370 * Determine whether we should allocate on a fill or not. If this
371 * cache is mostly inclusive with regards to the upstream cache(s)
372 * we always allocate (for any non-forwarded and cacheable
373 * requests). In the case of a mostly exclusive cache, we allocate
374 * on fill if the packet did not come from a cache, thus if we:
375 * are dealing with a whole-line write (the latter behaves much
376 * like a writeback), the original target packet came from a
377 * non-caching source, or if we are performing a prefetch or LLSC.
379 * @param cmd Command of the incoming requesting packet
380 * @return Whether we should allocate on the fill
382 inline bool allocOnFill(MemCmd cmd) const
384 return clusivity == Enums::mostly_incl ||
385 cmd == MemCmd::WriteLineReq ||
386 cmd == MemCmd::ReadReq ||
387 cmd == MemCmd::WriteReq ||
393 * Regenerate block address using tags.
394 * Block address regeneration depends on whether we're using a temporary
397 * @param blk The block to regenerate address.
398 * @return The block's address.
400 Addr regenerateBlkAddr(CacheBlk* blk);
403 * Does all the processing necessary to perform the provided request.
404 * @param pkt The memory request to perform.
405 * @param blk The cache block to be updated.
406 * @param lat The latency of the access.
407 * @param writebacks List for any writebacks that need to be performed.
408 * @return Boolean indicating whether the request was satisfied.
410 virtual bool access(PacketPtr pkt, CacheBlk *&blk, Cycles &lat,
411 PacketList &writebacks);
414 * Handle a timing request that hit in the cache
416 * @param ptk The request packet
417 * @param blk The referenced block
418 * @param request_time The tick at which the block lookup is compete
420 virtual void handleTimingReqHit(PacketPtr pkt, CacheBlk *blk,
424 * Handle a timing request that missed in the cache
426 * Implementation specific handling for different cache
429 * @param ptk The request packet
430 * @param blk The referenced block
431 * @param forward_time The tick at which we can process dependent requests
432 * @param request_time The tick at which the block lookup is compete
434 virtual void handleTimingReqMiss(PacketPtr pkt, CacheBlk *blk,
436 Tick request_time) = 0;
439 * Handle a timing request that missed in the cache
441 * Common functionality across different cache implementations
443 * @param ptk The request packet
444 * @param blk The referenced block
445 * @param mshr Any existing mshr for the referenced cache block
446 * @param forward_time The tick at which we can process dependent requests
447 * @param request_time The tick at which the block lookup is compete
449 void handleTimingReqMiss(PacketPtr pkt, MSHR *mshr, CacheBlk *blk,
450 Tick forward_time, Tick request_time);
453 * Performs the access specified by the request.
454 * @param pkt The request to perform.
456 virtual void recvTimingReq(PacketPtr pkt);
459 * Handling the special case of uncacheable write responses to
460 * make recvTimingResp less cluttered.
462 void handleUncacheableWriteResp(PacketPtr pkt);
465 * Service non-deferred MSHR targets using the received response
467 * Iterates through the list of targets that can be serviced with
468 * the current response. Any writebacks that need to performed
469 * must be appended to the writebacks parameter.
471 * @param mshr The MSHR that corresponds to the reponse
472 * @param pkt The response packet
473 * @param blk The reference block
474 * @param writebacks List of writebacks that need to be performed
476 virtual void serviceMSHRTargets(MSHR *mshr, const PacketPtr pkt,
477 CacheBlk *blk, PacketList& writebacks) = 0;
480 * Handles a response (cache line fill/write ack) from the bus.
481 * @param pkt The response packet
483 virtual void recvTimingResp(PacketPtr pkt);
486 * Snoops bus transactions to maintain coherence.
487 * @param pkt The current bus transaction.
489 virtual void recvTimingSnoopReq(PacketPtr pkt) = 0;
492 * Handle a snoop response.
493 * @param pkt Snoop response packet
495 virtual void recvTimingSnoopResp(PacketPtr pkt) = 0;
498 * Handle a request in atomic mode that missed in this cache
500 * Creates a downstream request, sends it to the memory below and
501 * handles the response. As we are in atomic mode all operations
502 * are performed immediately.
504 * @param pkt The packet with the requests
505 * @param blk The referenced block
506 * @param writebacks A list with packets for any performed writebacks
507 * @return Cycles for handling the request
509 virtual Cycles handleAtomicReqMiss(PacketPtr pkt, CacheBlk *&blk,
510 PacketList &writebacks) = 0;
513 * Performs the access specified by the request.
514 * @param pkt The request to perform.
515 * @return The number of ticks required for the access.
517 virtual Tick recvAtomic(PacketPtr pkt);
520 * Snoop for the provided request in the cache and return the estimated
522 * @param pkt The memory request to snoop
523 * @return The number of ticks required for the snoop.
525 virtual Tick recvAtomicSnoop(PacketPtr pkt) = 0;
528 * Performs the access specified by the request.
530 * @param pkt The request to perform.
531 * @param fromCpuSide from the CPU side port or the memory side port
533 virtual void functionalAccess(PacketPtr pkt, bool from_cpu_side);
536 * Handle doing the Compare and Swap function for SPARC.
538 void cmpAndSwap(CacheBlk *blk, PacketPtr pkt);
541 * Return the next queue entry to service, either a pending miss
542 * from the MSHR queue, a buffered write from the write buffer, or
543 * something from the prefetcher. This function is responsible
544 * for prioritizing among those sources on the fly.
546 QueueEntry* getNextQueueEntry();
549 * Insert writebacks into the write buffer
551 virtual void doWritebacks(PacketList& writebacks, Tick forward_time) = 0;
554 * Send writebacks down the memory hierarchy in atomic mode
556 virtual void doWritebacksAtomic(PacketList& writebacks) = 0;
559 * Create an appropriate downstream bus request packet.
561 * Creates a new packet with the request to be send to the memory
562 * below, or nullptr if the current request in cpu_pkt should just
565 * @param cpu_pkt The miss packet that needs to be satisfied.
566 * @param blk The referenced block, can be nullptr.
567 * @param needs_writable Indicates that the block must be writable
568 * even if the request in cpu_pkt doesn't indicate that.
569 * @param is_whole_line_write True if there are writes for the
571 * @return A packet send to the memory below
573 virtual PacketPtr createMissPacket(PacketPtr cpu_pkt, CacheBlk *blk,
575 bool is_whole_line_write) const = 0;
578 * Determine if clean lines should be written back or not. In
579 * cases where a downstream cache is mostly inclusive we likely
580 * want it to act as a victim cache also for lines that have not
581 * been modified. Hence, we cannot simply drop the line (or send a
582 * clean evict), but rather need to send the actual data.
584 const bool writebackClean;
587 * Writebacks from the tempBlock, resulting on the response path
588 * in atomic mode, must happen after the call to recvAtomic has
589 * finished (for the right ordering of the packets). We therefore
590 * need to hold on to the packets, and have a method and an event
593 PacketPtr tempBlockWriteback;
596 * Send the outstanding tempBlock writeback. To be called after
597 * recvAtomic finishes in cases where the block we filled is in
598 * fact the tempBlock, and now needs to be written back.
600 void writebackTempBlockAtomic() {
601 assert(tempBlockWriteback != nullptr);
602 PacketList writebacks{tempBlockWriteback};
603 doWritebacksAtomic(writebacks);
604 tempBlockWriteback = nullptr;
608 * An event to writeback the tempBlock after recvAtomic
609 * finishes. To avoid other calls to recvAtomic getting in
610 * between, we create this event with a higher priority.
612 EventFunctionWrapper writebackTempBlockAtomicEvent;
615 * Perform any necessary updates to the block and perform any data
616 * exchange between the packet and the block. The flags of the
617 * packet are also set accordingly.
619 * @param pkt Request packet from upstream that hit a block
620 * @param blk Cache block that the packet hit
621 * @param deferred_response Whether this request originally missed
622 * @param pending_downgrade Whether the writable flag is to be removed
624 virtual void satisfyRequest(PacketPtr pkt, CacheBlk *blk,
625 bool deferred_response = false,
626 bool pending_downgrade = false);
629 * Maintain the clusivity of this cache by potentially
630 * invalidating a block. This method works in conjunction with
631 * satisfyRequest, but is separate to allow us to handle all MSHR
632 * targets before potentially dropping a block.
634 * @param from_cache Whether we have dealt with a packet from a cache
635 * @param blk The block that should potentially be dropped
637 void maintainClusivity(bool from_cache, CacheBlk *blk);
640 * Handle a fill operation caused by a received packet.
642 * Populates a cache block and handles all outstanding requests for the
643 * satisfied fill request. This version takes two memory requests. One
644 * contains the fill data, the other is an optional target to satisfy.
645 * Note that the reason we return a list of writebacks rather than
646 * inserting them directly in the write buffer is that this function
647 * is called by both atomic and timing-mode accesses, and in atomic
648 * mode we don't mess with the write buffer (we just perform the
649 * writebacks atomically once the original request is complete).
651 * @param pkt The memory request with the fill data.
652 * @param blk The cache block if it already exists.
653 * @param writebacks List for any writebacks that need to be performed.
654 * @param allocate Whether to allocate a block or use the temp block
655 * @return Pointer to the new cache block.
657 CacheBlk *handleFill(PacketPtr pkt, CacheBlk *blk,
658 PacketList &writebacks, bool allocate);
661 * Allocate a new block and perform any necessary writebacks
663 * Find a victim block and if necessary prepare writebacks for any
664 * existing data. May return nullptr if there are no replaceable
665 * blocks. If a replaceable block is found, it inserts the new block in
666 * its place. The new block, however, is not set as valid yet.
668 * @param pkt Packet holding the address to update
669 * @param writebacks A list of writeback packets for the evicted blocks
670 * @return the allocated block
672 CacheBlk *allocateBlock(const PacketPtr pkt, PacketList &writebacks);
674 * Evict a cache block.
676 * Performs a writeback if necesssary and invalidates the block
678 * @param blk Block to invalidate
679 * @return A packet with the writeback, can be nullptr
681 M5_NODISCARD virtual PacketPtr evictBlock(CacheBlk *blk) = 0;
684 * Evict a cache block.
686 * Performs a writeback if necesssary and invalidates the block
688 * @param blk Block to invalidate
689 * @param writebacks Return a list of packets with writebacks
691 virtual void evictBlock(CacheBlk *blk, PacketList &writebacks) = 0;
694 * Invalidate a cache block.
696 * @param blk Block to invalidate
698 void invalidateBlock(CacheBlk *blk);
701 * Create a writeback request for the given block.
703 * @param blk The block to writeback.
704 * @return The writeback request for the block.
706 PacketPtr writebackBlk(CacheBlk *blk);
709 * Create a writeclean request for the given block.
711 * Creates a request that writes the block to the cache below
712 * without evicting the block from the current cache.
714 * @param blk The block to write clean.
715 * @param dest The destination of the write clean operation.
716 * @param id Use the given packet id for the write clean operation.
717 * @return The generated write clean packet.
719 PacketPtr writecleanBlk(CacheBlk *blk, Request::Flags dest, PacketId id);
722 * Write back dirty blocks in the cache using functional accesses.
724 virtual void memWriteback() override;
727 * Invalidates all blocks in the cache.
729 * @warn Dirty cache lines will not be written back to
730 * memory. Make sure to call functionalWriteback() first if you
731 * want the to write them to memory.
733 virtual void memInvalidate() override;
736 * Determine if there are any dirty blocks in the cache.
738 * @return true if at least one block is dirty, false otherwise.
740 bool isDirty() const;
743 * Determine if an address is in the ranges covered by this
744 * cache. This is useful to filter snoops.
746 * @param addr Address to check against
748 * @return If the address in question is in range
750 bool inRange(Addr addr) const;
753 * Find next request ready time from among possible sources.
755 Tick nextQueueReadyTime() const;
757 /** Block size of this cache */
758 const unsigned blkSize;
761 * The latency of tag lookup of a cache. It occurs when there is
762 * an access to the cache.
764 const Cycles lookupLatency;
767 * The latency of data access of a cache. It occurs when there is
768 * an access to the cache.
770 const Cycles dataLatency;
773 * This is the forward latency of the cache. It occurs when there
774 * is a cache miss and a request is forwarded downstream, in
775 * particular an outbound miss.
777 const Cycles forwardLatency;
779 /** The latency to fill a cache block */
780 const Cycles fillLatency;
783 * The latency of sending reponse to its upper level cache/core on
784 * a linefill. The responseLatency parameter captures this
787 const Cycles responseLatency;
789 /** The number of targets for each MSHR. */
792 /** Do we forward snoops from mem side port through to cpu side port? */
796 * Clusivity with respect to the upstream cache, determining if we
797 * fill into both this cache and the cache above on a miss. Note
798 * that we currently do not support strict clusivity policies.
800 const Enums::Clusivity clusivity;
803 * Is this cache read only, for example the instruction cache, or
804 * table-walker cache. A cache that is read only should never see
805 * any writes, and should never get any dirty data (and hence
806 * never have to do any writebacks).
808 const bool isReadOnly;
811 * Bit vector of the blocking reasons for the access path.
816 /** Increasing order number assigned to each incoming request. */
819 /** Stores time the cache blocked for statistics. */
822 /** Pointer to the MSHR that has no targets. */
825 /** The number of misses to trigger an exit event. */
829 * The address range to which the cache responds on the CPU side.
830 * Normally this is all possible memory addresses. */
831 const AddrRangeList addrRanges;
834 /** System we are currently operating in. */
839 * @addtogroup CacheStatistics
843 /** Number of hits per thread for each type of command.
844 @sa Packet::Command */
845 Stats::Vector hits[MemCmd::NUM_MEM_CMDS];
846 /** Number of hits for demand accesses. */
847 Stats::Formula demandHits;
848 /** Number of hit for all accesses. */
849 Stats::Formula overallHits;
851 /** Number of misses per thread for each type of command.
852 @sa Packet::Command */
853 Stats::Vector misses[MemCmd::NUM_MEM_CMDS];
854 /** Number of misses for demand accesses. */
855 Stats::Formula demandMisses;
856 /** Number of misses for all accesses. */
857 Stats::Formula overallMisses;
860 * Total number of cycles per thread/command spent waiting for a miss.
861 * Used to calculate the average miss latency.
863 Stats::Vector missLatency[MemCmd::NUM_MEM_CMDS];
864 /** Total number of cycles spent waiting for demand misses. */
865 Stats::Formula demandMissLatency;
866 /** Total number of cycles spent waiting for all misses. */
867 Stats::Formula overallMissLatency;
869 /** The number of accesses per command and thread. */
870 Stats::Formula accesses[MemCmd::NUM_MEM_CMDS];
871 /** The number of demand accesses. */
872 Stats::Formula demandAccesses;
873 /** The number of overall accesses. */
874 Stats::Formula overallAccesses;
876 /** The miss rate per command and thread. */
877 Stats::Formula missRate[MemCmd::NUM_MEM_CMDS];
878 /** The miss rate of all demand accesses. */
879 Stats::Formula demandMissRate;
880 /** The miss rate for all accesses. */
881 Stats::Formula overallMissRate;
883 /** The average miss latency per command and thread. */
884 Stats::Formula avgMissLatency[MemCmd::NUM_MEM_CMDS];
885 /** The average miss latency for demand misses. */
886 Stats::Formula demandAvgMissLatency;
887 /** The average miss latency for all misses. */
888 Stats::Formula overallAvgMissLatency;
890 /** The total number of cycles blocked for each blocked cause. */
891 Stats::Vector blocked_cycles;
892 /** The number of times this cache blocked for each blocked cause. */
893 Stats::Vector blocked_causes;
895 /** The average number of cycles blocked for each blocked cause. */
896 Stats::Formula avg_blocked;
898 /** The number of times a HW-prefetched block is evicted w/o reference. */
899 Stats::Scalar unusedPrefetches;
901 /** Number of blocks written back per thread. */
902 Stats::Vector writebacks;
904 /** Number of misses that hit in the MSHRs per command and thread. */
905 Stats::Vector mshr_hits[MemCmd::NUM_MEM_CMDS];
906 /** Demand misses that hit in the MSHRs. */
907 Stats::Formula demandMshrHits;
908 /** Total number of misses that hit in the MSHRs. */
909 Stats::Formula overallMshrHits;
911 /** Number of misses that miss in the MSHRs, per command and thread. */
912 Stats::Vector mshr_misses[MemCmd::NUM_MEM_CMDS];
913 /** Demand misses that miss in the MSHRs. */
914 Stats::Formula demandMshrMisses;
915 /** Total number of misses that miss in the MSHRs. */
916 Stats::Formula overallMshrMisses;
918 /** Number of misses that miss in the MSHRs, per command and thread. */
919 Stats::Vector mshr_uncacheable[MemCmd::NUM_MEM_CMDS];
920 /** Total number of misses that miss in the MSHRs. */
921 Stats::Formula overallMshrUncacheable;
923 /** Total cycle latency of each MSHR miss, per command and thread. */
924 Stats::Vector mshr_miss_latency[MemCmd::NUM_MEM_CMDS];
925 /** Total cycle latency of demand MSHR misses. */
926 Stats::Formula demandMshrMissLatency;
927 /** Total cycle latency of overall MSHR misses. */
928 Stats::Formula overallMshrMissLatency;
930 /** Total cycle latency of each MSHR miss, per command and thread. */
931 Stats::Vector mshr_uncacheable_lat[MemCmd::NUM_MEM_CMDS];
932 /** Total cycle latency of overall MSHR misses. */
933 Stats::Formula overallMshrUncacheableLatency;
936 /** The total number of MSHR accesses per command and thread. */
937 Stats::Formula mshrAccesses[MemCmd::NUM_MEM_CMDS];
938 /** The total number of demand MSHR accesses. */
939 Stats::Formula demandMshrAccesses;
940 /** The total number of MSHR accesses. */
941 Stats::Formula overallMshrAccesses;
944 /** The miss rate in the MSHRs pre command and thread. */
945 Stats::Formula mshrMissRate[MemCmd::NUM_MEM_CMDS];
946 /** The demand miss rate in the MSHRs. */
947 Stats::Formula demandMshrMissRate;
948 /** The overall miss rate in the MSHRs. */
949 Stats::Formula overallMshrMissRate;
951 /** The average latency of an MSHR miss, per command and thread. */
952 Stats::Formula avgMshrMissLatency[MemCmd::NUM_MEM_CMDS];
953 /** The average latency of a demand MSHR miss. */
954 Stats::Formula demandAvgMshrMissLatency;
955 /** The average overall latency of an MSHR miss. */
956 Stats::Formula overallAvgMshrMissLatency;
958 /** The average latency of an MSHR miss, per command and thread. */
959 Stats::Formula avgMshrUncacheableLatency[MemCmd::NUM_MEM_CMDS];
960 /** The average overall latency of an MSHR miss. */
961 Stats::Formula overallAvgMshrUncacheableLatency;
963 /** Number of replacements of valid blocks. */
964 Stats::Scalar replacements;
971 * Register stats for this object.
973 void regStats() override;
976 BaseCache(const BaseCacheParams *p, unsigned blk_size);
979 void init() override;
981 BaseMasterPort &getMasterPort(const std::string &if_name,
982 PortID idx = InvalidPortID) override;
983 BaseSlavePort &getSlavePort(const std::string &if_name,
984 PortID idx = InvalidPortID) override;
987 * Query block size of a cache.
988 * @return The block size
996 const AddrRangeList &getAddrRanges() const { return addrRanges; }
998 MSHR *allocateMissBuffer(PacketPtr pkt, Tick time, bool sched_send = true)
1000 MSHR *mshr = mshrQueue.allocate(pkt->getBlockAddr(blkSize), blkSize,
1002 allocOnFill(pkt->cmd));
1004 if (mshrQueue.isFull()) {
1005 setBlocked((BlockedCause)MSHRQueue_MSHRs);
1009 // schedule the send
1010 schedMemSideSendEvent(time);
1016 void allocateWriteBuffer(PacketPtr pkt, Tick time)
1018 // should only see writes or clean evicts here
1019 assert(pkt->isWrite() || pkt->cmd == MemCmd::CleanEvict);
1021 Addr blk_addr = pkt->getBlockAddr(blkSize);
1023 WriteQueueEntry *wq_entry =
1024 writeBuffer.findMatch(blk_addr, pkt->isSecure());
1025 if (wq_entry && !wq_entry->inService) {
1026 DPRINTF(Cache, "Potential to merge writeback %s", pkt->print());
1029 writeBuffer.allocate(blk_addr, blkSize, pkt, time, order++);
1031 if (writeBuffer.isFull()) {
1032 setBlocked((BlockedCause)MSHRQueue_WriteBuffer);
1035 // schedule the send
1036 schedMemSideSendEvent(time);
1040 * Returns true if the cache is blocked for accesses.
1042 bool isBlocked() const
1044 return blocked != 0;
1048 * Marks the access path of the cache as blocked for the given cause. This
1049 * also sets the blocked flag in the slave interface.
1050 * @param cause The reason for the cache blocking.
1052 void setBlocked(BlockedCause cause)
1054 uint8_t flag = 1 << cause;
1056 blocked_causes[cause]++;
1057 blockedCycle = curCycle();
1058 cpuSidePort.setBlocked();
1061 DPRINTF(Cache,"Blocking for cause %d, mask=%d\n", cause, blocked);
1065 * Marks the cache as unblocked for the given cause. This also clears the
1066 * blocked flags in the appropriate interfaces.
1067 * @param cause The newly unblocked cause.
1068 * @warning Calling this function can cause a blocked request on the bus to
1069 * access the cache. The cache must be in a state to handle that request.
1071 void clearBlocked(BlockedCause cause)
1073 uint8_t flag = 1 << cause;
1075 DPRINTF(Cache,"Unblocking for cause %d, mask=%d\n", cause, blocked);
1077 blocked_cycles[cause] += curCycle() - blockedCycle;
1078 cpuSidePort.clearBlocked();
1083 * Schedule a send event for the memory-side port. If already
1084 * scheduled, this may reschedule the event at an earlier
1085 * time. When the specified time is reached, the port is free to
1086 * send either a response, a request, or a prefetch request.
1088 * @param time The time when to attempt sending a packet.
1090 void schedMemSideSendEvent(Tick time)
1092 memSidePort.schedSendEvent(time);
1095 bool inCache(Addr addr, bool is_secure) const {
1096 return tags->findBlock(addr, is_secure);
1099 bool inMissQueue(Addr addr, bool is_secure) const {
1100 return mshrQueue.findMatch(addr, is_secure);
1103 void incMissCount(PacketPtr pkt)
1105 assert(pkt->req->masterId() < system->maxMasters());
1106 misses[pkt->cmdToIndex()][pkt->req->masterId()]++;
1107 pkt->req->incAccessDepth();
1111 exitSimLoop("A cache reached the maximum miss count");
1114 void incHitCount(PacketPtr pkt)
1116 assert(pkt->req->masterId() < system->maxMasters());
1117 hits[pkt->cmdToIndex()][pkt->req->masterId()]++;
1122 * Cache block visitor that writes back dirty cache blocks using
1123 * functional writes.
1125 void writebackVisitor(CacheBlk &blk);
1128 * Cache block visitor that invalidates all blocks in the cache.
1130 * @warn Dirty cache lines will not be written back to memory.
1132 void invalidateVisitor(CacheBlk &blk);
1135 * Take an MSHR, turn it into a suitable downstream packet, and
1136 * send it out. This construct allows a queue entry to choose a suitable
1137 * approach based on its type.
1139 * @param mshr The MSHR to turn into a packet and send
1140 * @return True if the port is waiting for a retry
1142 virtual bool sendMSHRQueuePacket(MSHR* mshr);
1145 * Similar to sendMSHR, but for a write-queue entry
1146 * instead. Create the packet, and send it, and if successful also
1147 * mark the entry in service.
1149 * @param wq_entry The write-queue entry to turn into a packet and send
1150 * @return True if the port is waiting for a retry
1152 bool sendWriteQueuePacket(WriteQueueEntry* wq_entry);
1155 * Serialize the state of the caches
1157 * We currently don't support checkpointing cache state, so this panics.
1159 void serialize(CheckpointOut &cp) const override;
1160 void unserialize(CheckpointIn &cp) override;
1164 #endif //__MEM_CACHE_BASE_HH__