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40 * Authors: Erik Hallnor
49 * Declares a basic cache interface BaseCache.
52 #ifndef __MEM_CACHE_BASE_HH__
53 #define __MEM_CACHE_BASE_HH__
59 #include "base/addr_range.hh"
60 #include "base/statistics.hh"
61 #include "base/trace.hh"
62 #include "base/types.hh"
63 #include "debug/Cache.hh"
64 #include "debug/CachePort.hh"
65 #include "enums/Clusivity.hh"
66 #include "mem/cache/cache_blk.hh"
67 #include "mem/cache/mshr_queue.hh"
68 #include "mem/cache/tags/base.hh"
69 #include "mem/cache/write_queue.hh"
70 #include "mem/cache/write_queue_entry.hh"
71 #include "mem/mem_object.hh"
72 #include "mem/packet.hh"
73 #include "mem/packet_queue.hh"
74 #include "mem/qport.hh"
75 #include "mem/request.hh"
76 #include "params/WriteAllocator.hh"
77 #include "sim/eventq.hh"
78 #include "sim/serialize.hh"
79 #include "sim/sim_exit.hh"
80 #include "sim/system.hh"
88 struct BaseCacheParams;
91 * A basic cache interface. Implements some common functions for speed.
93 class BaseCache : public MemObject
97 * Indexes to enumerate the MSHR queues.
101 MSHRQueue_WriteBuffer
106 * Reasons for caches to be blocked.
109 Blocked_NoMSHRs = MSHRQueue_MSHRs,
110 Blocked_NoWBBuffers = MSHRQueue_WriteBuffer,
118 * A cache master port is used for the memory-side port of the
119 * cache, and in addition to the basic timing port that only sends
120 * response packets through a transmit list, it also offers the
121 * ability to schedule and send request packets (requests &
122 * writebacks). The send event is scheduled through schedSendEvent,
123 * and the sendDeferredPacket of the timing port is modified to
124 * consider both the transmit list and the requests from the MSHR.
126 class CacheMasterPort : public QueuedMasterPort
132 * Schedule a send of a request packet (from the MSHR). Note
133 * that we could already have a retry outstanding.
135 void schedSendEvent(Tick time)
137 DPRINTF(CachePort, "Scheduling send event at %llu\n", time);
138 reqQueue.schedSendEvent(time);
143 CacheMasterPort(const std::string &_name, BaseCache *_cache,
144 ReqPacketQueue &_reqQueue,
145 SnoopRespPacketQueue &_snoopRespQueue) :
146 QueuedMasterPort(_name, _cache, _reqQueue, _snoopRespQueue)
150 * Memory-side port always snoops.
152 * @return always true
154 virtual bool isSnooping() const { return true; }
158 * Override the default behaviour of sendDeferredPacket to enable
159 * the memory-side cache port to also send requests based on the
160 * current MSHR status. This queue has a pointer to our specific
161 * cache implementation and is used by the MemSidePort.
163 class CacheReqPacketQueue : public ReqPacketQueue
169 SnoopRespPacketQueue &snoopRespQueue;
173 CacheReqPacketQueue(BaseCache &cache, MasterPort &port,
174 SnoopRespPacketQueue &snoop_resp_queue,
175 const std::string &label) :
176 ReqPacketQueue(cache, port, label), cache(cache),
177 snoopRespQueue(snoop_resp_queue) { }
180 * Override the normal sendDeferredPacket and do not only
181 * consider the transmit list (used for responses), but also
184 virtual void sendDeferredPacket();
187 * Check if there is a conflicting snoop response about to be
188 * send out, and if so simply stall any requests, and schedule
189 * a send event at the same time as the next snoop response is
192 bool checkConflictingSnoop(Addr addr)
194 if (snoopRespQueue.hasAddr(addr)) {
195 DPRINTF(CachePort, "Waiting for snoop response to be "
197 Tick when = snoopRespQueue.deferredPacketReadyTime();
198 schedSendEvent(when);
207 * The memory-side port extends the base cache master port with
208 * access functions for functional, atomic and timing snoops.
210 class MemSidePort : public CacheMasterPort
214 /** The cache-specific queue. */
215 CacheReqPacketQueue _reqQueue;
217 SnoopRespPacketQueue _snoopRespQueue;
219 // a pointer to our specific cache implementation
224 virtual void recvTimingSnoopReq(PacketPtr pkt);
226 virtual bool recvTimingResp(PacketPtr pkt);
228 virtual Tick recvAtomicSnoop(PacketPtr pkt);
230 virtual void recvFunctionalSnoop(PacketPtr pkt);
234 MemSidePort(const std::string &_name, BaseCache *_cache,
235 const std::string &_label);
239 * A cache slave port is used for the CPU-side port of the cache,
240 * and it is basically a simple timing port that uses a transmit
241 * list for responses to the CPU (or connected master). In
242 * addition, it has the functionality to block the port for
243 * incoming requests. If blocked, the port will issue a retry once
246 class CacheSlavePort : public QueuedSlavePort
251 /** Do not accept any new requests. */
254 /** Return to normal operation and accept new requests. */
257 bool isBlocked() const { return blocked; }
261 CacheSlavePort(const std::string &_name, BaseCache *_cache,
262 const std::string &_label);
264 /** A normal packet queue used to store responses. */
265 RespPacketQueue queue;
273 void processSendRetry();
275 EventFunctionWrapper sendRetryEvent;
280 * The CPU-side port extends the base cache slave port with access
281 * functions for functional, atomic and timing requests.
283 class CpuSidePort : public CacheSlavePort
287 // a pointer to our specific cache implementation
291 virtual bool recvTimingSnoopResp(PacketPtr pkt) override;
293 virtual bool tryTiming(PacketPtr pkt) override;
295 virtual bool recvTimingReq(PacketPtr pkt) override;
297 virtual Tick recvAtomic(PacketPtr pkt) override;
299 virtual void recvFunctional(PacketPtr pkt) override;
301 virtual AddrRangeList getAddrRanges() const override;
305 CpuSidePort(const std::string &_name, BaseCache *_cache,
306 const std::string &_label);
310 CpuSidePort cpuSidePort;
311 MemSidePort memSidePort;
315 /** Miss status registers */
318 /** Write/writeback buffer */
319 WriteQueue writeBuffer;
321 /** Tag and data Storage */
325 BasePrefetcher *prefetcher;
328 * Notify the prefetcher on every access, not just misses.
330 const bool prefetchOnAccess;
333 * The writeAllocator drive optimizations for streaming writes.
334 * It first determines whether a WriteReq MSHR should be delayed,
335 * thus ensuring that we wait longer in cases when we are write
336 * coalescing and allowing all the bytes of the line to be written
337 * before the MSHR packet is sent downstream. This works in unison
338 * with the tracking in the MSHR to check if the entire line is
339 * written. The write mode also affects the behaviour on filling
340 * any whole-line writes. Normally the cache allocates the line
341 * when receiving the InvalidateResp, but after seeing enough
342 * consecutive lines we switch to using the tempBlock, and thus
343 * end up not allocating the line, and instead turning the
344 * whole-line write into a writeback straight away.
346 WriteAllocator * const writeAllocator;
349 * Temporary cache block for occasional transitory use. We use
350 * the tempBlock to fill when allocation fails (e.g., when there
351 * is an outstanding request that accesses the victim block) or
352 * when we want to avoid allocation (e.g., exclusive caches)
354 TempCacheBlk *tempBlock;
357 * Upstream caches need this packet until true is returned, so
358 * hold it for deletion until a subsequent call
360 std::unique_ptr<Packet> pendingDelete;
363 * Mark a request as in service (sent downstream in the memory
364 * system), effectively making this MSHR the ordering point.
366 void markInService(MSHR *mshr, bool pending_modified_resp)
368 bool wasFull = mshrQueue.isFull();
369 mshrQueue.markInService(mshr, pending_modified_resp);
371 if (wasFull && !mshrQueue.isFull()) {
372 clearBlocked(Blocked_NoMSHRs);
376 void markInService(WriteQueueEntry *entry)
378 bool wasFull = writeBuffer.isFull();
379 writeBuffer.markInService(entry);
381 if (wasFull && !writeBuffer.isFull()) {
382 clearBlocked(Blocked_NoWBBuffers);
387 * Determine whether we should allocate on a fill or not. If this
388 * cache is mostly inclusive with regards to the upstream cache(s)
389 * we always allocate (for any non-forwarded and cacheable
390 * requests). In the case of a mostly exclusive cache, we allocate
391 * on fill if the packet did not come from a cache, thus if we:
392 * are dealing with a whole-line write (the latter behaves much
393 * like a writeback), the original target packet came from a
394 * non-caching source, or if we are performing a prefetch or LLSC.
396 * @param cmd Command of the incoming requesting packet
397 * @return Whether we should allocate on the fill
399 inline bool allocOnFill(MemCmd cmd) const
401 return clusivity == Enums::mostly_incl ||
402 cmd == MemCmd::WriteLineReq ||
403 cmd == MemCmd::ReadReq ||
404 cmd == MemCmd::WriteReq ||
410 * Regenerate block address using tags.
411 * Block address regeneration depends on whether we're using a temporary
414 * @param blk The block to regenerate address.
415 * @return The block's address.
417 Addr regenerateBlkAddr(CacheBlk* blk);
420 * Does all the processing necessary to perform the provided request.
421 * @param pkt The memory request to perform.
422 * @param blk The cache block to be updated.
423 * @param lat The latency of the access.
424 * @param writebacks List for any writebacks that need to be performed.
425 * @return Boolean indicating whether the request was satisfied.
427 virtual bool access(PacketPtr pkt, CacheBlk *&blk, Cycles &lat,
428 PacketList &writebacks);
431 * Handle a timing request that hit in the cache
433 * @param ptk The request packet
434 * @param blk The referenced block
435 * @param request_time The tick at which the block lookup is compete
437 virtual void handleTimingReqHit(PacketPtr pkt, CacheBlk *blk,
441 * Handle a timing request that missed in the cache
443 * Implementation specific handling for different cache
446 * @param ptk The request packet
447 * @param blk The referenced block
448 * @param forward_time The tick at which we can process dependent requests
449 * @param request_time The tick at which the block lookup is compete
451 virtual void handleTimingReqMiss(PacketPtr pkt, CacheBlk *blk,
453 Tick request_time) = 0;
456 * Handle a timing request that missed in the cache
458 * Common functionality across different cache implementations
460 * @param ptk The request packet
461 * @param blk The referenced block
462 * @param mshr Any existing mshr for the referenced cache block
463 * @param forward_time The tick at which we can process dependent requests
464 * @param request_time The tick at which the block lookup is compete
466 void handleTimingReqMiss(PacketPtr pkt, MSHR *mshr, CacheBlk *blk,
467 Tick forward_time, Tick request_time);
470 * Performs the access specified by the request.
471 * @param pkt The request to perform.
473 virtual void recvTimingReq(PacketPtr pkt);
476 * Handling the special case of uncacheable write responses to
477 * make recvTimingResp less cluttered.
479 void handleUncacheableWriteResp(PacketPtr pkt);
482 * Service non-deferred MSHR targets using the received response
484 * Iterates through the list of targets that can be serviced with
485 * the current response. Any writebacks that need to performed
486 * must be appended to the writebacks parameter.
488 * @param mshr The MSHR that corresponds to the reponse
489 * @param pkt The response packet
490 * @param blk The reference block
491 * @param writebacks List of writebacks that need to be performed
493 virtual void serviceMSHRTargets(MSHR *mshr, const PacketPtr pkt,
494 CacheBlk *blk, PacketList& writebacks) = 0;
497 * Handles a response (cache line fill/write ack) from the bus.
498 * @param pkt The response packet
500 virtual void recvTimingResp(PacketPtr pkt);
503 * Snoops bus transactions to maintain coherence.
504 * @param pkt The current bus transaction.
506 virtual void recvTimingSnoopReq(PacketPtr pkt) = 0;
509 * Handle a snoop response.
510 * @param pkt Snoop response packet
512 virtual void recvTimingSnoopResp(PacketPtr pkt) = 0;
515 * Handle a request in atomic mode that missed in this cache
517 * Creates a downstream request, sends it to the memory below and
518 * handles the response. As we are in atomic mode all operations
519 * are performed immediately.
521 * @param pkt The packet with the requests
522 * @param blk The referenced block
523 * @param writebacks A list with packets for any performed writebacks
524 * @return Cycles for handling the request
526 virtual Cycles handleAtomicReqMiss(PacketPtr pkt, CacheBlk *&blk,
527 PacketList &writebacks) = 0;
530 * Performs the access specified by the request.
531 * @param pkt The request to perform.
532 * @return The number of ticks required for the access.
534 virtual Tick recvAtomic(PacketPtr pkt);
537 * Snoop for the provided request in the cache and return the estimated
539 * @param pkt The memory request to snoop
540 * @return The number of ticks required for the snoop.
542 virtual Tick recvAtomicSnoop(PacketPtr pkt) = 0;
545 * Performs the access specified by the request.
547 * @param pkt The request to perform.
548 * @param fromCpuSide from the CPU side port or the memory side port
550 virtual void functionalAccess(PacketPtr pkt, bool from_cpu_side);
553 * Handle doing the Compare and Swap function for SPARC.
555 void cmpAndSwap(CacheBlk *blk, PacketPtr pkt);
558 * Return the next queue entry to service, either a pending miss
559 * from the MSHR queue, a buffered write from the write buffer, or
560 * something from the prefetcher. This function is responsible
561 * for prioritizing among those sources on the fly.
563 QueueEntry* getNextQueueEntry();
566 * Insert writebacks into the write buffer
568 virtual void doWritebacks(PacketList& writebacks, Tick forward_time) = 0;
571 * Send writebacks down the memory hierarchy in atomic mode
573 virtual void doWritebacksAtomic(PacketList& writebacks) = 0;
576 * Create an appropriate downstream bus request packet.
578 * Creates a new packet with the request to be send to the memory
579 * below, or nullptr if the current request in cpu_pkt should just
582 * @param cpu_pkt The miss packet that needs to be satisfied.
583 * @param blk The referenced block, can be nullptr.
584 * @param needs_writable Indicates that the block must be writable
585 * even if the request in cpu_pkt doesn't indicate that.
586 * @param is_whole_line_write True if there are writes for the
588 * @return A packet send to the memory below
590 virtual PacketPtr createMissPacket(PacketPtr cpu_pkt, CacheBlk *blk,
592 bool is_whole_line_write) const = 0;
595 * Determine if clean lines should be written back or not. In
596 * cases where a downstream cache is mostly inclusive we likely
597 * want it to act as a victim cache also for lines that have not
598 * been modified. Hence, we cannot simply drop the line (or send a
599 * clean evict), but rather need to send the actual data.
601 const bool writebackClean;
604 * Writebacks from the tempBlock, resulting on the response path
605 * in atomic mode, must happen after the call to recvAtomic has
606 * finished (for the right ordering of the packets). We therefore
607 * need to hold on to the packets, and have a method and an event
610 PacketPtr tempBlockWriteback;
613 * Send the outstanding tempBlock writeback. To be called after
614 * recvAtomic finishes in cases where the block we filled is in
615 * fact the tempBlock, and now needs to be written back.
617 void writebackTempBlockAtomic() {
618 assert(tempBlockWriteback != nullptr);
619 PacketList writebacks{tempBlockWriteback};
620 doWritebacksAtomic(writebacks);
621 tempBlockWriteback = nullptr;
625 * An event to writeback the tempBlock after recvAtomic
626 * finishes. To avoid other calls to recvAtomic getting in
627 * between, we create this event with a higher priority.
629 EventFunctionWrapper writebackTempBlockAtomicEvent;
632 * Perform any necessary updates to the block and perform any data
633 * exchange between the packet and the block. The flags of the
634 * packet are also set accordingly.
636 * @param pkt Request packet from upstream that hit a block
637 * @param blk Cache block that the packet hit
638 * @param deferred_response Whether this request originally missed
639 * @param pending_downgrade Whether the writable flag is to be removed
641 virtual void satisfyRequest(PacketPtr pkt, CacheBlk *blk,
642 bool deferred_response = false,
643 bool pending_downgrade = false);
646 * Maintain the clusivity of this cache by potentially
647 * invalidating a block. This method works in conjunction with
648 * satisfyRequest, but is separate to allow us to handle all MSHR
649 * targets before potentially dropping a block.
651 * @param from_cache Whether we have dealt with a packet from a cache
652 * @param blk The block that should potentially be dropped
654 void maintainClusivity(bool from_cache, CacheBlk *blk);
657 * Handle a fill operation caused by a received packet.
659 * Populates a cache block and handles all outstanding requests for the
660 * satisfied fill request. This version takes two memory requests. One
661 * contains the fill data, the other is an optional target to satisfy.
662 * Note that the reason we return a list of writebacks rather than
663 * inserting them directly in the write buffer is that this function
664 * is called by both atomic and timing-mode accesses, and in atomic
665 * mode we don't mess with the write buffer (we just perform the
666 * writebacks atomically once the original request is complete).
668 * @param pkt The memory request with the fill data.
669 * @param blk The cache block if it already exists.
670 * @param writebacks List for any writebacks that need to be performed.
671 * @param allocate Whether to allocate a block or use the temp block
672 * @return Pointer to the new cache block.
674 CacheBlk *handleFill(PacketPtr pkt, CacheBlk *blk,
675 PacketList &writebacks, bool allocate);
678 * Allocate a new block and perform any necessary writebacks
680 * Find a victim block and if necessary prepare writebacks for any
681 * existing data. May return nullptr if there are no replaceable
682 * blocks. If a replaceable block is found, it inserts the new block in
683 * its place. The new block, however, is not set as valid yet.
685 * @param pkt Packet holding the address to update
686 * @param writebacks A list of writeback packets for the evicted blocks
687 * @return the allocated block
689 CacheBlk *allocateBlock(const PacketPtr pkt, PacketList &writebacks);
691 * Evict a cache block.
693 * Performs a writeback if necesssary and invalidates the block
695 * @param blk Block to invalidate
696 * @return A packet with the writeback, can be nullptr
698 M5_NODISCARD virtual PacketPtr evictBlock(CacheBlk *blk) = 0;
701 * Evict a cache block.
703 * Performs a writeback if necesssary and invalidates the block
705 * @param blk Block to invalidate
706 * @param writebacks Return a list of packets with writebacks
708 void evictBlock(CacheBlk *blk, PacketList &writebacks);
711 * Invalidate a cache block.
713 * @param blk Block to invalidate
715 void invalidateBlock(CacheBlk *blk);
718 * Create a writeback request for the given block.
720 * @param blk The block to writeback.
721 * @return The writeback request for the block.
723 PacketPtr writebackBlk(CacheBlk *blk);
726 * Create a writeclean request for the given block.
728 * Creates a request that writes the block to the cache below
729 * without evicting the block from the current cache.
731 * @param blk The block to write clean.
732 * @param dest The destination of the write clean operation.
733 * @param id Use the given packet id for the write clean operation.
734 * @return The generated write clean packet.
736 PacketPtr writecleanBlk(CacheBlk *blk, Request::Flags dest, PacketId id);
739 * Write back dirty blocks in the cache using functional accesses.
741 virtual void memWriteback() override;
744 * Invalidates all blocks in the cache.
746 * @warn Dirty cache lines will not be written back to
747 * memory. Make sure to call functionalWriteback() first if you
748 * want the to write them to memory.
750 virtual void memInvalidate() override;
753 * Determine if there are any dirty blocks in the cache.
755 * @return true if at least one block is dirty, false otherwise.
757 bool isDirty() const;
760 * Determine if an address is in the ranges covered by this
761 * cache. This is useful to filter snoops.
763 * @param addr Address to check against
765 * @return If the address in question is in range
767 bool inRange(Addr addr) const;
770 * Find next request ready time from among possible sources.
772 Tick nextQueueReadyTime() const;
774 /** Block size of this cache */
775 const unsigned blkSize;
778 * The latency of tag lookup of a cache. It occurs when there is
779 * an access to the cache.
781 const Cycles lookupLatency;
784 * The latency of data access of a cache. It occurs when there is
785 * an access to the cache.
787 const Cycles dataLatency;
790 * This is the forward latency of the cache. It occurs when there
791 * is a cache miss and a request is forwarded downstream, in
792 * particular an outbound miss.
794 const Cycles forwardLatency;
796 /** The latency to fill a cache block */
797 const Cycles fillLatency;
800 * The latency of sending reponse to its upper level cache/core on
801 * a linefill. The responseLatency parameter captures this
804 const Cycles responseLatency;
806 /** The number of targets for each MSHR. */
809 /** Do we forward snoops from mem side port through to cpu side port? */
813 * Clusivity with respect to the upstream cache, determining if we
814 * fill into both this cache and the cache above on a miss. Note
815 * that we currently do not support strict clusivity policies.
817 const Enums::Clusivity clusivity;
820 * Is this cache read only, for example the instruction cache, or
821 * table-walker cache. A cache that is read only should never see
822 * any writes, and should never get any dirty data (and hence
823 * never have to do any writebacks).
825 const bool isReadOnly;
828 * Bit vector of the blocking reasons for the access path.
833 /** Increasing order number assigned to each incoming request. */
836 /** Stores time the cache blocked for statistics. */
839 /** Pointer to the MSHR that has no targets. */
842 /** The number of misses to trigger an exit event. */
846 * The address range to which the cache responds on the CPU side.
847 * Normally this is all possible memory addresses. */
848 const AddrRangeList addrRanges;
851 /** System we are currently operating in. */
856 * @addtogroup CacheStatistics
860 /** Number of hits per thread for each type of command.
861 @sa Packet::Command */
862 Stats::Vector hits[MemCmd::NUM_MEM_CMDS];
863 /** Number of hits for demand accesses. */
864 Stats::Formula demandHits;
865 /** Number of hit for all accesses. */
866 Stats::Formula overallHits;
868 /** Number of misses per thread for each type of command.
869 @sa Packet::Command */
870 Stats::Vector misses[MemCmd::NUM_MEM_CMDS];
871 /** Number of misses for demand accesses. */
872 Stats::Formula demandMisses;
873 /** Number of misses for all accesses. */
874 Stats::Formula overallMisses;
877 * Total number of cycles per thread/command spent waiting for a miss.
878 * Used to calculate the average miss latency.
880 Stats::Vector missLatency[MemCmd::NUM_MEM_CMDS];
881 /** Total number of cycles spent waiting for demand misses. */
882 Stats::Formula demandMissLatency;
883 /** Total number of cycles spent waiting for all misses. */
884 Stats::Formula overallMissLatency;
886 /** The number of accesses per command and thread. */
887 Stats::Formula accesses[MemCmd::NUM_MEM_CMDS];
888 /** The number of demand accesses. */
889 Stats::Formula demandAccesses;
890 /** The number of overall accesses. */
891 Stats::Formula overallAccesses;
893 /** The miss rate per command and thread. */
894 Stats::Formula missRate[MemCmd::NUM_MEM_CMDS];
895 /** The miss rate of all demand accesses. */
896 Stats::Formula demandMissRate;
897 /** The miss rate for all accesses. */
898 Stats::Formula overallMissRate;
900 /** The average miss latency per command and thread. */
901 Stats::Formula avgMissLatency[MemCmd::NUM_MEM_CMDS];
902 /** The average miss latency for demand misses. */
903 Stats::Formula demandAvgMissLatency;
904 /** The average miss latency for all misses. */
905 Stats::Formula overallAvgMissLatency;
907 /** The total number of cycles blocked for each blocked cause. */
908 Stats::Vector blocked_cycles;
909 /** The number of times this cache blocked for each blocked cause. */
910 Stats::Vector blocked_causes;
912 /** The average number of cycles blocked for each blocked cause. */
913 Stats::Formula avg_blocked;
915 /** The number of times a HW-prefetched block is evicted w/o reference. */
916 Stats::Scalar unusedPrefetches;
918 /** Number of blocks written back per thread. */
919 Stats::Vector writebacks;
921 /** Number of misses that hit in the MSHRs per command and thread. */
922 Stats::Vector mshr_hits[MemCmd::NUM_MEM_CMDS];
923 /** Demand misses that hit in the MSHRs. */
924 Stats::Formula demandMshrHits;
925 /** Total number of misses that hit in the MSHRs. */
926 Stats::Formula overallMshrHits;
928 /** Number of misses that miss in the MSHRs, per command and thread. */
929 Stats::Vector mshr_misses[MemCmd::NUM_MEM_CMDS];
930 /** Demand misses that miss in the MSHRs. */
931 Stats::Formula demandMshrMisses;
932 /** Total number of misses that miss in the MSHRs. */
933 Stats::Formula overallMshrMisses;
935 /** Number of misses that miss in the MSHRs, per command and thread. */
936 Stats::Vector mshr_uncacheable[MemCmd::NUM_MEM_CMDS];
937 /** Total number of misses that miss in the MSHRs. */
938 Stats::Formula overallMshrUncacheable;
940 /** Total cycle latency of each MSHR miss, per command and thread. */
941 Stats::Vector mshr_miss_latency[MemCmd::NUM_MEM_CMDS];
942 /** Total cycle latency of demand MSHR misses. */
943 Stats::Formula demandMshrMissLatency;
944 /** Total cycle latency of overall MSHR misses. */
945 Stats::Formula overallMshrMissLatency;
947 /** Total cycle latency of each MSHR miss, per command and thread. */
948 Stats::Vector mshr_uncacheable_lat[MemCmd::NUM_MEM_CMDS];
949 /** Total cycle latency of overall MSHR misses. */
950 Stats::Formula overallMshrUncacheableLatency;
953 /** The total number of MSHR accesses per command and thread. */
954 Stats::Formula mshrAccesses[MemCmd::NUM_MEM_CMDS];
955 /** The total number of demand MSHR accesses. */
956 Stats::Formula demandMshrAccesses;
957 /** The total number of MSHR accesses. */
958 Stats::Formula overallMshrAccesses;
961 /** The miss rate in the MSHRs pre command and thread. */
962 Stats::Formula mshrMissRate[MemCmd::NUM_MEM_CMDS];
963 /** The demand miss rate in the MSHRs. */
964 Stats::Formula demandMshrMissRate;
965 /** The overall miss rate in the MSHRs. */
966 Stats::Formula overallMshrMissRate;
968 /** The average latency of an MSHR miss, per command and thread. */
969 Stats::Formula avgMshrMissLatency[MemCmd::NUM_MEM_CMDS];
970 /** The average latency of a demand MSHR miss. */
971 Stats::Formula demandAvgMshrMissLatency;
972 /** The average overall latency of an MSHR miss. */
973 Stats::Formula overallAvgMshrMissLatency;
975 /** The average latency of an MSHR miss, per command and thread. */
976 Stats::Formula avgMshrUncacheableLatency[MemCmd::NUM_MEM_CMDS];
977 /** The average overall latency of an MSHR miss. */
978 Stats::Formula overallAvgMshrUncacheableLatency;
980 /** Number of replacements of valid blocks. */
981 Stats::Scalar replacements;
988 * Register stats for this object.
990 void regStats() override;
993 BaseCache(const BaseCacheParams *p, unsigned blk_size);
996 void init() override;
998 BaseMasterPort &getMasterPort(const std::string &if_name,
999 PortID idx = InvalidPortID) override;
1000 BaseSlavePort &getSlavePort(const std::string &if_name,
1001 PortID idx = InvalidPortID) override;
1004 * Query block size of a cache.
1005 * @return The block size
1008 getBlockSize() const
1013 const AddrRangeList &getAddrRanges() const { return addrRanges; }
1015 MSHR *allocateMissBuffer(PacketPtr pkt, Tick time, bool sched_send = true)
1017 MSHR *mshr = mshrQueue.allocate(pkt->getBlockAddr(blkSize), blkSize,
1019 allocOnFill(pkt->cmd));
1021 if (mshrQueue.isFull()) {
1022 setBlocked((BlockedCause)MSHRQueue_MSHRs);
1026 // schedule the send
1027 schedMemSideSendEvent(time);
1033 void allocateWriteBuffer(PacketPtr pkt, Tick time)
1035 // should only see writes or clean evicts here
1036 assert(pkt->isWrite() || pkt->cmd == MemCmd::CleanEvict);
1038 Addr blk_addr = pkt->getBlockAddr(blkSize);
1040 WriteQueueEntry *wq_entry =
1041 writeBuffer.findMatch(blk_addr, pkt->isSecure());
1042 if (wq_entry && !wq_entry->inService) {
1043 DPRINTF(Cache, "Potential to merge writeback %s", pkt->print());
1046 writeBuffer.allocate(blk_addr, blkSize, pkt, time, order++);
1048 if (writeBuffer.isFull()) {
1049 setBlocked((BlockedCause)MSHRQueue_WriteBuffer);
1052 // schedule the send
1053 schedMemSideSendEvent(time);
1057 * Returns true if the cache is blocked for accesses.
1059 bool isBlocked() const
1061 return blocked != 0;
1065 * Marks the access path of the cache as blocked for the given cause. This
1066 * also sets the blocked flag in the slave interface.
1067 * @param cause The reason for the cache blocking.
1069 void setBlocked(BlockedCause cause)
1071 uint8_t flag = 1 << cause;
1073 blocked_causes[cause]++;
1074 blockedCycle = curCycle();
1075 cpuSidePort.setBlocked();
1078 DPRINTF(Cache,"Blocking for cause %d, mask=%d\n", cause, blocked);
1082 * Marks the cache as unblocked for the given cause. This also clears the
1083 * blocked flags in the appropriate interfaces.
1084 * @param cause The newly unblocked cause.
1085 * @warning Calling this function can cause a blocked request on the bus to
1086 * access the cache. The cache must be in a state to handle that request.
1088 void clearBlocked(BlockedCause cause)
1090 uint8_t flag = 1 << cause;
1092 DPRINTF(Cache,"Unblocking for cause %d, mask=%d\n", cause, blocked);
1094 blocked_cycles[cause] += curCycle() - blockedCycle;
1095 cpuSidePort.clearBlocked();
1100 * Schedule a send event for the memory-side port. If already
1101 * scheduled, this may reschedule the event at an earlier
1102 * time. When the specified time is reached, the port is free to
1103 * send either a response, a request, or a prefetch request.
1105 * @param time The time when to attempt sending a packet.
1107 void schedMemSideSendEvent(Tick time)
1109 memSidePort.schedSendEvent(time);
1112 bool inCache(Addr addr, bool is_secure) const {
1113 return tags->findBlock(addr, is_secure);
1116 bool inMissQueue(Addr addr, bool is_secure) const {
1117 return mshrQueue.findMatch(addr, is_secure);
1120 void incMissCount(PacketPtr pkt)
1122 assert(pkt->req->masterId() < system->maxMasters());
1123 misses[pkt->cmdToIndex()][pkt->req->masterId()]++;
1124 pkt->req->incAccessDepth();
1128 exitSimLoop("A cache reached the maximum miss count");
1131 void incHitCount(PacketPtr pkt)
1133 assert(pkt->req->masterId() < system->maxMasters());
1134 hits[pkt->cmdToIndex()][pkt->req->masterId()]++;
1139 * Cache block visitor that writes back dirty cache blocks using
1140 * functional writes.
1142 void writebackVisitor(CacheBlk &blk);
1145 * Cache block visitor that invalidates all blocks in the cache.
1147 * @warn Dirty cache lines will not be written back to memory.
1149 void invalidateVisitor(CacheBlk &blk);
1152 * Take an MSHR, turn it into a suitable downstream packet, and
1153 * send it out. This construct allows a queue entry to choose a suitable
1154 * approach based on its type.
1156 * @param mshr The MSHR to turn into a packet and send
1157 * @return True if the port is waiting for a retry
1159 virtual bool sendMSHRQueuePacket(MSHR* mshr);
1162 * Similar to sendMSHR, but for a write-queue entry
1163 * instead. Create the packet, and send it, and if successful also
1164 * mark the entry in service.
1166 * @param wq_entry The write-queue entry to turn into a packet and send
1167 * @return True if the port is waiting for a retry
1169 bool sendWriteQueuePacket(WriteQueueEntry* wq_entry);
1172 * Serialize the state of the caches
1174 * We currently don't support checkpointing cache state, so this panics.
1176 void serialize(CheckpointOut &cp) const override;
1177 void unserialize(CheckpointIn &cp) override;
1182 * The write allocator inspects write packets and detects streaming
1183 * patterns. The write allocator supports a single stream where writes
1184 * are expected to access consecutive locations and keeps track of
1185 * size of the area covered by the concecutive writes in byteCount.
1187 * 1) When byteCount has surpassed the coallesceLimit the mode
1188 * switches from ALLOCATE to COALESCE where writes should be delayed
1189 * until the whole block is written at which point a single packet
1190 * (whole line write) can service them.
1192 * 2) When byteCount has also exceeded the noAllocateLimit (whole
1193 * line) we switch to NO_ALLOCATE when writes should not allocate in
1194 * the cache but rather send a whole line write to the memory below.
1196 class WriteAllocator : public SimObject {
1198 WriteAllocator(const WriteAllocatorParams *p) :
1200 coalesceLimit(p->coalesce_limit * p->block_size),
1201 noAllocateLimit(p->no_allocate_limit * p->block_size),
1202 delayThreshold(p->delay_threshold)
1208 * Should writes be coalesced? This is true if the mode is set to
1211 * @return return true if the cache should coalesce writes.
1213 bool coalesce() const {
1214 return mode != WriteMode::ALLOCATE;
1218 * Should writes allocate?
1220 * @return return true if the cache should not allocate for writes.
1222 bool allocate() const {
1223 return mode != WriteMode::NO_ALLOCATE;
1227 * Reset the write allocator state, meaning that it allocates for
1228 * writes and has not recorded any information about qualifying
1229 * writes that might trigger a switch to coalescing and later no
1233 mode = WriteMode::ALLOCATE;
1239 * Access whether we need to delay the current write.
1241 * @param blk_addr The block address the packet writes to
1242 * @return true if the current packet should be delayed
1244 bool delay(Addr blk_addr) {
1245 if (delayCtr[blk_addr] > 0) {
1246 --delayCtr[blk_addr];
1254 * Clear delay counter for the input block
1256 * @param blk_addr The accessed cache block
1258 void resetDelay(Addr blk_addr) {
1259 delayCtr.erase(blk_addr);
1263 * Update the write mode based on the current write
1264 * packet. This method compares the packet's address with any
1265 * current stream, and updates the tracking and the mode
1268 * @param write_addr Start address of the write request
1269 * @param write_size Size of the write request
1270 * @param blk_addr The block address that this packet writes to
1272 void updateMode(Addr write_addr, unsigned write_size, Addr blk_addr);
1276 * The current mode for write coalescing and allocation, either
1277 * normal operation (ALLOCATE), write coalescing (COALESCE), or
1278 * write coalescing without allocation (NO_ALLOCATE).
1280 enum class WriteMode : char {
1287 /** Address to match writes against to detect streams. */
1291 * Bytes written contiguously. Saturating once we no longer
1297 * Limits for when to switch between the different write modes.
1299 const uint32_t coalesceLimit;
1300 const uint32_t noAllocateLimit;
1302 * The number of times the allocator will delay an WriteReq MSHR.
1304 const uint32_t delayThreshold;
1307 * Keep track of the number of times the allocator has delayed an
1310 std::unordered_map<Addr, Counter> delayCtr;
1313 #endif //__MEM_CACHE_BASE_HH__