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40 * Authors: Erik Hallnor
47 * Declares a basic cache interface BaseCache.
50 #ifndef __BASE_CACHE_HH__
51 #define __BASE_CACHE_HH__
58 #include "base/misc.hh"
59 #include "base/statistics.hh"
60 #include "base/trace.hh"
61 #include "base/types.hh"
62 #include "debug/Cache.hh"
63 #include "debug/CachePort.hh"
64 #include "mem/cache/mshr_queue.hh"
65 #include "mem/mem_object.hh"
66 #include "mem/packet.hh"
67 #include "mem/qport.hh"
68 #include "mem/request.hh"
69 #include "params/BaseCache.hh"
70 #include "sim/eventq.hh"
71 #include "sim/full_system.hh"
72 #include "sim/sim_exit.hh"
73 #include "sim/system.hh"
77 * A basic cache interface. Implements some common functions for speed.
79 class BaseCache : public MemObject
82 * Indexes to enumerate the MSHR queues.
91 * Reasons for caches to be blocked.
94 Blocked_NoMSHRs = MSHRQueue_MSHRs,
95 Blocked_NoWBBuffers = MSHRQueue_WriteBuffer,
101 * Reasons for cache to request a bus.
104 Request_MSHR = MSHRQueue_MSHRs,
105 Request_WB = MSHRQueue_WriteBuffer,
113 * A cache master port is used for the memory-side port of the
114 * cache, and in addition to the basic timing port that only sends
115 * response packets through a transmit list, it also offers the
116 * ability to schedule and send request packets (requests &
117 * writebacks). The send event is scheduled through requestBus,
118 * and the sendDeferredPacket of the timing port is modified to
119 * consider both the transmit list and the requests from the MSHR.
121 class CacheMasterPort : public QueuedMasterPort
127 * Schedule a send of a request packet (from the MSHR). Note
128 * that we could already have a retry or a transmit list of
129 * responses outstanding.
131 void requestBus(RequestCause cause, Tick time)
133 DPRINTF(CachePort, "Asserting bus request for cause %d\n", cause);
134 queue.schedSendEvent(time);
138 * Schedule the transmissions of a response packet at a given
141 * @param pkt response packet
142 * @param when time to send the response
144 void respond(PacketPtr pkt, Tick time) {
145 queue.schedSendTiming(pkt, time, true);
150 CacheMasterPort(const std::string &_name, BaseCache *_cache,
151 MasterPacketQueue &_queue) :
152 QueuedMasterPort(_name, _cache, _queue)
156 * Memory-side port always snoops.
158 * @return always true
160 virtual bool isSnooping() const { return true; }
164 * A cache slave port is used for the CPU-side port of the cache,
165 * and it is basically a simple timing port that uses a transmit
166 * list for responses to the CPU (or connected master). In
167 * addition, it has the functionality to block the port for
168 * incoming requests. If blocked, the port will issue a retry once
171 class CacheSlavePort : public QueuedSlavePort
176 /** Do not accept any new requests. */
179 /** Return to normal operation and accept new requests. */
183 * Schedule the transmissions of a response packet at a given
186 * @param pkt response packet
187 * @param when time to send the response
189 void respond(PacketPtr pkt, Tick time) {
190 queue.schedSendTiming(pkt, time);
195 CacheSlavePort(const std::string &_name, BaseCache *_cache,
196 const std::string &_label);
198 /** A normal packet queue used to store responses. */
199 SlavePacketQueue queue;
207 EventWrapper<SlavePort, &SlavePort::sendRetry> sendRetryEvent;
211 CacheSlavePort *cpuSidePort;
212 CacheMasterPort *memSidePort;
216 /** Miss status registers */
219 /** Write/writeback buffer */
220 MSHRQueue writeBuffer;
222 MSHR *allocateBufferInternal(MSHRQueue *mq, Addr addr, int size,
223 PacketPtr pkt, Tick time, bool requestBus)
225 MSHR *mshr = mq->allocate(addr, size, pkt, time, order++);
228 setBlocked((BlockedCause)mq->index);
232 requestMemSideBus((RequestCause)mq->index, time);
238 void markInServiceInternal(MSHR *mshr, PacketPtr pkt)
240 MSHRQueue *mq = mshr->queue;
241 bool wasFull = mq->isFull();
242 mq->markInService(mshr, pkt);
243 if (wasFull && !mq->isFull()) {
244 clearBlocked((BlockedCause)mq->index);
248 /** Block size of this cache */
249 const unsigned blkSize;
252 * The latency of a hit in this device.
256 /** The number of targets for each MSHR. */
259 /** Do we forward snoops from mem side port through to cpu side port? */
262 /** Is this cache a toplevel cache (e.g. L1, I/O cache). If so we should
263 * never try to forward ownership and similar optimizations to the cpu
268 * Bit vector of the blocking reasons for the access path.
273 /** Increasing order number assigned to each incoming request. */
276 /** Stores time the cache blocked for statistics. */
279 /** Pointer to the MSHR that has no targets. */
282 /** The number of misses to trigger an exit event. */
285 /** The drain event. */
289 * The address range to which the cache responds on the CPU side.
290 * Normally this is all possible memory addresses. */
291 AddrRangeList addrRanges;
294 /** System we are currently operating in. */
299 * @addtogroup CacheStatistics
303 /** Number of hits per thread for each type of command. @sa Packet::Command */
304 Stats::Vector hits[MemCmd::NUM_MEM_CMDS];
305 /** Number of hits for demand accesses. */
306 Stats::Formula demandHits;
307 /** Number of hit for all accesses. */
308 Stats::Formula overallHits;
310 /** Number of misses per thread for each type of command. @sa Packet::Command */
311 Stats::Vector misses[MemCmd::NUM_MEM_CMDS];
312 /** Number of misses for demand accesses. */
313 Stats::Formula demandMisses;
314 /** Number of misses for all accesses. */
315 Stats::Formula overallMisses;
318 * Total number of cycles per thread/command spent waiting for a miss.
319 * Used to calculate the average miss latency.
321 Stats::Vector missLatency[MemCmd::NUM_MEM_CMDS];
322 /** Total number of cycles spent waiting for demand misses. */
323 Stats::Formula demandMissLatency;
324 /** Total number of cycles spent waiting for all misses. */
325 Stats::Formula overallMissLatency;
327 /** The number of accesses per command and thread. */
328 Stats::Formula accesses[MemCmd::NUM_MEM_CMDS];
329 /** The number of demand accesses. */
330 Stats::Formula demandAccesses;
331 /** The number of overall accesses. */
332 Stats::Formula overallAccesses;
334 /** The miss rate per command and thread. */
335 Stats::Formula missRate[MemCmd::NUM_MEM_CMDS];
336 /** The miss rate of all demand accesses. */
337 Stats::Formula demandMissRate;
338 /** The miss rate for all accesses. */
339 Stats::Formula overallMissRate;
341 /** The average miss latency per command and thread. */
342 Stats::Formula avgMissLatency[MemCmd::NUM_MEM_CMDS];
343 /** The average miss latency for demand misses. */
344 Stats::Formula demandAvgMissLatency;
345 /** The average miss latency for all misses. */
346 Stats::Formula overallAvgMissLatency;
348 /** The total number of cycles blocked for each blocked cause. */
349 Stats::Vector blocked_cycles;
350 /** The number of times this cache blocked for each blocked cause. */
351 Stats::Vector blocked_causes;
353 /** The average number of cycles blocked for each blocked cause. */
354 Stats::Formula avg_blocked;
356 /** The number of fast writes (WH64) performed. */
357 Stats::Scalar fastWrites;
359 /** The number of cache copies performed. */
360 Stats::Scalar cacheCopies;
362 /** Number of blocks written back per thread. */
363 Stats::Vector writebacks;
365 /** Number of misses that hit in the MSHRs per command and thread. */
366 Stats::Vector mshr_hits[MemCmd::NUM_MEM_CMDS];
367 /** Demand misses that hit in the MSHRs. */
368 Stats::Formula demandMshrHits;
369 /** Total number of misses that hit in the MSHRs. */
370 Stats::Formula overallMshrHits;
372 /** Number of misses that miss in the MSHRs, per command and thread. */
373 Stats::Vector mshr_misses[MemCmd::NUM_MEM_CMDS];
374 /** Demand misses that miss in the MSHRs. */
375 Stats::Formula demandMshrMisses;
376 /** Total number of misses that miss in the MSHRs. */
377 Stats::Formula overallMshrMisses;
379 /** Number of misses that miss in the MSHRs, per command and thread. */
380 Stats::Vector mshr_uncacheable[MemCmd::NUM_MEM_CMDS];
381 /** Total number of misses that miss in the MSHRs. */
382 Stats::Formula overallMshrUncacheable;
384 /** Total cycle latency of each MSHR miss, per command and thread. */
385 Stats::Vector mshr_miss_latency[MemCmd::NUM_MEM_CMDS];
386 /** Total cycle latency of demand MSHR misses. */
387 Stats::Formula demandMshrMissLatency;
388 /** Total cycle latency of overall MSHR misses. */
389 Stats::Formula overallMshrMissLatency;
391 /** Total cycle latency of each MSHR miss, per command and thread. */
392 Stats::Vector mshr_uncacheable_lat[MemCmd::NUM_MEM_CMDS];
393 /** Total cycle latency of overall MSHR misses. */
394 Stats::Formula overallMshrUncacheableLatency;
397 /** The total number of MSHR accesses per command and thread. */
398 Stats::Formula mshrAccesses[MemCmd::NUM_MEM_CMDS];
399 /** The total number of demand MSHR accesses. */
400 Stats::Formula demandMshrAccesses;
401 /** The total number of MSHR accesses. */
402 Stats::Formula overallMshrAccesses;
405 /** The miss rate in the MSHRs pre command and thread. */
406 Stats::Formula mshrMissRate[MemCmd::NUM_MEM_CMDS];
407 /** The demand miss rate in the MSHRs. */
408 Stats::Formula demandMshrMissRate;
409 /** The overall miss rate in the MSHRs. */
410 Stats::Formula overallMshrMissRate;
412 /** The average latency of an MSHR miss, per command and thread. */
413 Stats::Formula avgMshrMissLatency[MemCmd::NUM_MEM_CMDS];
414 /** The average latency of a demand MSHR miss. */
415 Stats::Formula demandAvgMshrMissLatency;
416 /** The average overall latency of an MSHR miss. */
417 Stats::Formula overallAvgMshrMissLatency;
419 /** The average latency of an MSHR miss, per command and thread. */
420 Stats::Formula avgMshrUncacheableLatency[MemCmd::NUM_MEM_CMDS];
421 /** The average overall latency of an MSHR miss. */
422 Stats::Formula overallAvgMshrUncacheableLatency;
424 /** The number of times a thread hit its MSHR cap. */
425 Stats::Vector mshr_cap_events;
426 /** The number of times software prefetches caused the MSHR to block. */
427 Stats::Vector soft_prefetch_mshr_full;
429 Stats::Scalar mshr_no_allocate_misses;
436 * Register stats for this object.
438 virtual void regStats();
441 typedef BaseCacheParams Params;
442 BaseCache(const Params *p);
447 virtual MasterPort &getMasterPort(const std::string &if_name, int idx = -1);
448 virtual SlavePort &getSlavePort(const std::string &if_name, int idx = -1);
451 * Query block size of a cache.
452 * @return The block size
461 Addr blockAlign(Addr addr) const { return (addr & ~(Addr(blkSize - 1))); }
464 const AddrRangeList &getAddrRanges() const { return addrRanges; }
466 MSHR *allocateMissBuffer(PacketPtr pkt, Tick time, bool requestBus)
468 assert(!pkt->req->isUncacheable());
469 return allocateBufferInternal(&mshrQueue,
470 blockAlign(pkt->getAddr()), blkSize,
471 pkt, time, requestBus);
474 MSHR *allocateWriteBuffer(PacketPtr pkt, Tick time, bool requestBus)
476 assert(pkt->isWrite() && !pkt->isRead());
477 return allocateBufferInternal(&writeBuffer,
478 pkt->getAddr(), pkt->getSize(),
479 pkt, time, requestBus);
482 MSHR *allocateUncachedReadBuffer(PacketPtr pkt, Tick time, bool requestBus)
484 assert(pkt->req->isUncacheable());
485 assert(pkt->isRead());
486 return allocateBufferInternal(&mshrQueue,
487 pkt->getAddr(), pkt->getSize(),
488 pkt, time, requestBus);
492 * Returns true if the cache is blocked for accesses.
500 * Marks the access path of the cache as blocked for the given cause. This
501 * also sets the blocked flag in the slave interface.
502 * @param cause The reason for the cache blocking.
504 void setBlocked(BlockedCause cause)
506 uint8_t flag = 1 << cause;
508 blocked_causes[cause]++;
509 blockedCycle = curTick();
510 cpuSidePort->setBlocked();
513 DPRINTF(Cache,"Blocking for cause %d, mask=%d\n", cause, blocked);
517 * Marks the cache as unblocked for the given cause. This also clears the
518 * blocked flags in the appropriate interfaces.
519 * @param cause The newly unblocked cause.
520 * @warning Calling this function can cause a blocked request on the bus to
521 * access the cache. The cache must be in a state to handle that request.
523 void clearBlocked(BlockedCause cause)
525 uint8_t flag = 1 << cause;
527 DPRINTF(Cache,"Unblocking for cause %d, mask=%d\n", cause, blocked);
529 blocked_cycles[cause] += curTick() - blockedCycle;
530 cpuSidePort->clearBlocked();
535 * Request the master bus for the given cause and time.
536 * @param cause The reason for the request.
537 * @param time The time to make the request.
539 void requestMemSideBus(RequestCause cause, Tick time)
541 memSidePort->requestBus(cause, time);
545 * Clear the master bus request for the given cause.
546 * @param cause The request reason to clear.
548 void deassertMemSideBusRequest(RequestCause cause)
550 // Obsolete... we no longer signal bus requests explicitly so
551 // we can't deassert them. Leaving this in as a no-op since
552 // the prefetcher calls it to indicate that it no longer wants
553 // to request a prefetch, and someday that might be
554 // interesting again.
557 virtual unsigned int drain(Event *de);
559 virtual bool inCache(Addr addr) = 0;
561 virtual bool inMissQueue(Addr addr) = 0;
563 void incMissCount(PacketPtr pkt)
565 assert(pkt->req->masterId() < system->maxMasters());
566 misses[pkt->cmdToIndex()][pkt->req->masterId()]++;
571 exitSimLoop("A cache reached the maximum miss count");
574 void incHitCount(PacketPtr pkt)
576 assert(pkt->req->masterId() < system->maxMasters());
577 hits[pkt->cmdToIndex()][pkt->req->masterId()]++;
583 #endif //__BASE_CACHE_HH__