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40 * Authors: Erik Hallnor
49 * Declares a basic cache interface BaseCache.
52 #ifndef __MEM_CACHE_BASE_HH__
53 #define __MEM_CACHE_BASE_HH__
59 #include "base/addr_range.hh"
60 #include "base/statistics.hh"
61 #include "base/trace.hh"
62 #include "base/types.hh"
63 #include "debug/Cache.hh"
64 #include "debug/CachePort.hh"
65 #include "enums/Clusivity.hh"
66 #include "mem/cache/cache_blk.hh"
67 #include "mem/cache/mshr_queue.hh"
68 #include "mem/cache/tags/base.hh"
69 #include "mem/cache/write_queue.hh"
70 #include "mem/cache/write_queue_entry.hh"
71 #include "mem/mem_object.hh"
72 #include "mem/packet.hh"
73 #include "mem/packet_queue.hh"
74 #include "mem/qport.hh"
75 #include "mem/request.hh"
76 #include "params/WriteAllocator.hh"
77 #include "sim/eventq.hh"
78 #include "sim/probe/probe.hh"
79 #include "sim/serialize.hh"
80 #include "sim/sim_exit.hh"
81 #include "sim/system.hh"
89 struct BaseCacheParams;
92 * A basic cache interface. Implements some common functions for speed.
94 class BaseCache : public MemObject
98 * Indexes to enumerate the MSHR queues.
100 enum MSHRQueueIndex {
102 MSHRQueue_WriteBuffer
107 * Reasons for caches to be blocked.
110 Blocked_NoMSHRs = MSHRQueue_MSHRs,
111 Blocked_NoWBBuffers = MSHRQueue_WriteBuffer,
119 * A cache master port is used for the memory-side port of the
120 * cache, and in addition to the basic timing port that only sends
121 * response packets through a transmit list, it also offers the
122 * ability to schedule and send request packets (requests &
123 * writebacks). The send event is scheduled through schedSendEvent,
124 * and the sendDeferredPacket of the timing port is modified to
125 * consider both the transmit list and the requests from the MSHR.
127 class CacheMasterPort : public QueuedMasterPort
133 * Schedule a send of a request packet (from the MSHR). Note
134 * that we could already have a retry outstanding.
136 void schedSendEvent(Tick time)
138 DPRINTF(CachePort, "Scheduling send event at %llu\n", time);
139 reqQueue.schedSendEvent(time);
144 CacheMasterPort(const std::string &_name, BaseCache *_cache,
145 ReqPacketQueue &_reqQueue,
146 SnoopRespPacketQueue &_snoopRespQueue) :
147 QueuedMasterPort(_name, _cache, _reqQueue, _snoopRespQueue)
151 * Memory-side port always snoops.
153 * @return always true
155 virtual bool isSnooping() const { return true; }
159 * Override the default behaviour of sendDeferredPacket to enable
160 * the memory-side cache port to also send requests based on the
161 * current MSHR status. This queue has a pointer to our specific
162 * cache implementation and is used by the MemSidePort.
164 class CacheReqPacketQueue : public ReqPacketQueue
170 SnoopRespPacketQueue &snoopRespQueue;
174 CacheReqPacketQueue(BaseCache &cache, MasterPort &port,
175 SnoopRespPacketQueue &snoop_resp_queue,
176 const std::string &label) :
177 ReqPacketQueue(cache, port, label), cache(cache),
178 snoopRespQueue(snoop_resp_queue) { }
181 * Override the normal sendDeferredPacket and do not only
182 * consider the transmit list (used for responses), but also
185 virtual void sendDeferredPacket();
188 * Check if there is a conflicting snoop response about to be
189 * send out, and if so simply stall any requests, and schedule
190 * a send event at the same time as the next snoop response is
193 * @param pkt The packet to check for conflicts against.
195 bool checkConflictingSnoop(const PacketPtr pkt)
197 if (snoopRespQueue.checkConflict(pkt, cache.blkSize)) {
198 DPRINTF(CachePort, "Waiting for snoop response to be "
200 Tick when = snoopRespQueue.deferredPacketReadyTime();
201 schedSendEvent(when);
210 * The memory-side port extends the base cache master port with
211 * access functions for functional, atomic and timing snoops.
213 class MemSidePort : public CacheMasterPort
217 /** The cache-specific queue. */
218 CacheReqPacketQueue _reqQueue;
220 SnoopRespPacketQueue _snoopRespQueue;
222 // a pointer to our specific cache implementation
227 virtual void recvTimingSnoopReq(PacketPtr pkt);
229 virtual bool recvTimingResp(PacketPtr pkt);
231 virtual Tick recvAtomicSnoop(PacketPtr pkt);
233 virtual void recvFunctionalSnoop(PacketPtr pkt);
237 MemSidePort(const std::string &_name, BaseCache *_cache,
238 const std::string &_label);
242 * A cache slave port is used for the CPU-side port of the cache,
243 * and it is basically a simple timing port that uses a transmit
244 * list for responses to the CPU (or connected master). In
245 * addition, it has the functionality to block the port for
246 * incoming requests. If blocked, the port will issue a retry once
249 class CacheSlavePort : public QueuedSlavePort
254 /** Do not accept any new requests. */
257 /** Return to normal operation and accept new requests. */
260 bool isBlocked() const { return blocked; }
264 CacheSlavePort(const std::string &_name, BaseCache *_cache,
265 const std::string &_label);
267 /** A normal packet queue used to store responses. */
268 RespPacketQueue queue;
276 void processSendRetry();
278 EventFunctionWrapper sendRetryEvent;
283 * The CPU-side port extends the base cache slave port with access
284 * functions for functional, atomic and timing requests.
286 class CpuSidePort : public CacheSlavePort
290 // a pointer to our specific cache implementation
294 virtual bool recvTimingSnoopResp(PacketPtr pkt) override;
296 virtual bool tryTiming(PacketPtr pkt) override;
298 virtual bool recvTimingReq(PacketPtr pkt) override;
300 virtual Tick recvAtomic(PacketPtr pkt) override;
302 virtual void recvFunctional(PacketPtr pkt) override;
304 virtual AddrRangeList getAddrRanges() const override;
308 CpuSidePort(const std::string &_name, BaseCache *_cache,
309 const std::string &_label);
313 CpuSidePort cpuSidePort;
314 MemSidePort memSidePort;
318 /** Miss status registers */
321 /** Write/writeback buffer */
322 WriteQueue writeBuffer;
324 /** Tag and data Storage */
328 BasePrefetcher *prefetcher;
330 /** To probe when a cache hit occurs */
331 ProbePointArg<PacketPtr> *ppHit;
333 /** To probe when a cache miss occurs */
334 ProbePointArg<PacketPtr> *ppMiss;
336 /** To probe when a cache fill occurs */
337 ProbePointArg<PacketPtr> *ppFill;
340 * The writeAllocator drive optimizations for streaming writes.
341 * It first determines whether a WriteReq MSHR should be delayed,
342 * thus ensuring that we wait longer in cases when we are write
343 * coalescing and allowing all the bytes of the line to be written
344 * before the MSHR packet is sent downstream. This works in unison
345 * with the tracking in the MSHR to check if the entire line is
346 * written. The write mode also affects the behaviour on filling
347 * any whole-line writes. Normally the cache allocates the line
348 * when receiving the InvalidateResp, but after seeing enough
349 * consecutive lines we switch to using the tempBlock, and thus
350 * end up not allocating the line, and instead turning the
351 * whole-line write into a writeback straight away.
353 WriteAllocator * const writeAllocator;
356 * Temporary cache block for occasional transitory use. We use
357 * the tempBlock to fill when allocation fails (e.g., when there
358 * is an outstanding request that accesses the victim block) or
359 * when we want to avoid allocation (e.g., exclusive caches)
361 TempCacheBlk *tempBlock;
364 * Upstream caches need this packet until true is returned, so
365 * hold it for deletion until a subsequent call
367 std::unique_ptr<Packet> pendingDelete;
370 * Mark a request as in service (sent downstream in the memory
371 * system), effectively making this MSHR the ordering point.
373 void markInService(MSHR *mshr, bool pending_modified_resp)
375 bool wasFull = mshrQueue.isFull();
376 mshrQueue.markInService(mshr, pending_modified_resp);
378 if (wasFull && !mshrQueue.isFull()) {
379 clearBlocked(Blocked_NoMSHRs);
383 void markInService(WriteQueueEntry *entry)
385 bool wasFull = writeBuffer.isFull();
386 writeBuffer.markInService(entry);
388 if (wasFull && !writeBuffer.isFull()) {
389 clearBlocked(Blocked_NoWBBuffers);
394 * Determine whether we should allocate on a fill or not. If this
395 * cache is mostly inclusive with regards to the upstream cache(s)
396 * we always allocate (for any non-forwarded and cacheable
397 * requests). In the case of a mostly exclusive cache, we allocate
398 * on fill if the packet did not come from a cache, thus if we:
399 * are dealing with a whole-line write (the latter behaves much
400 * like a writeback), the original target packet came from a
401 * non-caching source, or if we are performing a prefetch or LLSC.
403 * @param cmd Command of the incoming requesting packet
404 * @return Whether we should allocate on the fill
406 inline bool allocOnFill(MemCmd cmd) const
408 return clusivity == Enums::mostly_incl ||
409 cmd == MemCmd::WriteLineReq ||
410 cmd == MemCmd::ReadReq ||
411 cmd == MemCmd::WriteReq ||
417 * Regenerate block address using tags.
418 * Block address regeneration depends on whether we're using a temporary
421 * @param blk The block to regenerate address.
422 * @return The block's address.
424 Addr regenerateBlkAddr(CacheBlk* blk);
427 * Calculate latency of accesses that only touch the tag array.
428 * @sa calculateAccessLatency
430 * @param delay The delay until the packet's metadata is present.
431 * @param lookup_lat Latency of the respective tag lookup.
432 * @return The number of ticks that pass due to a tag-only access.
434 Cycles calculateTagOnlyLatency(const uint32_t delay,
435 const Cycles lookup_lat) const;
437 * Calculate access latency in ticks given a tag lookup latency, and
438 * whether access was a hit or miss.
440 * @param blk The cache block that was accessed.
441 * @param delay The delay until the packet's metadata is present.
442 * @param lookup_lat Latency of the respective tag lookup.
443 * @return The number of ticks that pass due to a block access.
445 Cycles calculateAccessLatency(const CacheBlk* blk, const uint32_t delay,
446 const Cycles lookup_lat) const;
449 * Does all the processing necessary to perform the provided request.
450 * @param pkt The memory request to perform.
451 * @param blk The cache block to be updated.
452 * @param lat The latency of the access.
453 * @param writebacks List for any writebacks that need to be performed.
454 * @return Boolean indicating whether the request was satisfied.
456 virtual bool access(PacketPtr pkt, CacheBlk *&blk, Cycles &lat,
457 PacketList &writebacks);
460 * Handle a timing request that hit in the cache
462 * @param ptk The request packet
463 * @param blk The referenced block
464 * @param request_time The tick at which the block lookup is compete
466 virtual void handleTimingReqHit(PacketPtr pkt, CacheBlk *blk,
470 * Handle a timing request that missed in the cache
472 * Implementation specific handling for different cache
475 * @param ptk The request packet
476 * @param blk The referenced block
477 * @param forward_time The tick at which we can process dependent requests
478 * @param request_time The tick at which the block lookup is compete
480 virtual void handleTimingReqMiss(PacketPtr pkt, CacheBlk *blk,
482 Tick request_time) = 0;
485 * Handle a timing request that missed in the cache
487 * Common functionality across different cache implementations
489 * @param ptk The request packet
490 * @param blk The referenced block
491 * @param mshr Any existing mshr for the referenced cache block
492 * @param forward_time The tick at which we can process dependent requests
493 * @param request_time The tick at which the block lookup is compete
495 void handleTimingReqMiss(PacketPtr pkt, MSHR *mshr, CacheBlk *blk,
496 Tick forward_time, Tick request_time);
499 * Performs the access specified by the request.
500 * @param pkt The request to perform.
502 virtual void recvTimingReq(PacketPtr pkt);
505 * Handling the special case of uncacheable write responses to
506 * make recvTimingResp less cluttered.
508 void handleUncacheableWriteResp(PacketPtr pkt);
511 * Service non-deferred MSHR targets using the received response
513 * Iterates through the list of targets that can be serviced with
514 * the current response.
516 * @param mshr The MSHR that corresponds to the reponse
517 * @param pkt The response packet
518 * @param blk The reference block
520 virtual void serviceMSHRTargets(MSHR *mshr, const PacketPtr pkt,
524 * Handles a response (cache line fill/write ack) from the bus.
525 * @param pkt The response packet
527 virtual void recvTimingResp(PacketPtr pkt);
530 * Snoops bus transactions to maintain coherence.
531 * @param pkt The current bus transaction.
533 virtual void recvTimingSnoopReq(PacketPtr pkt) = 0;
536 * Handle a snoop response.
537 * @param pkt Snoop response packet
539 virtual void recvTimingSnoopResp(PacketPtr pkt) = 0;
542 * Handle a request in atomic mode that missed in this cache
544 * Creates a downstream request, sends it to the memory below and
545 * handles the response. As we are in atomic mode all operations
546 * are performed immediately.
548 * @param pkt The packet with the requests
549 * @param blk The referenced block
550 * @param writebacks A list with packets for any performed writebacks
551 * @return Cycles for handling the request
553 virtual Cycles handleAtomicReqMiss(PacketPtr pkt, CacheBlk *&blk,
554 PacketList &writebacks) = 0;
557 * Performs the access specified by the request.
558 * @param pkt The request to perform.
559 * @return The number of ticks required for the access.
561 virtual Tick recvAtomic(PacketPtr pkt);
564 * Snoop for the provided request in the cache and return the estimated
566 * @param pkt The memory request to snoop
567 * @return The number of ticks required for the snoop.
569 virtual Tick recvAtomicSnoop(PacketPtr pkt) = 0;
572 * Performs the access specified by the request.
574 * @param pkt The request to perform.
575 * @param fromCpuSide from the CPU side port or the memory side port
577 virtual void functionalAccess(PacketPtr pkt, bool from_cpu_side);
580 * Handle doing the Compare and Swap function for SPARC.
582 void cmpAndSwap(CacheBlk *blk, PacketPtr pkt);
585 * Return the next queue entry to service, either a pending miss
586 * from the MSHR queue, a buffered write from the write buffer, or
587 * something from the prefetcher. This function is responsible
588 * for prioritizing among those sources on the fly.
590 QueueEntry* getNextQueueEntry();
593 * Insert writebacks into the write buffer
595 virtual void doWritebacks(PacketList& writebacks, Tick forward_time) = 0;
598 * Send writebacks down the memory hierarchy in atomic mode
600 virtual void doWritebacksAtomic(PacketList& writebacks) = 0;
603 * Create an appropriate downstream bus request packet.
605 * Creates a new packet with the request to be send to the memory
606 * below, or nullptr if the current request in cpu_pkt should just
609 * @param cpu_pkt The miss packet that needs to be satisfied.
610 * @param blk The referenced block, can be nullptr.
611 * @param needs_writable Indicates that the block must be writable
612 * even if the request in cpu_pkt doesn't indicate that.
613 * @param is_whole_line_write True if there are writes for the
615 * @return A packet send to the memory below
617 virtual PacketPtr createMissPacket(PacketPtr cpu_pkt, CacheBlk *blk,
619 bool is_whole_line_write) const = 0;
622 * Determine if clean lines should be written back or not. In
623 * cases where a downstream cache is mostly inclusive we likely
624 * want it to act as a victim cache also for lines that have not
625 * been modified. Hence, we cannot simply drop the line (or send a
626 * clean evict), but rather need to send the actual data.
628 const bool writebackClean;
631 * Writebacks from the tempBlock, resulting on the response path
632 * in atomic mode, must happen after the call to recvAtomic has
633 * finished (for the right ordering of the packets). We therefore
634 * need to hold on to the packets, and have a method and an event
637 PacketPtr tempBlockWriteback;
640 * Send the outstanding tempBlock writeback. To be called after
641 * recvAtomic finishes in cases where the block we filled is in
642 * fact the tempBlock, and now needs to be written back.
644 void writebackTempBlockAtomic() {
645 assert(tempBlockWriteback != nullptr);
646 PacketList writebacks{tempBlockWriteback};
647 doWritebacksAtomic(writebacks);
648 tempBlockWriteback = nullptr;
652 * An event to writeback the tempBlock after recvAtomic
653 * finishes. To avoid other calls to recvAtomic getting in
654 * between, we create this event with a higher priority.
656 EventFunctionWrapper writebackTempBlockAtomicEvent;
659 * Perform any necessary updates to the block and perform any data
660 * exchange between the packet and the block. The flags of the
661 * packet are also set accordingly.
663 * @param pkt Request packet from upstream that hit a block
664 * @param blk Cache block that the packet hit
665 * @param deferred_response Whether this request originally missed
666 * @param pending_downgrade Whether the writable flag is to be removed
668 virtual void satisfyRequest(PacketPtr pkt, CacheBlk *blk,
669 bool deferred_response = false,
670 bool pending_downgrade = false);
673 * Maintain the clusivity of this cache by potentially
674 * invalidating a block. This method works in conjunction with
675 * satisfyRequest, but is separate to allow us to handle all MSHR
676 * targets before potentially dropping a block.
678 * @param from_cache Whether we have dealt with a packet from a cache
679 * @param blk The block that should potentially be dropped
681 void maintainClusivity(bool from_cache, CacheBlk *blk);
684 * Handle a fill operation caused by a received packet.
686 * Populates a cache block and handles all outstanding requests for the
687 * satisfied fill request. This version takes two memory requests. One
688 * contains the fill data, the other is an optional target to satisfy.
689 * Note that the reason we return a list of writebacks rather than
690 * inserting them directly in the write buffer is that this function
691 * is called by both atomic and timing-mode accesses, and in atomic
692 * mode we don't mess with the write buffer (we just perform the
693 * writebacks atomically once the original request is complete).
695 * @param pkt The memory request with the fill data.
696 * @param blk The cache block if it already exists.
697 * @param writebacks List for any writebacks that need to be performed.
698 * @param allocate Whether to allocate a block or use the temp block
699 * @return Pointer to the new cache block.
701 CacheBlk *handleFill(PacketPtr pkt, CacheBlk *blk,
702 PacketList &writebacks, bool allocate);
705 * Allocate a new block and perform any necessary writebacks
707 * Find a victim block and if necessary prepare writebacks for any
708 * existing data. May return nullptr if there are no replaceable
709 * blocks. If a replaceable block is found, it inserts the new block in
710 * its place. The new block, however, is not set as valid yet.
712 * @param pkt Packet holding the address to update
713 * @param writebacks A list of writeback packets for the evicted blocks
714 * @return the allocated block
716 CacheBlk *allocateBlock(const PacketPtr pkt, PacketList &writebacks);
718 * Evict a cache block.
720 * Performs a writeback if necesssary and invalidates the block
722 * @param blk Block to invalidate
723 * @return A packet with the writeback, can be nullptr
725 M5_NODISCARD virtual PacketPtr evictBlock(CacheBlk *blk) = 0;
728 * Evict a cache block.
730 * Performs a writeback if necesssary and invalidates the block
732 * @param blk Block to invalidate
733 * @param writebacks Return a list of packets with writebacks
735 void evictBlock(CacheBlk *blk, PacketList &writebacks);
738 * Invalidate a cache block.
740 * @param blk Block to invalidate
742 void invalidateBlock(CacheBlk *blk);
745 * Create a writeback request for the given block.
747 * @param blk The block to writeback.
748 * @return The writeback request for the block.
750 PacketPtr writebackBlk(CacheBlk *blk);
753 * Create a writeclean request for the given block.
755 * Creates a request that writes the block to the cache below
756 * without evicting the block from the current cache.
758 * @param blk The block to write clean.
759 * @param dest The destination of the write clean operation.
760 * @param id Use the given packet id for the write clean operation.
761 * @return The generated write clean packet.
763 PacketPtr writecleanBlk(CacheBlk *blk, Request::Flags dest, PacketId id);
766 * Write back dirty blocks in the cache using functional accesses.
768 virtual void memWriteback() override;
771 * Invalidates all blocks in the cache.
773 * @warn Dirty cache lines will not be written back to
774 * memory. Make sure to call functionalWriteback() first if you
775 * want the to write them to memory.
777 virtual void memInvalidate() override;
780 * Determine if there are any dirty blocks in the cache.
782 * @return true if at least one block is dirty, false otherwise.
784 bool isDirty() const;
787 * Determine if an address is in the ranges covered by this
788 * cache. This is useful to filter snoops.
790 * @param addr Address to check against
792 * @return If the address in question is in range
794 bool inRange(Addr addr) const;
797 * Find next request ready time from among possible sources.
799 Tick nextQueueReadyTime() const;
801 /** Block size of this cache */
802 const unsigned blkSize;
805 * The latency of tag lookup of a cache. It occurs when there is
806 * an access to the cache.
808 const Cycles lookupLatency;
811 * The latency of data access of a cache. It occurs when there is
812 * an access to the cache.
814 const Cycles dataLatency;
817 * This is the forward latency of the cache. It occurs when there
818 * is a cache miss and a request is forwarded downstream, in
819 * particular an outbound miss.
821 const Cycles forwardLatency;
823 /** The latency to fill a cache block */
824 const Cycles fillLatency;
827 * The latency of sending reponse to its upper level cache/core on
828 * a linefill. The responseLatency parameter captures this
831 const Cycles responseLatency;
834 * Whether tags and data are accessed sequentially.
836 const bool sequentialAccess;
838 /** The number of targets for each MSHR. */
841 /** Do we forward snoops from mem side port through to cpu side port? */
845 * Clusivity with respect to the upstream cache, determining if we
846 * fill into both this cache and the cache above on a miss. Note
847 * that we currently do not support strict clusivity policies.
849 const Enums::Clusivity clusivity;
852 * Is this cache read only, for example the instruction cache, or
853 * table-walker cache. A cache that is read only should never see
854 * any writes, and should never get any dirty data (and hence
855 * never have to do any writebacks).
857 const bool isReadOnly;
860 * Bit vector of the blocking reasons for the access path.
865 /** Increasing order number assigned to each incoming request. */
868 /** Stores time the cache blocked for statistics. */
871 /** Pointer to the MSHR that has no targets. */
874 /** The number of misses to trigger an exit event. */
878 * The address range to which the cache responds on the CPU side.
879 * Normally this is all possible memory addresses. */
880 const AddrRangeList addrRanges;
883 /** System we are currently operating in. */
888 * @addtogroup CacheStatistics
892 /** Number of hits per thread for each type of command.
893 @sa Packet::Command */
894 Stats::Vector hits[MemCmd::NUM_MEM_CMDS];
895 /** Number of hits for demand accesses. */
896 Stats::Formula demandHits;
897 /** Number of hit for all accesses. */
898 Stats::Formula overallHits;
900 /** Number of misses per thread for each type of command.
901 @sa Packet::Command */
902 Stats::Vector misses[MemCmd::NUM_MEM_CMDS];
903 /** Number of misses for demand accesses. */
904 Stats::Formula demandMisses;
905 /** Number of misses for all accesses. */
906 Stats::Formula overallMisses;
909 * Total number of cycles per thread/command spent waiting for a miss.
910 * Used to calculate the average miss latency.
912 Stats::Vector missLatency[MemCmd::NUM_MEM_CMDS];
913 /** Total number of cycles spent waiting for demand misses. */
914 Stats::Formula demandMissLatency;
915 /** Total number of cycles spent waiting for all misses. */
916 Stats::Formula overallMissLatency;
918 /** The number of accesses per command and thread. */
919 Stats::Formula accesses[MemCmd::NUM_MEM_CMDS];
920 /** The number of demand accesses. */
921 Stats::Formula demandAccesses;
922 /** The number of overall accesses. */
923 Stats::Formula overallAccesses;
925 /** The miss rate per command and thread. */
926 Stats::Formula missRate[MemCmd::NUM_MEM_CMDS];
927 /** The miss rate of all demand accesses. */
928 Stats::Formula demandMissRate;
929 /** The miss rate for all accesses. */
930 Stats::Formula overallMissRate;
932 /** The average miss latency per command and thread. */
933 Stats::Formula avgMissLatency[MemCmd::NUM_MEM_CMDS];
934 /** The average miss latency for demand misses. */
935 Stats::Formula demandAvgMissLatency;
936 /** The average miss latency for all misses. */
937 Stats::Formula overallAvgMissLatency;
939 /** The total number of cycles blocked for each blocked cause. */
940 Stats::Vector blocked_cycles;
941 /** The number of times this cache blocked for each blocked cause. */
942 Stats::Vector blocked_causes;
944 /** The average number of cycles blocked for each blocked cause. */
945 Stats::Formula avg_blocked;
947 /** The number of times a HW-prefetched block is evicted w/o reference. */
948 Stats::Scalar unusedPrefetches;
950 /** Number of blocks written back per thread. */
951 Stats::Vector writebacks;
953 /** Number of misses that hit in the MSHRs per command and thread. */
954 Stats::Vector mshr_hits[MemCmd::NUM_MEM_CMDS];
955 /** Demand misses that hit in the MSHRs. */
956 Stats::Formula demandMshrHits;
957 /** Total number of misses that hit in the MSHRs. */
958 Stats::Formula overallMshrHits;
960 /** Number of misses that miss in the MSHRs, per command and thread. */
961 Stats::Vector mshr_misses[MemCmd::NUM_MEM_CMDS];
962 /** Demand misses that miss in the MSHRs. */
963 Stats::Formula demandMshrMisses;
964 /** Total number of misses that miss in the MSHRs. */
965 Stats::Formula overallMshrMisses;
967 /** Number of misses that miss in the MSHRs, per command and thread. */
968 Stats::Vector mshr_uncacheable[MemCmd::NUM_MEM_CMDS];
969 /** Total number of misses that miss in the MSHRs. */
970 Stats::Formula overallMshrUncacheable;
972 /** Total cycle latency of each MSHR miss, per command and thread. */
973 Stats::Vector mshr_miss_latency[MemCmd::NUM_MEM_CMDS];
974 /** Total cycle latency of demand MSHR misses. */
975 Stats::Formula demandMshrMissLatency;
976 /** Total cycle latency of overall MSHR misses. */
977 Stats::Formula overallMshrMissLatency;
979 /** Total cycle latency of each MSHR miss, per command and thread. */
980 Stats::Vector mshr_uncacheable_lat[MemCmd::NUM_MEM_CMDS];
981 /** Total cycle latency of overall MSHR misses. */
982 Stats::Formula overallMshrUncacheableLatency;
985 /** The total number of MSHR accesses per command and thread. */
986 Stats::Formula mshrAccesses[MemCmd::NUM_MEM_CMDS];
987 /** The total number of demand MSHR accesses. */
988 Stats::Formula demandMshrAccesses;
989 /** The total number of MSHR accesses. */
990 Stats::Formula overallMshrAccesses;
993 /** The miss rate in the MSHRs pre command and thread. */
994 Stats::Formula mshrMissRate[MemCmd::NUM_MEM_CMDS];
995 /** The demand miss rate in the MSHRs. */
996 Stats::Formula demandMshrMissRate;
997 /** The overall miss rate in the MSHRs. */
998 Stats::Formula overallMshrMissRate;
1000 /** The average latency of an MSHR miss, per command and thread. */
1001 Stats::Formula avgMshrMissLatency[MemCmd::NUM_MEM_CMDS];
1002 /** The average latency of a demand MSHR miss. */
1003 Stats::Formula demandAvgMshrMissLatency;
1004 /** The average overall latency of an MSHR miss. */
1005 Stats::Formula overallAvgMshrMissLatency;
1007 /** The average latency of an MSHR miss, per command and thread. */
1008 Stats::Formula avgMshrUncacheableLatency[MemCmd::NUM_MEM_CMDS];
1009 /** The average overall latency of an MSHR miss. */
1010 Stats::Formula overallAvgMshrUncacheableLatency;
1012 /** Number of replacements of valid blocks. */
1013 Stats::Scalar replacements;
1020 * Register stats for this object.
1022 void regStats() override;
1024 /** Registers probes. */
1025 void regProbePoints() override;
1028 BaseCache(const BaseCacheParams *p, unsigned blk_size);
1031 void init() override;
1033 Port &getPort(const std::string &if_name,
1034 PortID idx=InvalidPortID) override;
1037 * Query block size of a cache.
1038 * @return The block size
1041 getBlockSize() const
1046 const AddrRangeList &getAddrRanges() const { return addrRanges; }
1048 MSHR *allocateMissBuffer(PacketPtr pkt, Tick time, bool sched_send = true)
1050 MSHR *mshr = mshrQueue.allocate(pkt->getBlockAddr(blkSize), blkSize,
1052 allocOnFill(pkt->cmd));
1054 if (mshrQueue.isFull()) {
1055 setBlocked((BlockedCause)MSHRQueue_MSHRs);
1059 // schedule the send
1060 schedMemSideSendEvent(time);
1066 void allocateWriteBuffer(PacketPtr pkt, Tick time)
1068 // should only see writes or clean evicts here
1069 assert(pkt->isWrite() || pkt->cmd == MemCmd::CleanEvict);
1071 Addr blk_addr = pkt->getBlockAddr(blkSize);
1073 WriteQueueEntry *wq_entry =
1074 writeBuffer.findMatch(blk_addr, pkt->isSecure());
1075 if (wq_entry && !wq_entry->inService) {
1076 DPRINTF(Cache, "Potential to merge writeback %s", pkt->print());
1079 writeBuffer.allocate(blk_addr, blkSize, pkt, time, order++);
1081 if (writeBuffer.isFull()) {
1082 setBlocked((BlockedCause)MSHRQueue_WriteBuffer);
1085 // schedule the send
1086 schedMemSideSendEvent(time);
1090 * Returns true if the cache is blocked for accesses.
1092 bool isBlocked() const
1094 return blocked != 0;
1098 * Marks the access path of the cache as blocked for the given cause. This
1099 * also sets the blocked flag in the slave interface.
1100 * @param cause The reason for the cache blocking.
1102 void setBlocked(BlockedCause cause)
1104 uint8_t flag = 1 << cause;
1106 blocked_causes[cause]++;
1107 blockedCycle = curCycle();
1108 cpuSidePort.setBlocked();
1111 DPRINTF(Cache,"Blocking for cause %d, mask=%d\n", cause, blocked);
1115 * Marks the cache as unblocked for the given cause. This also clears the
1116 * blocked flags in the appropriate interfaces.
1117 * @param cause The newly unblocked cause.
1118 * @warning Calling this function can cause a blocked request on the bus to
1119 * access the cache. The cache must be in a state to handle that request.
1121 void clearBlocked(BlockedCause cause)
1123 uint8_t flag = 1 << cause;
1125 DPRINTF(Cache,"Unblocking for cause %d, mask=%d\n", cause, blocked);
1127 blocked_cycles[cause] += curCycle() - blockedCycle;
1128 cpuSidePort.clearBlocked();
1133 * Schedule a send event for the memory-side port. If already
1134 * scheduled, this may reschedule the event at an earlier
1135 * time. When the specified time is reached, the port is free to
1136 * send either a response, a request, or a prefetch request.
1138 * @param time The time when to attempt sending a packet.
1140 void schedMemSideSendEvent(Tick time)
1142 memSidePort.schedSendEvent(time);
1145 bool inCache(Addr addr, bool is_secure) const {
1146 return tags->findBlock(addr, is_secure);
1149 bool hasBeenPrefetched(Addr addr, bool is_secure) const {
1150 CacheBlk *block = tags->findBlock(addr, is_secure);
1152 return block->wasPrefetched();
1158 bool inMissQueue(Addr addr, bool is_secure) const {
1159 return mshrQueue.findMatch(addr, is_secure);
1162 void incMissCount(PacketPtr pkt)
1164 assert(pkt->req->masterId() < system->maxMasters());
1165 misses[pkt->cmdToIndex()][pkt->req->masterId()]++;
1166 pkt->req->incAccessDepth();
1170 exitSimLoop("A cache reached the maximum miss count");
1173 void incHitCount(PacketPtr pkt)
1175 assert(pkt->req->masterId() < system->maxMasters());
1176 hits[pkt->cmdToIndex()][pkt->req->masterId()]++;
1181 * Checks if the cache is coalescing writes
1183 * @return True if the cache is coalescing writes
1185 bool coalesce() const;
1189 * Cache block visitor that writes back dirty cache blocks using
1190 * functional writes.
1192 void writebackVisitor(CacheBlk &blk);
1195 * Cache block visitor that invalidates all blocks in the cache.
1197 * @warn Dirty cache lines will not be written back to memory.
1199 void invalidateVisitor(CacheBlk &blk);
1202 * Take an MSHR, turn it into a suitable downstream packet, and
1203 * send it out. This construct allows a queue entry to choose a suitable
1204 * approach based on its type.
1206 * @param mshr The MSHR to turn into a packet and send
1207 * @return True if the port is waiting for a retry
1209 virtual bool sendMSHRQueuePacket(MSHR* mshr);
1212 * Similar to sendMSHR, but for a write-queue entry
1213 * instead. Create the packet, and send it, and if successful also
1214 * mark the entry in service.
1216 * @param wq_entry The write-queue entry to turn into a packet and send
1217 * @return True if the port is waiting for a retry
1219 bool sendWriteQueuePacket(WriteQueueEntry* wq_entry);
1222 * Serialize the state of the caches
1224 * We currently don't support checkpointing cache state, so this panics.
1226 void serialize(CheckpointOut &cp) const override;
1227 void unserialize(CheckpointIn &cp) override;
1231 * The write allocator inspects write packets and detects streaming
1232 * patterns. The write allocator supports a single stream where writes
1233 * are expected to access consecutive locations and keeps track of
1234 * size of the area covered by the concecutive writes in byteCount.
1236 * 1) When byteCount has surpassed the coallesceLimit the mode
1237 * switches from ALLOCATE to COALESCE where writes should be delayed
1238 * until the whole block is written at which point a single packet
1239 * (whole line write) can service them.
1241 * 2) When byteCount has also exceeded the noAllocateLimit (whole
1242 * line) we switch to NO_ALLOCATE when writes should not allocate in
1243 * the cache but rather send a whole line write to the memory below.
1245 class WriteAllocator : public SimObject {
1247 WriteAllocator(const WriteAllocatorParams *p) :
1249 coalesceLimit(p->coalesce_limit * p->block_size),
1250 noAllocateLimit(p->no_allocate_limit * p->block_size),
1251 delayThreshold(p->delay_threshold)
1257 * Should writes be coalesced? This is true if the mode is set to
1260 * @return return true if the cache should coalesce writes.
1262 bool coalesce() const {
1263 return mode != WriteMode::ALLOCATE;
1267 * Should writes allocate?
1269 * @return return true if the cache should not allocate for writes.
1271 bool allocate() const {
1272 return mode != WriteMode::NO_ALLOCATE;
1276 * Reset the write allocator state, meaning that it allocates for
1277 * writes and has not recorded any information about qualifying
1278 * writes that might trigger a switch to coalescing and later no
1282 mode = WriteMode::ALLOCATE;
1288 * Access whether we need to delay the current write.
1290 * @param blk_addr The block address the packet writes to
1291 * @return true if the current packet should be delayed
1293 bool delay(Addr blk_addr) {
1294 if (delayCtr[blk_addr] > 0) {
1295 --delayCtr[blk_addr];
1303 * Clear delay counter for the input block
1305 * @param blk_addr The accessed cache block
1307 void resetDelay(Addr blk_addr) {
1308 delayCtr.erase(blk_addr);
1312 * Update the write mode based on the current write
1313 * packet. This method compares the packet's address with any
1314 * current stream, and updates the tracking and the mode
1317 * @param write_addr Start address of the write request
1318 * @param write_size Size of the write request
1319 * @param blk_addr The block address that this packet writes to
1321 void updateMode(Addr write_addr, unsigned write_size, Addr blk_addr);
1325 * The current mode for write coalescing and allocation, either
1326 * normal operation (ALLOCATE), write coalescing (COALESCE), or
1327 * write coalescing without allocation (NO_ALLOCATE).
1329 enum class WriteMode : char {
1336 /** Address to match writes against to detect streams. */
1340 * Bytes written contiguously. Saturating once we no longer
1346 * Limits for when to switch between the different write modes.
1348 const uint32_t coalesceLimit;
1349 const uint32_t noAllocateLimit;
1351 * The number of times the allocator will delay an WriteReq MSHR.
1353 const uint32_t delayThreshold;
1356 * Keep track of the number of times the allocator has delayed an
1359 std::unordered_map<Addr, Counter> delayCtr;
1362 #endif //__MEM_CACHE_BASE_HH__