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43 * Declares a basic cache interface BaseCache.
46 #ifndef __MEM_CACHE_BASE_HH__
47 #define __MEM_CACHE_BASE_HH__
53 #include "base/addr_range.hh"
54 #include "base/statistics.hh"
55 #include "base/trace.hh"
56 #include "base/types.hh"
57 #include "debug/Cache.hh"
58 #include "debug/CachePort.hh"
59 #include "enums/Clusivity.hh"
60 #include "mem/cache/cache_blk.hh"
61 #include "mem/cache/compressors/base.hh"
62 #include "mem/cache/mshr_queue.hh"
63 #include "mem/cache/tags/base.hh"
64 #include "mem/cache/write_queue.hh"
65 #include "mem/cache/write_queue_entry.hh"
66 #include "mem/packet.hh"
67 #include "mem/packet_queue.hh"
68 #include "mem/qport.hh"
69 #include "mem/request.hh"
70 #include "params/WriteAllocator.hh"
71 #include "sim/clocked_object.hh"
72 #include "sim/eventq.hh"
73 #include "sim/probe/probe.hh"
74 #include "sim/serialize.hh"
75 #include "sim/sim_exit.hh"
76 #include "sim/system.hh"
78 namespace Prefetcher {
84 struct BaseCacheParams;
87 * A basic cache interface. Implements some common functions for speed.
89 class BaseCache : public ClockedObject
93 * Indexes to enumerate the MSHR queues.
102 * Reasons for caches to be blocked.
105 Blocked_NoMSHRs = MSHRQueue_MSHRs,
106 Blocked_NoWBBuffers = MSHRQueue_WriteBuffer,
114 * A cache master port is used for the memory-side port of the
115 * cache, and in addition to the basic timing port that only sends
116 * response packets through a transmit list, it also offers the
117 * ability to schedule and send request packets (requests &
118 * writebacks). The send event is scheduled through schedSendEvent,
119 * and the sendDeferredPacket of the timing port is modified to
120 * consider both the transmit list and the requests from the MSHR.
122 class CacheMasterPort : public QueuedMasterPort
128 * Schedule a send of a request packet (from the MSHR). Note
129 * that we could already have a retry outstanding.
131 void schedSendEvent(Tick time)
133 DPRINTF(CachePort, "Scheduling send event at %llu\n", time);
134 reqQueue.schedSendEvent(time);
139 CacheMasterPort(const std::string &_name, BaseCache *_cache,
140 ReqPacketQueue &_reqQueue,
141 SnoopRespPacketQueue &_snoopRespQueue) :
142 QueuedMasterPort(_name, _cache, _reqQueue, _snoopRespQueue)
146 * Memory-side port always snoops.
148 * @return always true
150 virtual bool isSnooping() const { return true; }
154 * Override the default behaviour of sendDeferredPacket to enable
155 * the memory-side cache port to also send requests based on the
156 * current MSHR status. This queue has a pointer to our specific
157 * cache implementation and is used by the MemSidePort.
159 class CacheReqPacketQueue : public ReqPacketQueue
165 SnoopRespPacketQueue &snoopRespQueue;
169 CacheReqPacketQueue(BaseCache &cache, RequestPort &port,
170 SnoopRespPacketQueue &snoop_resp_queue,
171 const std::string &label) :
172 ReqPacketQueue(cache, port, label), cache(cache),
173 snoopRespQueue(snoop_resp_queue) { }
176 * Override the normal sendDeferredPacket and do not only
177 * consider the transmit list (used for responses), but also
180 virtual void sendDeferredPacket();
183 * Check if there is a conflicting snoop response about to be
184 * send out, and if so simply stall any requests, and schedule
185 * a send event at the same time as the next snoop response is
188 * @param pkt The packet to check for conflicts against.
190 bool checkConflictingSnoop(const PacketPtr pkt)
192 if (snoopRespQueue.checkConflict(pkt, cache.blkSize)) {
193 DPRINTF(CachePort, "Waiting for snoop response to be "
195 Tick when = snoopRespQueue.deferredPacketReadyTime();
196 schedSendEvent(when);
205 * The memory-side port extends the base cache master port with
206 * access functions for functional, atomic and timing snoops.
208 class MemSidePort : public CacheMasterPort
212 /** The cache-specific queue. */
213 CacheReqPacketQueue _reqQueue;
215 SnoopRespPacketQueue _snoopRespQueue;
217 // a pointer to our specific cache implementation
222 virtual void recvTimingSnoopReq(PacketPtr pkt);
224 virtual bool recvTimingResp(PacketPtr pkt);
226 virtual Tick recvAtomicSnoop(PacketPtr pkt);
228 virtual void recvFunctionalSnoop(PacketPtr pkt);
232 MemSidePort(const std::string &_name, BaseCache *_cache,
233 const std::string &_label);
237 * A cache slave port is used for the CPU-side port of the cache,
238 * and it is basically a simple timing port that uses a transmit
239 * list for responses to the CPU (or connected master). In
240 * addition, it has the functionality to block the port for
241 * incoming requests. If blocked, the port will issue a retry once
244 class CacheSlavePort : public QueuedSlavePort
249 /** Do not accept any new requests. */
252 /** Return to normal operation and accept new requests. */
255 bool isBlocked() const { return blocked; }
259 CacheSlavePort(const std::string &_name, BaseCache *_cache,
260 const std::string &_label);
262 /** A normal packet queue used to store responses. */
263 RespPacketQueue queue;
271 void processSendRetry();
273 EventFunctionWrapper sendRetryEvent;
278 * The CPU-side port extends the base cache slave port with access
279 * functions for functional, atomic and timing requests.
281 class CpuSidePort : public CacheSlavePort
285 // a pointer to our specific cache implementation
289 virtual bool recvTimingSnoopResp(PacketPtr pkt) override;
291 virtual bool tryTiming(PacketPtr pkt) override;
293 virtual bool recvTimingReq(PacketPtr pkt) override;
295 virtual Tick recvAtomic(PacketPtr pkt) override;
297 virtual void recvFunctional(PacketPtr pkt) override;
299 virtual AddrRangeList getAddrRanges() const override;
303 CpuSidePort(const std::string &_name, BaseCache *_cache,
304 const std::string &_label);
308 CpuSidePort cpuSidePort;
309 MemSidePort memSidePort;
313 /** Miss status registers */
316 /** Write/writeback buffer */
317 WriteQueue writeBuffer;
319 /** Tag and data Storage */
322 /** Compression method being used. */
323 Compressor::Base* compressor;
326 Prefetcher::Base *prefetcher;
328 /** To probe when a cache hit occurs */
329 ProbePointArg<PacketPtr> *ppHit;
331 /** To probe when a cache miss occurs */
332 ProbePointArg<PacketPtr> *ppMiss;
334 /** To probe when a cache fill occurs */
335 ProbePointArg<PacketPtr> *ppFill;
338 * The writeAllocator drive optimizations for streaming writes.
339 * It first determines whether a WriteReq MSHR should be delayed,
340 * thus ensuring that we wait longer in cases when we are write
341 * coalescing and allowing all the bytes of the line to be written
342 * before the MSHR packet is sent downstream. This works in unison
343 * with the tracking in the MSHR to check if the entire line is
344 * written. The write mode also affects the behaviour on filling
345 * any whole-line writes. Normally the cache allocates the line
346 * when receiving the InvalidateResp, but after seeing enough
347 * consecutive lines we switch to using the tempBlock, and thus
348 * end up not allocating the line, and instead turning the
349 * whole-line write into a writeback straight away.
351 WriteAllocator * const writeAllocator;
354 * Temporary cache block for occasional transitory use. We use
355 * the tempBlock to fill when allocation fails (e.g., when there
356 * is an outstanding request that accesses the victim block) or
357 * when we want to avoid allocation (e.g., exclusive caches)
359 TempCacheBlk *tempBlock;
362 * Upstream caches need this packet until true is returned, so
363 * hold it for deletion until a subsequent call
365 std::unique_ptr<Packet> pendingDelete;
368 * Mark a request as in service (sent downstream in the memory
369 * system), effectively making this MSHR the ordering point.
371 void markInService(MSHR *mshr, bool pending_modified_resp)
373 bool wasFull = mshrQueue.isFull();
374 mshrQueue.markInService(mshr, pending_modified_resp);
376 if (wasFull && !mshrQueue.isFull()) {
377 clearBlocked(Blocked_NoMSHRs);
381 void markInService(WriteQueueEntry *entry)
383 bool wasFull = writeBuffer.isFull();
384 writeBuffer.markInService(entry);
386 if (wasFull && !writeBuffer.isFull()) {
387 clearBlocked(Blocked_NoWBBuffers);
392 * Determine whether we should allocate on a fill or not. If this
393 * cache is mostly inclusive with regards to the upstream cache(s)
394 * we always allocate (for any non-forwarded and cacheable
395 * requests). In the case of a mostly exclusive cache, we allocate
396 * on fill if the packet did not come from a cache, thus if we:
397 * are dealing with a whole-line write (the latter behaves much
398 * like a writeback), the original target packet came from a
399 * non-caching source, or if we are performing a prefetch or LLSC.
401 * @param cmd Command of the incoming requesting packet
402 * @return Whether we should allocate on the fill
404 inline bool allocOnFill(MemCmd cmd) const
406 return clusivity == Enums::mostly_incl ||
407 cmd == MemCmd::WriteLineReq ||
408 cmd == MemCmd::ReadReq ||
409 cmd == MemCmd::WriteReq ||
415 * Regenerate block address using tags.
416 * Block address regeneration depends on whether we're using a temporary
419 * @param blk The block to regenerate address.
420 * @return The block's address.
422 Addr regenerateBlkAddr(CacheBlk* blk);
425 * Calculate latency of accesses that only touch the tag array.
426 * @sa calculateAccessLatency
428 * @param delay The delay until the packet's metadata is present.
429 * @param lookup_lat Latency of the respective tag lookup.
430 * @return The number of ticks that pass due to a tag-only access.
432 Cycles calculateTagOnlyLatency(const uint32_t delay,
433 const Cycles lookup_lat) const;
435 * Calculate access latency in ticks given a tag lookup latency, and
436 * whether access was a hit or miss.
438 * @param blk The cache block that was accessed.
439 * @param delay The delay until the packet's metadata is present.
440 * @param lookup_lat Latency of the respective tag lookup.
441 * @return The number of ticks that pass due to a block access.
443 Cycles calculateAccessLatency(const CacheBlk* blk, const uint32_t delay,
444 const Cycles lookup_lat) const;
447 * Does all the processing necessary to perform the provided request.
448 * @param pkt The memory request to perform.
449 * @param blk The cache block to be updated.
450 * @param lat The latency of the access.
451 * @param writebacks List for any writebacks that need to be performed.
452 * @return Boolean indicating whether the request was satisfied.
454 virtual bool access(PacketPtr pkt, CacheBlk *&blk, Cycles &lat,
455 PacketList &writebacks);
458 * Handle a timing request that hit in the cache
460 * @param ptk The request packet
461 * @param blk The referenced block
462 * @param request_time The tick at which the block lookup is compete
464 virtual void handleTimingReqHit(PacketPtr pkt, CacheBlk *blk,
468 * Handle a timing request that missed in the cache
470 * Implementation specific handling for different cache
473 * @param ptk The request packet
474 * @param blk The referenced block
475 * @param forward_time The tick at which we can process dependent requests
476 * @param request_time The tick at which the block lookup is compete
478 virtual void handleTimingReqMiss(PacketPtr pkt, CacheBlk *blk,
480 Tick request_time) = 0;
483 * Handle a timing request that missed in the cache
485 * Common functionality across different cache implementations
487 * @param ptk The request packet
488 * @param blk The referenced block
489 * @param mshr Any existing mshr for the referenced cache block
490 * @param forward_time The tick at which we can process dependent requests
491 * @param request_time The tick at which the block lookup is compete
493 void handleTimingReqMiss(PacketPtr pkt, MSHR *mshr, CacheBlk *blk,
494 Tick forward_time, Tick request_time);
497 * Performs the access specified by the request.
498 * @param pkt The request to perform.
500 virtual void recvTimingReq(PacketPtr pkt);
503 * Handling the special case of uncacheable write responses to
504 * make recvTimingResp less cluttered.
506 void handleUncacheableWriteResp(PacketPtr pkt);
509 * Service non-deferred MSHR targets using the received response
511 * Iterates through the list of targets that can be serviced with
512 * the current response.
514 * @param mshr The MSHR that corresponds to the reponse
515 * @param pkt The response packet
516 * @param blk The reference block
518 virtual void serviceMSHRTargets(MSHR *mshr, const PacketPtr pkt,
522 * Handles a response (cache line fill/write ack) from the bus.
523 * @param pkt The response packet
525 virtual void recvTimingResp(PacketPtr pkt);
528 * Snoops bus transactions to maintain coherence.
529 * @param pkt The current bus transaction.
531 virtual void recvTimingSnoopReq(PacketPtr pkt) = 0;
534 * Handle a snoop response.
535 * @param pkt Snoop response packet
537 virtual void recvTimingSnoopResp(PacketPtr pkt) = 0;
540 * Handle a request in atomic mode that missed in this cache
542 * Creates a downstream request, sends it to the memory below and
543 * handles the response. As we are in atomic mode all operations
544 * are performed immediately.
546 * @param pkt The packet with the requests
547 * @param blk The referenced block
548 * @param writebacks A list with packets for any performed writebacks
549 * @return Cycles for handling the request
551 virtual Cycles handleAtomicReqMiss(PacketPtr pkt, CacheBlk *&blk,
552 PacketList &writebacks) = 0;
555 * Performs the access specified by the request.
556 * @param pkt The request to perform.
557 * @return The number of ticks required for the access.
559 virtual Tick recvAtomic(PacketPtr pkt);
562 * Snoop for the provided request in the cache and return the estimated
564 * @param pkt The memory request to snoop
565 * @return The number of ticks required for the snoop.
567 virtual Tick recvAtomicSnoop(PacketPtr pkt) = 0;
570 * Performs the access specified by the request.
572 * @param pkt The request to perform.
573 * @param fromCpuSide from the CPU side port or the memory side port
575 virtual void functionalAccess(PacketPtr pkt, bool from_cpu_side);
578 * Handle doing the Compare and Swap function for SPARC.
580 void cmpAndSwap(CacheBlk *blk, PacketPtr pkt);
583 * Return the next queue entry to service, either a pending miss
584 * from the MSHR queue, a buffered write from the write buffer, or
585 * something from the prefetcher. This function is responsible
586 * for prioritizing among those sources on the fly.
588 QueueEntry* getNextQueueEntry();
591 * Insert writebacks into the write buffer
593 virtual void doWritebacks(PacketList& writebacks, Tick forward_time) = 0;
596 * Send writebacks down the memory hierarchy in atomic mode
598 virtual void doWritebacksAtomic(PacketList& writebacks) = 0;
601 * Create an appropriate downstream bus request packet.
603 * Creates a new packet with the request to be send to the memory
604 * below, or nullptr if the current request in cpu_pkt should just
607 * @param cpu_pkt The miss packet that needs to be satisfied.
608 * @param blk The referenced block, can be nullptr.
609 * @param needs_writable Indicates that the block must be writable
610 * even if the request in cpu_pkt doesn't indicate that.
611 * @param is_whole_line_write True if there are writes for the
613 * @return A packet send to the memory below
615 virtual PacketPtr createMissPacket(PacketPtr cpu_pkt, CacheBlk *blk,
617 bool is_whole_line_write) const = 0;
620 * Determine if clean lines should be written back or not. In
621 * cases where a downstream cache is mostly inclusive we likely
622 * want it to act as a victim cache also for lines that have not
623 * been modified. Hence, we cannot simply drop the line (or send a
624 * clean evict), but rather need to send the actual data.
626 const bool writebackClean;
629 * Writebacks from the tempBlock, resulting on the response path
630 * in atomic mode, must happen after the call to recvAtomic has
631 * finished (for the right ordering of the packets). We therefore
632 * need to hold on to the packets, and have a method and an event
635 PacketPtr tempBlockWriteback;
638 * Send the outstanding tempBlock writeback. To be called after
639 * recvAtomic finishes in cases where the block we filled is in
640 * fact the tempBlock, and now needs to be written back.
642 void writebackTempBlockAtomic() {
643 assert(tempBlockWriteback != nullptr);
644 PacketList writebacks{tempBlockWriteback};
645 doWritebacksAtomic(writebacks);
646 tempBlockWriteback = nullptr;
650 * An event to writeback the tempBlock after recvAtomic
651 * finishes. To avoid other calls to recvAtomic getting in
652 * between, we create this event with a higher priority.
654 EventFunctionWrapper writebackTempBlockAtomicEvent;
657 * When a block is overwriten, its compression information must be updated,
658 * and it may need to be recompressed. If the compression size changes, the
659 * block may either become smaller, in which case there is no side effect,
660 * or bigger (data expansion; fat write), in which case the block might not
661 * fit in its current location anymore. If that happens, there are usually
662 * two options to be taken:
664 * - The co-allocated blocks must be evicted to make room for this block.
665 * Simpler, but ignores replacement data.
666 * - The block itself is moved elsewhere (used in policies where the CF
667 * determines the location of the block).
669 * This implementation uses the first approach.
671 * Notice that this is only called for writebacks, which means that L1
672 * caches (which see regular Writes), do not support compression.
675 * @param blk The block to be overwriten.
676 * @param data A pointer to the data to be compressed (blk's new data).
677 * @param writebacks List for any writebacks that need to be performed.
678 * @return Whether operation is successful or not.
680 bool updateCompressionData(CacheBlk *blk, const uint64_t* data,
681 PacketList &writebacks);
684 * Perform any necessary updates to the block and perform any data
685 * exchange between the packet and the block. The flags of the
686 * packet are also set accordingly.
688 * @param pkt Request packet from upstream that hit a block
689 * @param blk Cache block that the packet hit
690 * @param deferred_response Whether this request originally missed
691 * @param pending_downgrade Whether the writable flag is to be removed
693 virtual void satisfyRequest(PacketPtr pkt, CacheBlk *blk,
694 bool deferred_response = false,
695 bool pending_downgrade = false);
698 * Maintain the clusivity of this cache by potentially
699 * invalidating a block. This method works in conjunction with
700 * satisfyRequest, but is separate to allow us to handle all MSHR
701 * targets before potentially dropping a block.
703 * @param from_cache Whether we have dealt with a packet from a cache
704 * @param blk The block that should potentially be dropped
706 void maintainClusivity(bool from_cache, CacheBlk *blk);
709 * Try to evict the given blocks. If any of them is a transient eviction,
710 * that is, the block is present in the MSHR queue all evictions are
711 * cancelled since handling such cases has not been implemented.
713 * @param evict_blks Blocks marked for eviction.
714 * @param writebacks List for any writebacks that need to be performed.
715 * @return False if any of the evicted blocks is in transient state.
717 bool handleEvictions(std::vector<CacheBlk*> &evict_blks,
718 PacketList &writebacks);
721 * Handle a fill operation caused by a received packet.
723 * Populates a cache block and handles all outstanding requests for the
724 * satisfied fill request. This version takes two memory requests. One
725 * contains the fill data, the other is an optional target to satisfy.
726 * Note that the reason we return a list of writebacks rather than
727 * inserting them directly in the write buffer is that this function
728 * is called by both atomic and timing-mode accesses, and in atomic
729 * mode we don't mess with the write buffer (we just perform the
730 * writebacks atomically once the original request is complete).
732 * @param pkt The memory request with the fill data.
733 * @param blk The cache block if it already exists.
734 * @param writebacks List for any writebacks that need to be performed.
735 * @param allocate Whether to allocate a block or use the temp block
736 * @return Pointer to the new cache block.
738 CacheBlk *handleFill(PacketPtr pkt, CacheBlk *blk,
739 PacketList &writebacks, bool allocate);
742 * Allocate a new block and perform any necessary writebacks
744 * Find a victim block and if necessary prepare writebacks for any
745 * existing data. May return nullptr if there are no replaceable
746 * blocks. If a replaceable block is found, it inserts the new block in
747 * its place. The new block, however, is not set as valid yet.
749 * @param pkt Packet holding the address to update
750 * @param writebacks A list of writeback packets for the evicted blocks
751 * @return the allocated block
753 CacheBlk *allocateBlock(const PacketPtr pkt, PacketList &writebacks);
755 * Evict a cache block.
757 * Performs a writeback if necesssary and invalidates the block
759 * @param blk Block to invalidate
760 * @return A packet with the writeback, can be nullptr
762 M5_NODISCARD virtual PacketPtr evictBlock(CacheBlk *blk) = 0;
765 * Evict a cache block.
767 * Performs a writeback if necesssary and invalidates the block
769 * @param blk Block to invalidate
770 * @param writebacks Return a list of packets with writebacks
772 void evictBlock(CacheBlk *blk, PacketList &writebacks);
775 * Invalidate a cache block.
777 * @param blk Block to invalidate
779 void invalidateBlock(CacheBlk *blk);
782 * Create a writeback request for the given block.
784 * @param blk The block to writeback.
785 * @return The writeback request for the block.
787 PacketPtr writebackBlk(CacheBlk *blk);
790 * Create a writeclean request for the given block.
792 * Creates a request that writes the block to the cache below
793 * without evicting the block from the current cache.
795 * @param blk The block to write clean.
796 * @param dest The destination of the write clean operation.
797 * @param id Use the given packet id for the write clean operation.
798 * @return The generated write clean packet.
800 PacketPtr writecleanBlk(CacheBlk *blk, Request::Flags dest, PacketId id);
803 * Write back dirty blocks in the cache using functional accesses.
805 virtual void memWriteback() override;
808 * Invalidates all blocks in the cache.
810 * @warn Dirty cache lines will not be written back to
811 * memory. Make sure to call functionalWriteback() first if you
812 * want the to write them to memory.
814 virtual void memInvalidate() override;
817 * Determine if there are any dirty blocks in the cache.
819 * @return true if at least one block is dirty, false otherwise.
821 bool isDirty() const;
824 * Determine if an address is in the ranges covered by this
825 * cache. This is useful to filter snoops.
827 * @param addr Address to check against
829 * @return If the address in question is in range
831 bool inRange(Addr addr) const;
834 * Find next request ready time from among possible sources.
836 Tick nextQueueReadyTime() const;
838 /** Block size of this cache */
839 const unsigned blkSize;
842 * The latency of tag lookup of a cache. It occurs when there is
843 * an access to the cache.
845 const Cycles lookupLatency;
848 * The latency of data access of a cache. It occurs when there is
849 * an access to the cache.
851 const Cycles dataLatency;
854 * This is the forward latency of the cache. It occurs when there
855 * is a cache miss and a request is forwarded downstream, in
856 * particular an outbound miss.
858 const Cycles forwardLatency;
860 /** The latency to fill a cache block */
861 const Cycles fillLatency;
864 * The latency of sending reponse to its upper level cache/core on
865 * a linefill. The responseLatency parameter captures this
868 const Cycles responseLatency;
871 * Whether tags and data are accessed sequentially.
873 const bool sequentialAccess;
875 /** The number of targets for each MSHR. */
878 /** Do we forward snoops from mem side port through to cpu side port? */
882 * Clusivity with respect to the upstream cache, determining if we
883 * fill into both this cache and the cache above on a miss. Note
884 * that we currently do not support strict clusivity policies.
886 const Enums::Clusivity clusivity;
889 * Is this cache read only, for example the instruction cache, or
890 * table-walker cache. A cache that is read only should never see
891 * any writes, and should never get any dirty data (and hence
892 * never have to do any writebacks).
894 const bool isReadOnly;
897 * Bit vector of the blocking reasons for the access path.
902 /** Increasing order number assigned to each incoming request. */
905 /** Stores time the cache blocked for statistics. */
908 /** Pointer to the MSHR that has no targets. */
911 /** The number of misses to trigger an exit event. */
915 * The address range to which the cache responds on the CPU side.
916 * Normally this is all possible memory addresses. */
917 const AddrRangeList addrRanges;
920 /** System we are currently operating in. */
923 struct CacheCmdStats : public Stats::Group
925 CacheCmdStats(BaseCache &c, const std::string &name);
928 * Callback to register stats from parent
929 * CacheStats::regStats(). We can't use the normal flow since
930 * there is is no guaranteed order and CacheStats::regStats()
931 * needs to rely on these stats being initialised.
933 void regStatsFromParent();
935 const BaseCache &cache;
937 /** Number of hits per thread for each type of command.
938 @sa Packet::Command */
940 /** Number of misses per thread for each type of command.
941 @sa Packet::Command */
942 Stats::Vector misses;
944 * Total number of cycles per thread/command spent waiting for a miss.
945 * Used to calculate the average miss latency.
947 Stats::Vector missLatency;
948 /** The number of accesses per command and thread. */
949 Stats::Formula accesses;
950 /** The miss rate per command and thread. */
951 Stats::Formula missRate;
952 /** The average miss latency per command and thread. */
953 Stats::Formula avgMissLatency;
954 /** Number of misses that hit in the MSHRs per command and thread. */
955 Stats::Vector mshr_hits;
956 /** Number of misses that miss in the MSHRs, per command and thread. */
957 Stats::Vector mshr_misses;
958 /** Number of misses that miss in the MSHRs, per command and thread. */
959 Stats::Vector mshr_uncacheable;
960 /** Total cycle latency of each MSHR miss, per command and thread. */
961 Stats::Vector mshr_miss_latency;
962 /** Total cycle latency of each MSHR miss, per command and thread. */
963 Stats::Vector mshr_uncacheable_lat;
964 /** The miss rate in the MSHRs pre command and thread. */
965 Stats::Formula mshrMissRate;
966 /** The average latency of an MSHR miss, per command and thread. */
967 Stats::Formula avgMshrMissLatency;
968 /** The average latency of an MSHR miss, per command and thread. */
969 Stats::Formula avgMshrUncacheableLatency;
972 struct CacheStats : public Stats::Group
974 CacheStats(BaseCache &c);
976 void regStats() override;
978 CacheCmdStats &cmdStats(const PacketPtr p) {
979 return *cmd[p->cmdToIndex()];
982 const BaseCache &cache;
984 /** Number of hits for demand accesses. */
985 Stats::Formula demandHits;
986 /** Number of hit for all accesses. */
987 Stats::Formula overallHits;
989 /** Number of misses for demand accesses. */
990 Stats::Formula demandMisses;
991 /** Number of misses for all accesses. */
992 Stats::Formula overallMisses;
994 /** Total number of cycles spent waiting for demand misses. */
995 Stats::Formula demandMissLatency;
996 /** Total number of cycles spent waiting for all misses. */
997 Stats::Formula overallMissLatency;
999 /** The number of demand accesses. */
1000 Stats::Formula demandAccesses;
1001 /** The number of overall accesses. */
1002 Stats::Formula overallAccesses;
1004 /** The miss rate of all demand accesses. */
1005 Stats::Formula demandMissRate;
1006 /** The miss rate for all accesses. */
1007 Stats::Formula overallMissRate;
1009 /** The average miss latency for demand misses. */
1010 Stats::Formula demandAvgMissLatency;
1011 /** The average miss latency for all misses. */
1012 Stats::Formula overallAvgMissLatency;
1014 /** The total number of cycles blocked for each blocked cause. */
1015 Stats::Vector blocked_cycles;
1016 /** The number of times this cache blocked for each blocked cause. */
1017 Stats::Vector blocked_causes;
1019 /** The average number of cycles blocked for each blocked cause. */
1020 Stats::Formula avg_blocked;
1022 /** The number of times a HW-prefetched block is evicted w/o
1024 Stats::Scalar unusedPrefetches;
1026 /** Number of blocks written back per thread. */
1027 Stats::Vector writebacks;
1029 /** Demand misses that hit in the MSHRs. */
1030 Stats::Formula demandMshrHits;
1031 /** Total number of misses that hit in the MSHRs. */
1032 Stats::Formula overallMshrHits;
1034 /** Demand misses that miss in the MSHRs. */
1035 Stats::Formula demandMshrMisses;
1036 /** Total number of misses that miss in the MSHRs. */
1037 Stats::Formula overallMshrMisses;
1039 /** Total number of misses that miss in the MSHRs. */
1040 Stats::Formula overallMshrUncacheable;
1042 /** Total cycle latency of demand MSHR misses. */
1043 Stats::Formula demandMshrMissLatency;
1044 /** Total cycle latency of overall MSHR misses. */
1045 Stats::Formula overallMshrMissLatency;
1047 /** Total cycle latency of overall MSHR misses. */
1048 Stats::Formula overallMshrUncacheableLatency;
1050 /** The demand miss rate in the MSHRs. */
1051 Stats::Formula demandMshrMissRate;
1052 /** The overall miss rate in the MSHRs. */
1053 Stats::Formula overallMshrMissRate;
1055 /** The average latency of a demand MSHR miss. */
1056 Stats::Formula demandAvgMshrMissLatency;
1057 /** The average overall latency of an MSHR miss. */
1058 Stats::Formula overallAvgMshrMissLatency;
1060 /** The average overall latency of an MSHR miss. */
1061 Stats::Formula overallAvgMshrUncacheableLatency;
1063 /** Number of replacements of valid blocks. */
1064 Stats::Scalar replacements;
1066 /** Number of data expansions. */
1067 Stats::Scalar dataExpansions;
1069 /** Per-command statistics */
1070 std::vector<std::unique_ptr<CacheCmdStats>> cmd;
1073 /** Registers probes. */
1074 void regProbePoints() override;
1077 BaseCache(const BaseCacheParams *p, unsigned blk_size);
1080 void init() override;
1082 Port &getPort(const std::string &if_name,
1083 PortID idx=InvalidPortID) override;
1086 * Query block size of a cache.
1087 * @return The block size
1090 getBlockSize() const
1095 const AddrRangeList &getAddrRanges() const { return addrRanges; }
1097 MSHR *allocateMissBuffer(PacketPtr pkt, Tick time, bool sched_send = true)
1099 MSHR *mshr = mshrQueue.allocate(pkt->getBlockAddr(blkSize), blkSize,
1101 allocOnFill(pkt->cmd));
1103 if (mshrQueue.isFull()) {
1104 setBlocked((BlockedCause)MSHRQueue_MSHRs);
1108 // schedule the send
1109 schedMemSideSendEvent(time);
1115 void allocateWriteBuffer(PacketPtr pkt, Tick time)
1117 // should only see writes or clean evicts here
1118 assert(pkt->isWrite() || pkt->cmd == MemCmd::CleanEvict);
1120 Addr blk_addr = pkt->getBlockAddr(blkSize);
1122 // If using compression, on evictions the block is decompressed and
1123 // the operation's latency is added to the payload delay. Consume
1124 // that payload delay here, meaning that the data is always stored
1125 // uncompressed in the writebuffer
1127 time += pkt->payloadDelay;
1128 pkt->payloadDelay = 0;
1131 WriteQueueEntry *wq_entry =
1132 writeBuffer.findMatch(blk_addr, pkt->isSecure());
1133 if (wq_entry && !wq_entry->inService) {
1134 DPRINTF(Cache, "Potential to merge writeback %s", pkt->print());
1137 writeBuffer.allocate(blk_addr, blkSize, pkt, time, order++);
1139 if (writeBuffer.isFull()) {
1140 setBlocked((BlockedCause)MSHRQueue_WriteBuffer);
1143 // schedule the send
1144 schedMemSideSendEvent(time);
1148 * Returns true if the cache is blocked for accesses.
1150 bool isBlocked() const
1152 return blocked != 0;
1156 * Marks the access path of the cache as blocked for the given cause. This
1157 * also sets the blocked flag in the slave interface.
1158 * @param cause The reason for the cache blocking.
1160 void setBlocked(BlockedCause cause)
1162 uint8_t flag = 1 << cause;
1164 stats.blocked_causes[cause]++;
1165 blockedCycle = curCycle();
1166 cpuSidePort.setBlocked();
1169 DPRINTF(Cache,"Blocking for cause %d, mask=%d\n", cause, blocked);
1173 * Marks the cache as unblocked for the given cause. This also clears the
1174 * blocked flags in the appropriate interfaces.
1175 * @param cause The newly unblocked cause.
1176 * @warning Calling this function can cause a blocked request on the bus to
1177 * access the cache. The cache must be in a state to handle that request.
1179 void clearBlocked(BlockedCause cause)
1181 uint8_t flag = 1 << cause;
1183 DPRINTF(Cache,"Unblocking for cause %d, mask=%d\n", cause, blocked);
1185 stats.blocked_cycles[cause] += curCycle() - blockedCycle;
1186 cpuSidePort.clearBlocked();
1191 * Schedule a send event for the memory-side port. If already
1192 * scheduled, this may reschedule the event at an earlier
1193 * time. When the specified time is reached, the port is free to
1194 * send either a response, a request, or a prefetch request.
1196 * @param time The time when to attempt sending a packet.
1198 void schedMemSideSendEvent(Tick time)
1200 memSidePort.schedSendEvent(time);
1203 bool inCache(Addr addr, bool is_secure) const {
1204 return tags->findBlock(addr, is_secure);
1207 bool hasBeenPrefetched(Addr addr, bool is_secure) const {
1208 CacheBlk *block = tags->findBlock(addr, is_secure);
1210 return block->wasPrefetched();
1216 bool inMissQueue(Addr addr, bool is_secure) const {
1217 return mshrQueue.findMatch(addr, is_secure);
1220 void incMissCount(PacketPtr pkt)
1222 assert(pkt->req->masterId() < system->maxMasters());
1223 stats.cmdStats(pkt).misses[pkt->req->masterId()]++;
1224 pkt->req->incAccessDepth();
1228 exitSimLoop("A cache reached the maximum miss count");
1231 void incHitCount(PacketPtr pkt)
1233 assert(pkt->req->masterId() < system->maxMasters());
1234 stats.cmdStats(pkt).hits[pkt->req->masterId()]++;
1238 * Checks if the cache is coalescing writes
1240 * @return True if the cache is coalescing writes
1242 bool coalesce() const;
1246 * Cache block visitor that writes back dirty cache blocks using
1247 * functional writes.
1249 void writebackVisitor(CacheBlk &blk);
1252 * Cache block visitor that invalidates all blocks in the cache.
1254 * @warn Dirty cache lines will not be written back to memory.
1256 void invalidateVisitor(CacheBlk &blk);
1259 * Take an MSHR, turn it into a suitable downstream packet, and
1260 * send it out. This construct allows a queue entry to choose a suitable
1261 * approach based on its type.
1263 * @param mshr The MSHR to turn into a packet and send
1264 * @return True if the port is waiting for a retry
1266 virtual bool sendMSHRQueuePacket(MSHR* mshr);
1269 * Similar to sendMSHR, but for a write-queue entry
1270 * instead. Create the packet, and send it, and if successful also
1271 * mark the entry in service.
1273 * @param wq_entry The write-queue entry to turn into a packet and send
1274 * @return True if the port is waiting for a retry
1276 bool sendWriteQueuePacket(WriteQueueEntry* wq_entry);
1279 * Serialize the state of the caches
1281 * We currently don't support checkpointing cache state, so this panics.
1283 void serialize(CheckpointOut &cp) const override;
1284 void unserialize(CheckpointIn &cp) override;
1288 * The write allocator inspects write packets and detects streaming
1289 * patterns. The write allocator supports a single stream where writes
1290 * are expected to access consecutive locations and keeps track of
1291 * size of the area covered by the concecutive writes in byteCount.
1293 * 1) When byteCount has surpassed the coallesceLimit the mode
1294 * switches from ALLOCATE to COALESCE where writes should be delayed
1295 * until the whole block is written at which point a single packet
1296 * (whole line write) can service them.
1298 * 2) When byteCount has also exceeded the noAllocateLimit (whole
1299 * line) we switch to NO_ALLOCATE when writes should not allocate in
1300 * the cache but rather send a whole line write to the memory below.
1302 class WriteAllocator : public SimObject {
1304 WriteAllocator(const WriteAllocatorParams *p) :
1306 coalesceLimit(p->coalesce_limit * p->block_size),
1307 noAllocateLimit(p->no_allocate_limit * p->block_size),
1308 delayThreshold(p->delay_threshold)
1314 * Should writes be coalesced? This is true if the mode is set to
1317 * @return return true if the cache should coalesce writes.
1319 bool coalesce() const {
1320 return mode != WriteMode::ALLOCATE;
1324 * Should writes allocate?
1326 * @return return true if the cache should not allocate for writes.
1328 bool allocate() const {
1329 return mode != WriteMode::NO_ALLOCATE;
1333 * Reset the write allocator state, meaning that it allocates for
1334 * writes and has not recorded any information about qualifying
1335 * writes that might trigger a switch to coalescing and later no
1339 mode = WriteMode::ALLOCATE;
1345 * Access whether we need to delay the current write.
1347 * @param blk_addr The block address the packet writes to
1348 * @return true if the current packet should be delayed
1350 bool delay(Addr blk_addr) {
1351 if (delayCtr[blk_addr] > 0) {
1352 --delayCtr[blk_addr];
1360 * Clear delay counter for the input block
1362 * @param blk_addr The accessed cache block
1364 void resetDelay(Addr blk_addr) {
1365 delayCtr.erase(blk_addr);
1369 * Update the write mode based on the current write
1370 * packet. This method compares the packet's address with any
1371 * current stream, and updates the tracking and the mode
1374 * @param write_addr Start address of the write request
1375 * @param write_size Size of the write request
1376 * @param blk_addr The block address that this packet writes to
1378 void updateMode(Addr write_addr, unsigned write_size, Addr blk_addr);
1382 * The current mode for write coalescing and allocation, either
1383 * normal operation (ALLOCATE), write coalescing (COALESCE), or
1384 * write coalescing without allocation (NO_ALLOCATE).
1386 enum class WriteMode : char {
1393 /** Address to match writes against to detect streams. */
1397 * Bytes written contiguously. Saturating once we no longer
1403 * Limits for when to switch between the different write modes.
1405 const uint32_t coalesceLimit;
1406 const uint32_t noAllocateLimit;
1408 * The number of times the allocator will delay an WriteReq MSHR.
1410 const uint32_t delayThreshold;
1413 * Keep track of the number of times the allocator has delayed an
1416 std::unordered_map<Addr, Counter> delayCtr;
1419 #endif //__MEM_CACHE_BASE_HH__