src/mem/cache/base.hh

   1 /*
   2  * Copyright (c) 2003-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Erik Hallnor
  29  *          Steve Reinhardt
  30  *          Ron Dreslinski
  31  */
  32
  33 /**
  34  * @file
  35  * Declares a basic cache interface BaseCache.
  36  */
  37
  38 #ifndef __BASE_CACHE_HH__
  39 #define __BASE_CACHE_HH__
  40
  41 #include <vector>
  42 #include <string>
  43 #include <list>
  44 #include <algorithm>
  45 #include <inttypes.h>
  46
  47 #include "base/misc.hh"
  48 #include "base/statistics.hh"
  49 #include "base/trace.hh"
  50 #include "mem/cache/mshr_queue.hh"
  51 #include "mem/mem_object.hh"
  52 #include "mem/packet.hh"
  53 #include "mem/tport.hh"
  54 #include "mem/request.hh"
  55 #include "params/BaseCache.hh"
  56 #include "sim/eventq.hh"
  57 #include "sim/sim_exit.hh"
  58
  59 class MSHR;
  60 /**
  61  * A basic cache interface. Implements some common functions for speed.
  62  */
  63 class BaseCache : public MemObject
  64 {
  65     /**
  66      * Indexes to enumerate the MSHR queues.
  67      */
  68     enum MSHRQueueIndex {
  69         MSHRQueue_MSHRs,
  70         MSHRQueue_WriteBuffer
  71     };
  72
  73     /**
  74      * Reasons for caches to be blocked.
  75      */
  76     enum BlockedCause {
  77         Blocked_NoMSHRs = MSHRQueue_MSHRs,
  78         Blocked_NoWBBuffers = MSHRQueue_WriteBuffer,
  79         Blocked_NoTargets,
  80         NUM_BLOCKED_CAUSES
  81     };
  82
  83   public:
  84     /**
  85      * Reasons for cache to request a bus.
  86      */
  87     enum RequestCause {
  88         Request_MSHR = MSHRQueue_MSHRs,
  89         Request_WB = MSHRQueue_WriteBuffer,
  90         Request_PF,
  91         NUM_REQUEST_CAUSES
  92     };
  93
  94   private:
  95
  96     class CachePort : public SimpleTimingPort
  97     {
  98       public:
  99         BaseCache *cache;
 100
 101       protected:
 102         CachePort(const std::string &_name, BaseCache *_cache,
 103                   const std::string &_label);
 104
 105         virtual void recvStatusChange(Status status);
 106
 107         virtual int deviceBlockSize();
 108
 109         bool recvRetryCommon();
 110
 111         typedef EventWrapper<Port, &Port::sendRetry>
 112             SendRetryEvent;
 113
 114         const std::string label;
 115
 116       public:
 117         void setOtherPort(CachePort *_otherPort) { otherPort = _otherPort; }
 118
 119         void setBlocked();
 120
 121         void clearBlocked();
 122
 123         bool checkFunctional(PacketPtr pkt);
 124
 125         CachePort *otherPort;
 126
 127         bool blocked;
 128
 129         bool mustSendRetry;
 130
 131         void requestBus(RequestCause cause, Tick time)
 132         {
 133             DPRINTF(CachePort, "Asserting bus request for cause %d\n", cause);
 134             if (!waitingOnRetry) {
 135                 schedSendEvent(time);
 136             }
 137         }
 138
 139         void respond(PacketPtr pkt, Tick time) {
 140             schedSendTiming(pkt, time);
 141         }
 142     };
 143
 144   public: //Made public so coherence can get at it.
 145     CachePort *cpuSidePort;
 146     CachePort *memSidePort;
 147
 148   protected:
 149
 150     /** Miss status registers */
 151     MSHRQueue mshrQueue;
 152
 153     /** Write/writeback buffer */
 154     MSHRQueue writeBuffer;
 155
 156     MSHR *allocateBufferInternal(MSHRQueue *mq, Addr addr, int size,
 157                                  PacketPtr pkt, Tick time, bool requestBus)
 158     {
 159         MSHR *mshr = mq->allocate(addr, size, pkt, time, order++);
 160
 161         if (mq->isFull()) {
 162             setBlocked((BlockedCause)mq->index);
 163         }
 164
 165         if (requestBus) {
 166             requestMemSideBus((RequestCause)mq->index, time);
 167         }
 168
 169         return mshr;
 170     }
 171
 172     void markInServiceInternal(MSHR *mshr)
 173     {
 174         MSHRQueue *mq = mshr->queue;
 175         bool wasFull = mq->isFull();
 176         mq->markInService(mshr);
 177         if (wasFull && !mq->isFull()) {
 178             clearBlocked((BlockedCause)mq->index);
 179         }
 180     }
 181
 182     /** Block size of this cache */
 183     const int blkSize;
 184
 185     /**
 186      * The latency of a hit in this device.
 187      */
 188     int hitLatency;
 189
 190     /** The number of targets for each MSHR. */
 191     const int numTarget;
 192
 193     /** Do we forward snoops from mem side port through to cpu side port? */
 194     bool forwardSnoops;
 195
 196     /**
 197      * Bit vector of the blocking reasons for the access path.
 198      * @sa #BlockedCause
 199      */
 200     uint8_t blocked;
 201
 202     /** Increasing order number assigned to each incoming request. */
 203     uint64_t order;
 204
 205     /** Stores time the cache blocked for statistics. */
 206     Tick blockedCycle;
 207
 208     /** Pointer to the MSHR that has no targets. */
 209     MSHR *noTargetMSHR;
 210
 211     /** The number of misses to trigger an exit event. */
 212     Counter missCount;
 213
 214     /** The drain event. */
 215     Event *drainEvent;
 216
 217     /**
 218      * The address range to which the cache responds on the CPU side.
 219      * Normally this is all possible memory addresses. */
 220     Range<Addr> addrRange;
 221
 222   public:
 223     // Statistics
 224     /**
 225      * @addtogroup CacheStatistics
 226      * @{
 227      */
 228
 229     /** Number of hits per thread for each type of command. @sa Packet::Command */
 230     Stats::Vector hits[MemCmd::NUM_MEM_CMDS];
 231     /** Number of hits for demand accesses. */
 232     Stats::Formula demandHits;
 233     /** Number of hit for all accesses. */
 234     Stats::Formula overallHits;
 235
 236     /** Number of misses per thread for each type of command. @sa Packet::Command */
 237     Stats::Vector misses[MemCmd::NUM_MEM_CMDS];
 238     /** Number of misses for demand accesses. */
 239     Stats::Formula demandMisses;
 240     /** Number of misses for all accesses. */
 241     Stats::Formula overallMisses;
 242
 243     /**
 244      * Total number of cycles per thread/command spent waiting for a miss.
 245      * Used to calculate the average miss latency.
 246      */
 247     Stats::Vector missLatency[MemCmd::NUM_MEM_CMDS];
 248     /** Total number of cycles spent waiting for demand misses. */
 249     Stats::Formula demandMissLatency;
 250     /** Total number of cycles spent waiting for all misses. */
 251     Stats::Formula overallMissLatency;
 252
 253     /** The number of accesses per command and thread. */
 254     Stats::Formula accesses[MemCmd::NUM_MEM_CMDS];
 255     /** The number of demand accesses. */
 256     Stats::Formula demandAccesses;
 257     /** The number of overall accesses. */
 258     Stats::Formula overallAccesses;
 259
 260     /** The miss rate per command and thread. */
 261     Stats::Formula missRate[MemCmd::NUM_MEM_CMDS];
 262     /** The miss rate of all demand accesses. */
 263     Stats::Formula demandMissRate;
 264     /** The miss rate for all accesses. */
 265     Stats::Formula overallMissRate;
 266
 267     /** The average miss latency per command and thread. */
 268     Stats::Formula avgMissLatency[MemCmd::NUM_MEM_CMDS];
 269     /** The average miss latency for demand misses. */
 270     Stats::Formula demandAvgMissLatency;
 271     /** The average miss latency for all misses. */
 272     Stats::Formula overallAvgMissLatency;
 273
 274     /** The total number of cycles blocked for each blocked cause. */
 275     Stats::Vector blocked_cycles;
 276     /** The number of times this cache blocked for each blocked cause. */
 277     Stats::Vector blocked_causes;
 278
 279     /** The average number of cycles blocked for each blocked cause. */
 280     Stats::Formula avg_blocked;
 281
 282     /** The number of fast writes (WH64) performed. */
 283     Stats::Scalar fastWrites;
 284
 285     /** The number of cache copies performed. */
 286     Stats::Scalar cacheCopies;
 287
 288     /** Number of blocks written back per thread. */
 289     Stats::Vector writebacks;
 290
 291     /** Number of misses that hit in the MSHRs per command and thread. */
 292     Stats::Vector mshr_hits[MemCmd::NUM_MEM_CMDS];
 293     /** Demand misses that hit in the MSHRs. */
 294     Stats::Formula demandMshrHits;
 295     /** Total number of misses that hit in the MSHRs. */
 296     Stats::Formula overallMshrHits;
 297
 298     /** Number of misses that miss in the MSHRs, per command and thread. */
 299     Stats::Vector mshr_misses[MemCmd::NUM_MEM_CMDS];
 300     /** Demand misses that miss in the MSHRs. */
 301     Stats::Formula demandMshrMisses;
 302     /** Total number of misses that miss in the MSHRs. */
 303     Stats::Formula overallMshrMisses;
 304
 305     /** Number of misses that miss in the MSHRs, per command and thread. */
 306     Stats::Vector mshr_uncacheable[MemCmd::NUM_MEM_CMDS];
 307     /** Total number of misses that miss in the MSHRs. */
 308     Stats::Formula overallMshrUncacheable;
 309
 310     /** Total cycle latency of each MSHR miss, per command and thread. */
 311     Stats::Vector mshr_miss_latency[MemCmd::NUM_MEM_CMDS];
 312     /** Total cycle latency of demand MSHR misses. */
 313     Stats::Formula demandMshrMissLatency;
 314     /** Total cycle latency of overall MSHR misses. */
 315     Stats::Formula overallMshrMissLatency;
 316
 317     /** Total cycle latency of each MSHR miss, per command and thread. */
 318     Stats::Vector mshr_uncacheable_lat[MemCmd::NUM_MEM_CMDS];
 319     /** Total cycle latency of overall MSHR misses. */
 320     Stats::Formula overallMshrUncacheableLatency;
 321
 322     /** The total number of MSHR accesses per command and thread. */
 323     Stats::Formula mshrAccesses[MemCmd::NUM_MEM_CMDS];
 324     /** The total number of demand MSHR accesses. */
 325     Stats::Formula demandMshrAccesses;
 326     /** The total number of MSHR accesses. */
 327     Stats::Formula overallMshrAccesses;
 328
 329     /** The miss rate in the MSHRs pre command and thread. */
 330     Stats::Formula mshrMissRate[MemCmd::NUM_MEM_CMDS];
 331     /** The demand miss rate in the MSHRs. */
 332     Stats::Formula demandMshrMissRate;
 333     /** The overall miss rate in the MSHRs. */
 334     Stats::Formula overallMshrMissRate;
 335
 336     /** The average latency of an MSHR miss, per command and thread. */
 337     Stats::Formula avgMshrMissLatency[MemCmd::NUM_MEM_CMDS];
 338     /** The average latency of a demand MSHR miss. */
 339     Stats::Formula demandAvgMshrMissLatency;
 340     /** The average overall latency of an MSHR miss. */
 341     Stats::Formula overallAvgMshrMissLatency;
 342
 343     /** The average latency of an MSHR miss, per command and thread. */
 344     Stats::Formula avgMshrUncacheableLatency[MemCmd::NUM_MEM_CMDS];
 345     /** The average overall latency of an MSHR miss. */
 346     Stats::Formula overallAvgMshrUncacheableLatency;
 347
 348     /** The number of times a thread hit its MSHR cap. */
 349     Stats::Vector mshr_cap_events;
 350     /** The number of times software prefetches caused the MSHR to block. */
 351     Stats::Vector soft_prefetch_mshr_full;
 352
 353     Stats::Scalar mshr_no_allocate_misses;
 354
 355     /**
 356      * @}
 357      */
 358
 359     /**
 360      * Register stats for this object.
 361      */
 362     virtual void regStats();
 363
 364   public:
 365     typedef BaseCacheParams Params;
 366     BaseCache(const Params *p);
 367     ~BaseCache() {}
 368
 369     virtual void init();
 370
 371     /**
 372      * Query block size of a cache.
 373      * @return  The block size
 374      */
 375     int getBlockSize() const
 376     {
 377         return blkSize;
 378     }
 379
 380
 381     Addr blockAlign(Addr addr) const { return (addr & ~(blkSize - 1)); }
 382
 383
 384     const Range<Addr> &getAddrRange() const { return addrRange; }
 385
 386     MSHR *allocateMissBuffer(PacketPtr pkt, Tick time, bool requestBus)
 387     {
 388         assert(!pkt->req->isUncacheable());
 389         return allocateBufferInternal(&mshrQueue,
 390                                       blockAlign(pkt->getAddr()), blkSize,
 391                                       pkt, time, requestBus);
 392     }
 393
 394     MSHR *allocateWriteBuffer(PacketPtr pkt, Tick time, bool requestBus)
 395     {
 396         assert(pkt->isWrite() && !pkt->isRead());
 397         return allocateBufferInternal(&writeBuffer,
 398                                       pkt->getAddr(), pkt->getSize(),
 399                                       pkt, time, requestBus);
 400     }
 401
 402     MSHR *allocateUncachedReadBuffer(PacketPtr pkt, Tick time, bool requestBus)
 403     {
 404         assert(pkt->req->isUncacheable());
 405         assert(pkt->isRead());
 406         return allocateBufferInternal(&mshrQueue,
 407                                       pkt->getAddr(), pkt->getSize(),
 408                                       pkt, time, requestBus);
 409     }
 410
 411     /**
 412      * Returns true if the cache is blocked for accesses.
 413      */
 414     bool isBlocked()
 415     {
 416         return blocked != 0;
 417     }
 418
 419     /**
 420      * Marks the access path of the cache as blocked for the given cause. This
 421      * also sets the blocked flag in the slave interface.
 422      * @param cause The reason for the cache blocking.
 423      */
 424     void setBlocked(BlockedCause cause)
 425     {
 426         uint8_t flag = 1 << cause;
 427         if (blocked == 0) {
 428             blocked_causes[cause]++;
 429             blockedCycle = curTick;
 430             cpuSidePort->setBlocked();
 431         }
 432         blocked |= flag;
 433         DPRINTF(Cache,"Blocking for cause %d, mask=%d\n", cause, blocked);
 434     }
 435
 436     /**
 437      * Marks the cache as unblocked for the given cause. This also clears the
 438      * blocked flags in the appropriate interfaces.
 439      * @param cause The newly unblocked cause.
 440      * @warning Calling this function can cause a blocked request on the bus to
 441      * access the cache. The cache must be in a state to handle that request.
 442      */
 443     void clearBlocked(BlockedCause cause)
 444     {
 445         uint8_t flag = 1 << cause;
 446         blocked &= ~flag;
 447         DPRINTF(Cache,"Unblocking for cause %d, mask=%d\n", cause, blocked);
 448         if (blocked == 0) {
 449             blocked_cycles[cause] += curTick - blockedCycle;
 450             cpuSidePort->clearBlocked();
 451         }
 452     }
 453
 454     /**
 455      * Request the master bus for the given cause and time.
 456      * @param cause The reason for the request.
 457      * @param time The time to make the request.
 458      */
 459     void requestMemSideBus(RequestCause cause, Tick time)
 460     {
 461         memSidePort->requestBus(cause, time);
 462     }
 463
 464     /**
 465      * Clear the master bus request for the given cause.
 466      * @param cause The request reason to clear.
 467      */
 468     void deassertMemSideBusRequest(RequestCause cause)
 469     {
 470         // Obsolete... we no longer signal bus requests explicitly so
 471         // we can't deassert them.  Leaving this in as a no-op since
 472         // the prefetcher calls it to indicate that it no longer wants
 473         // to request a prefetch, and someday that might be
 474         // interesting again.
 475     }
 476
 477     virtual unsigned int drain(Event *de);
 478
 479     virtual bool inCache(Addr addr) = 0;
 480
 481     virtual bool inMissQueue(Addr addr) = 0;
 482
 483     void incMissCount(PacketPtr pkt)
 484     {
 485         misses[pkt->cmdToIndex()][0/*pkt->req->threadId()*/]++;
 486
 487         if (missCount) {
 488             --missCount;
 489             if (missCount == 0)
 490                 exitSimLoop("A cache reached the maximum miss count");
 491         }
 492     }
 493
 494 };
 495
 496 #endif //__BASE_CACHE_HH__