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28 * Authors: Erik Hallnor
35 * Declares a basic cache interface BaseCache.
38 #ifndef __BASE_CACHE_HH__
39 #define __BASE_CACHE_HH__
47 #include "base/misc.hh"
48 #include "base/statistics.hh"
49 #include "base/trace.hh"
50 #include "mem/cache/mshr_queue.hh"
51 #include "mem/mem_object.hh"
52 #include "mem/packet.hh"
53 #include "mem/tport.hh"
54 #include "mem/request.hh"
55 #include "params/BaseCache.hh"
56 #include "sim/eventq.hh"
57 #include "sim/sim_exit.hh"
61 * A basic cache interface. Implements some common functions for speed.
63 class BaseCache : public MemObject
66 * Indexes to enumerate the MSHR queues.
74 * Reasons for caches to be blocked.
77 Blocked_NoMSHRs = MSHRQueue_MSHRs,
78 Blocked_NoWBBuffers = MSHRQueue_WriteBuffer,
85 * Reasons for cache to request a bus.
88 Request_MSHR = MSHRQueue_MSHRs,
89 Request_WB = MSHRQueue_WriteBuffer,
96 class CachePort : public SimpleTimingPort
102 CachePort(const std::string &_name, BaseCache *_cache,
103 const std::string &_label,
104 std::vector<Range<Addr> > filter_ranges);
106 virtual void recvStatusChange(Status status);
108 virtual int deviceBlockSize();
110 bool recvRetryCommon();
112 typedef EventWrapper<Port, &Port::sendRetry>
115 const std::string label;
118 void setOtherPort(CachePort *_otherPort) { otherPort = _otherPort; }
124 bool checkFunctional(PacketPtr pkt);
126 CachePort *otherPort;
133 std::vector<Range<Addr> > filterRanges;
135 void requestBus(RequestCause cause, Tick time)
137 DPRINTF(CachePort, "Asserting bus request for cause %d\n", cause);
138 if (!waitingOnRetry) {
139 schedSendEvent(time);
143 void respond(PacketPtr pkt, Tick time) {
144 schedSendTiming(pkt, time);
148 public: //Made public so coherence can get at it.
149 CachePort *cpuSidePort;
150 CachePort *memSidePort;
154 /** Miss status registers */
157 /** Write/writeback buffer */
158 MSHRQueue writeBuffer;
160 MSHR *allocateBufferInternal(MSHRQueue *mq, Addr addr, int size,
161 PacketPtr pkt, Tick time, bool requestBus)
163 MSHR *mshr = mq->allocate(addr, size, pkt, time, order++);
166 setBlocked((BlockedCause)mq->index);
170 requestMemSideBus((RequestCause)mq->index, time);
176 void markInServiceInternal(MSHR *mshr)
178 MSHRQueue *mq = mshr->queue;
179 bool wasFull = mq->isFull();
180 mq->markInService(mshr);
181 if (wasFull && !mq->isFull()) {
182 clearBlocked((BlockedCause)mq->index);
186 /** Block size of this cache */
190 * The latency of a hit in this device.
194 /** The number of targets for each MSHR. */
197 /** Increasing order number assigned to each incoming request. */
201 * Bit vector of the blocking reasons for the access path.
206 /** Stores time the cache blocked for statistics. */
209 /** Pointer to the MSHR that has no targets. */
212 /** The number of misses to trigger an exit event. */
215 /** The drain event. */
221 * @addtogroup CacheStatistics
225 /** Number of hits per thread for each type of command. @sa Packet::Command */
226 Stats::Vector<> hits[MemCmd::NUM_MEM_CMDS];
227 /** Number of hits for demand accesses. */
228 Stats::Formula demandHits;
229 /** Number of hit for all accesses. */
230 Stats::Formula overallHits;
232 /** Number of misses per thread for each type of command. @sa Packet::Command */
233 Stats::Vector<> misses[MemCmd::NUM_MEM_CMDS];
234 /** Number of misses for demand accesses. */
235 Stats::Formula demandMisses;
236 /** Number of misses for all accesses. */
237 Stats::Formula overallMisses;
240 * Total number of cycles per thread/command spent waiting for a miss.
241 * Used to calculate the average miss latency.
243 Stats::Vector<> missLatency[MemCmd::NUM_MEM_CMDS];
244 /** Total number of cycles spent waiting for demand misses. */
245 Stats::Formula demandMissLatency;
246 /** Total number of cycles spent waiting for all misses. */
247 Stats::Formula overallMissLatency;
249 /** The number of accesses per command and thread. */
250 Stats::Formula accesses[MemCmd::NUM_MEM_CMDS];
251 /** The number of demand accesses. */
252 Stats::Formula demandAccesses;
253 /** The number of overall accesses. */
254 Stats::Formula overallAccesses;
256 /** The miss rate per command and thread. */
257 Stats::Formula missRate[MemCmd::NUM_MEM_CMDS];
258 /** The miss rate of all demand accesses. */
259 Stats::Formula demandMissRate;
260 /** The miss rate for all accesses. */
261 Stats::Formula overallMissRate;
263 /** The average miss latency per command and thread. */
264 Stats::Formula avgMissLatency[MemCmd::NUM_MEM_CMDS];
265 /** The average miss latency for demand misses. */
266 Stats::Formula demandAvgMissLatency;
267 /** The average miss latency for all misses. */
268 Stats::Formula overallAvgMissLatency;
270 /** The total number of cycles blocked for each blocked cause. */
271 Stats::Vector<> blocked_cycles;
272 /** The number of times this cache blocked for each blocked cause. */
273 Stats::Vector<> blocked_causes;
275 /** The average number of cycles blocked for each blocked cause. */
276 Stats::Formula avg_blocked;
278 /** The number of fast writes (WH64) performed. */
279 Stats::Scalar<> fastWrites;
281 /** The number of cache copies performed. */
282 Stats::Scalar<> cacheCopies;
284 /** Number of blocks written back per thread. */
285 Stats::Vector<> writebacks;
287 /** Number of misses that hit in the MSHRs per command and thread. */
288 Stats::Vector<> mshr_hits[MemCmd::NUM_MEM_CMDS];
289 /** Demand misses that hit in the MSHRs. */
290 Stats::Formula demandMshrHits;
291 /** Total number of misses that hit in the MSHRs. */
292 Stats::Formula overallMshrHits;
294 /** Number of misses that miss in the MSHRs, per command and thread. */
295 Stats::Vector<> mshr_misses[MemCmd::NUM_MEM_CMDS];
296 /** Demand misses that miss in the MSHRs. */
297 Stats::Formula demandMshrMisses;
298 /** Total number of misses that miss in the MSHRs. */
299 Stats::Formula overallMshrMisses;
301 /** Number of misses that miss in the MSHRs, per command and thread. */
302 Stats::Vector<> mshr_uncacheable[MemCmd::NUM_MEM_CMDS];
303 /** Total number of misses that miss in the MSHRs. */
304 Stats::Formula overallMshrUncacheable;
306 /** Total cycle latency of each MSHR miss, per command and thread. */
307 Stats::Vector<> mshr_miss_latency[MemCmd::NUM_MEM_CMDS];
308 /** Total cycle latency of demand MSHR misses. */
309 Stats::Formula demandMshrMissLatency;
310 /** Total cycle latency of overall MSHR misses. */
311 Stats::Formula overallMshrMissLatency;
313 /** Total cycle latency of each MSHR miss, per command and thread. */
314 Stats::Vector<> mshr_uncacheable_lat[MemCmd::NUM_MEM_CMDS];
315 /** Total cycle latency of overall MSHR misses. */
316 Stats::Formula overallMshrUncacheableLatency;
318 /** The total number of MSHR accesses per command and thread. */
319 Stats::Formula mshrAccesses[MemCmd::NUM_MEM_CMDS];
320 /** The total number of demand MSHR accesses. */
321 Stats::Formula demandMshrAccesses;
322 /** The total number of MSHR accesses. */
323 Stats::Formula overallMshrAccesses;
325 /** The miss rate in the MSHRs pre command and thread. */
326 Stats::Formula mshrMissRate[MemCmd::NUM_MEM_CMDS];
327 /** The demand miss rate in the MSHRs. */
328 Stats::Formula demandMshrMissRate;
329 /** The overall miss rate in the MSHRs. */
330 Stats::Formula overallMshrMissRate;
332 /** The average latency of an MSHR miss, per command and thread. */
333 Stats::Formula avgMshrMissLatency[MemCmd::NUM_MEM_CMDS];
334 /** The average latency of a demand MSHR miss. */
335 Stats::Formula demandAvgMshrMissLatency;
336 /** The average overall latency of an MSHR miss. */
337 Stats::Formula overallAvgMshrMissLatency;
339 /** The average latency of an MSHR miss, per command and thread. */
340 Stats::Formula avgMshrUncacheableLatency[MemCmd::NUM_MEM_CMDS];
341 /** The average overall latency of an MSHR miss. */
342 Stats::Formula overallAvgMshrUncacheableLatency;
344 /** The number of times a thread hit its MSHR cap. */
345 Stats::Vector<> mshr_cap_events;
346 /** The number of times software prefetches caused the MSHR to block. */
347 Stats::Vector<> soft_prefetch_mshr_full;
349 Stats::Scalar<> mshr_no_allocate_misses;
356 * Register stats for this object.
358 virtual void regStats();
361 typedef BaseCacheParams Params;
362 BaseCache(const Params *p);
368 * Query block size of a cache.
369 * @return The block size
371 int getBlockSize() const
377 Addr blockAlign(Addr addr) const { return (addr & ~(blkSize - 1)); }
380 MSHR *allocateMissBuffer(PacketPtr pkt, Tick time, bool requestBus)
382 assert(!pkt->req->isUncacheable());
383 return allocateBufferInternal(&mshrQueue,
384 blockAlign(pkt->getAddr()), blkSize,
385 pkt, time, requestBus);
388 MSHR *allocateWriteBuffer(PacketPtr pkt, Tick time, bool requestBus)
390 assert(pkt->isWrite() && !pkt->isRead());
391 return allocateBufferInternal(&writeBuffer,
392 pkt->getAddr(), pkt->getSize(),
393 pkt, time, requestBus);
396 MSHR *allocateUncachedReadBuffer(PacketPtr pkt, Tick time, bool requestBus)
398 assert(pkt->req->isUncacheable());
399 assert(pkt->isRead());
400 return allocateBufferInternal(&mshrQueue,
401 pkt->getAddr(), pkt->getSize(),
402 pkt, time, requestBus);
406 * Returns true if the cache is blocked for accesses.
414 * Marks the access path of the cache as blocked for the given cause. This
415 * also sets the blocked flag in the slave interface.
416 * @param cause The reason for the cache blocking.
418 void setBlocked(BlockedCause cause)
420 uint8_t flag = 1 << cause;
422 blocked_causes[cause]++;
423 blockedCycle = curTick;
424 cpuSidePort->setBlocked();
427 DPRINTF(Cache,"Blocking for cause %d, mask=%d\n", cause, blocked);
431 * Marks the cache as unblocked for the given cause. This also clears the
432 * blocked flags in the appropriate interfaces.
433 * @param cause The newly unblocked cause.
434 * @warning Calling this function can cause a blocked request on the bus to
435 * access the cache. The cache must be in a state to handle that request.
437 void clearBlocked(BlockedCause cause)
439 uint8_t flag = 1 << cause;
441 DPRINTF(Cache,"Unblocking for cause %d, mask=%d\n", cause, blocked);
443 blocked_cycles[cause] += curTick - blockedCycle;
444 cpuSidePort->clearBlocked();
449 * Request the master bus for the given cause and time.
450 * @param cause The reason for the request.
451 * @param time The time to make the request.
453 void requestMemSideBus(RequestCause cause, Tick time)
455 memSidePort->requestBus(cause, time);
459 * Clear the master bus request for the given cause.
460 * @param cause The request reason to clear.
462 void deassertMemSideBusRequest(RequestCause cause)
464 // Obsolete... we no longer signal bus requests explicitly so
465 // we can't deassert them. Leaving this in as a no-op since
466 // the prefetcher calls it to indicate that it no longer wants
467 // to request a prefetch, and someday that might be
468 // interesting again.
471 virtual unsigned int drain(Event *de);
473 virtual bool inCache(Addr addr) = 0;
475 virtual bool inMissQueue(Addr addr) = 0;
477 void incMissCount(PacketPtr pkt)
479 misses[pkt->cmdToIndex()][0/*pkt->req->threadId()*/]++;
484 exitSimLoop("A cache reached the maximum miss count");
490 #endif //__BASE_CACHE_HH__