2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
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14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Authors: Erik Hallnor
33 * Definition of BaseCache functions.
36 #include "mem/cache/base_cache.hh"
38 #include "cpu/base.hh"
42 BaseCache::CachePort::CachePort(const std::string
&_name
, BaseCache
*_cache
,
44 : Port(_name
), cache(_cache
), isCpuSide(_isCpuSide
)
47 //Start ports at null if more than one is created we should panic
53 BaseCache::CachePort::recvStatusChange(Port::Status status
)
55 cache
->recvStatusChange(status
, isCpuSide
);
59 BaseCache::CachePort::getDeviceAddressRanges(AddrRangeList
&resp
,
62 cache
->getAddressRanges(resp
, snoop
, isCpuSide
);
66 BaseCache::CachePort::deviceBlockSize()
68 return cache
->getBlockSize();
72 BaseCache::CachePort::recvTiming(Packet
*pkt
)
74 if (pkt
->isRequest() && blocked
)
76 DPRINTF(Cache
,"Scheduling a retry while blocked\n");
80 return cache
->doTimingAccess(pkt
, this, isCpuSide
);
84 BaseCache::CachePort::recvAtomic(Packet
*pkt
)
86 return cache
->doAtomicAccess(pkt
, isCpuSide
);
90 BaseCache::CachePort::recvFunctional(Packet
*pkt
)
92 cache
->doFunctionalAccess(pkt
, isCpuSide
);
96 BaseCache::CachePort::recvRetry()
99 if (!drainList
.empty()) {
100 //We have some responses to drain first
102 while (result
&& !drainList
.empty()) {
103 result
= sendTiming(drainList
.front());
105 drainList
.pop_front();
111 pkt
= cache
->getPacket();
112 MSHR
* mshr
= (MSHR
*)pkt
->senderState
;
113 bool success
= sendTiming(pkt
);
114 DPRINTF(Cache
, "Address %x was %s in sending the timing request\n",
115 pkt
->getAddr(), success
? "succesful" : "unsuccesful");
116 cache
->sendResult(pkt
, mshr
, success
);
117 if (success
&& cache
->doMasterRequest())
119 //Still more to issue, rerequest in 1 cycle
121 BaseCache::CacheEvent
* reqCpu
= new BaseCache::CacheEvent(this);
122 reqCpu
->schedule(curTick
+ 1);
127 //pkt = cache->getCoherencePacket();
128 //We save the packet, no reordering on CSHRS
130 bool success
= sendTiming(pkt
);
131 if (success
&& cache
->doSlaveRequest())
133 //Still more to issue, rerequest in 1 cycle
135 BaseCache::CacheEvent
* reqCpu
= new BaseCache::CacheEvent(this);
136 reqCpu
->schedule(curTick
+ 1);
143 BaseCache::CachePort::setBlocked()
146 DPRINTF(Cache
, "Cache Blocking\n");
148 //Clear the retry flag
149 mustSendRetry
= false;
153 BaseCache::CachePort::clearBlocked()
156 DPRINTF(Cache
, "Cache Unblocking\n");
160 DPRINTF(Cache
, "Cache Sending Retry\n");
161 mustSendRetry
= false;
166 BaseCache::CacheEvent::CacheEvent(CachePort
*_cachePort
)
167 : Event(&mainEventQueue
, CPU_Tick_Pri
), cachePort(_cachePort
)
169 this->setFlags(AutoDelete
);
173 BaseCache::CacheEvent::CacheEvent(CachePort
*_cachePort
, Packet
*_pkt
)
174 : Event(&mainEventQueue
, CPU_Tick_Pri
), cachePort(_cachePort
), pkt(_pkt
)
176 this->setFlags(AutoDelete
);
180 BaseCache::CacheEvent::process()
184 if (!cachePort
->isCpuSide
)
187 pkt
= cachePort
->cache
->getPacket();
188 MSHR
* mshr
= (MSHR
*) pkt
->senderState
;
189 bool success
= cachePort
->sendTiming(pkt
);
190 DPRINTF(Cache
, "Address %x was %s in sending the timing request\n",
191 pkt
->getAddr(), success
? "succesful" : "unsuccesful");
192 cachePort
->cache
->sendResult(pkt
, mshr
, success
);
193 if (success
&& cachePort
->cache
->doMasterRequest())
195 //Still more to issue, rerequest in 1 cycle
197 this->schedule(curTick
+1);
203 pkt
= cachePort
->cache
->getCoherencePacket();
204 bool success
= cachePort
->sendTiming(pkt
);
206 //Need to send on a retry
207 cachePort
->cshrRetry
= pkt
;
209 else if (cachePort
->cache
->doSlaveRequest())
211 //Still more to issue, rerequest in 1 cycle
213 this->schedule(curTick
+1);
219 //Know the packet to send
220 pkt
->result
= Packet::Success
;
221 pkt
->makeTimingResponse();
222 if (!cachePort
->drainList
.empty()) {
223 //Already blocked waiting for bus, just append
224 cachePort
->drainList
.push_back(pkt
);
226 else if (!cachePort
->sendTiming(pkt
)) {
227 //It failed, save it to list of drain events
228 cachePort
->drainList
.push_back(pkt
);
233 BaseCache::CacheEvent::description()
235 return "timing event\n";
239 BaseCache::getPort(const std::string
&if_name
, int idx
)
243 if(cpuSidePort
== NULL
)
244 cpuSidePort
= new CachePort(name() + "-cpu_side_port", this, true);
247 else if (if_name
== "functional")
249 if(cpuSidePort
== NULL
)
250 cpuSidePort
= new CachePort(name() + "-cpu_side_port", this, true);
253 else if (if_name
== "cpu_side")
255 if(cpuSidePort
== NULL
)
256 cpuSidePort
= new CachePort(name() + "-cpu_side_port", this, true);
259 else if (if_name
== "mem_side")
261 if (memSidePort
!= NULL
)
262 panic("Already have a mem side for this cache\n");
263 memSidePort
= new CachePort(name() + "-mem_side_port", this, false);
266 else panic("Port name %s unrecognized\n", if_name
);
272 if (!cpuSidePort
|| !memSidePort
)
273 panic("Cache not hooked up on both sides\n");
274 cpuSidePort
->sendStatusChange(Port::RangeChange
);
278 BaseCache::regStats()
280 Request
temp_req((Addr
) NULL
, 4, 0);
281 Packet::Command temp_cmd
= Packet::ReadReq
;
282 Packet
temp_pkt(&temp_req
, temp_cmd
, 0); //@todo FIx command strings so this isn't neccessary
283 temp_pkt
.allocate(); //Temp allocate, all need data
285 using namespace Stats
;
288 for (int access_idx
= 0; access_idx
< NUM_MEM_CMDS
; ++access_idx
) {
289 Packet::Command cmd
= (Packet::Command
)access_idx
;
290 const string
&cstr
= temp_pkt
.cmdIdxToString(cmd
);
293 .init(maxThreadsPerCPU
)
294 .name(name() + "." + cstr
+ "_hits")
295 .desc("number of " + cstr
+ " hits")
296 .flags(total
| nozero
| nonan
)
301 .name(name() + ".demand_hits")
302 .desc("number of demand (read+write) hits")
305 demandHits
= hits
[Packet::ReadReq
] + hits
[Packet::WriteReq
];
308 .name(name() + ".overall_hits")
309 .desc("number of overall hits")
312 overallHits
= demandHits
+ hits
[Packet::SoftPFReq
] + hits
[Packet::HardPFReq
]
313 + hits
[Packet::Writeback
];
316 for (int access_idx
= 0; access_idx
< NUM_MEM_CMDS
; ++access_idx
) {
317 Packet::Command cmd
= (Packet::Command
)access_idx
;
318 const string
&cstr
= temp_pkt
.cmdIdxToString(cmd
);
321 .init(maxThreadsPerCPU
)
322 .name(name() + "." + cstr
+ "_misses")
323 .desc("number of " + cstr
+ " misses")
324 .flags(total
| nozero
| nonan
)
329 .name(name() + ".demand_misses")
330 .desc("number of demand (read+write) misses")
333 demandMisses
= misses
[Packet::ReadReq
] + misses
[Packet::WriteReq
];
336 .name(name() + ".overall_misses")
337 .desc("number of overall misses")
340 overallMisses
= demandMisses
+ misses
[Packet::SoftPFReq
] +
341 misses
[Packet::HardPFReq
] + misses
[Packet::Writeback
];
343 // Miss latency statistics
344 for (int access_idx
= 0; access_idx
< NUM_MEM_CMDS
; ++access_idx
) {
345 Packet::Command cmd
= (Packet::Command
)access_idx
;
346 const string
&cstr
= temp_pkt
.cmdIdxToString(cmd
);
348 missLatency
[access_idx
]
349 .init(maxThreadsPerCPU
)
350 .name(name() + "." + cstr
+ "_miss_latency")
351 .desc("number of " + cstr
+ " miss cycles")
352 .flags(total
| nozero
| nonan
)
357 .name(name() + ".demand_miss_latency")
358 .desc("number of demand (read+write) miss cycles")
361 demandMissLatency
= missLatency
[Packet::ReadReq
] + missLatency
[Packet::WriteReq
];
364 .name(name() + ".overall_miss_latency")
365 .desc("number of overall miss cycles")
368 overallMissLatency
= demandMissLatency
+ missLatency
[Packet::SoftPFReq
] +
369 missLatency
[Packet::HardPFReq
];
372 for (int access_idx
= 0; access_idx
< NUM_MEM_CMDS
; ++access_idx
) {
373 Packet::Command cmd
= (Packet::Command
)access_idx
;
374 const string
&cstr
= temp_pkt
.cmdIdxToString(cmd
);
377 .name(name() + "." + cstr
+ "_accesses")
378 .desc("number of " + cstr
+ " accesses(hits+misses)")
379 .flags(total
| nozero
| nonan
)
382 accesses
[access_idx
] = hits
[access_idx
] + misses
[access_idx
];
386 .name(name() + ".demand_accesses")
387 .desc("number of demand (read+write) accesses")
390 demandAccesses
= demandHits
+ demandMisses
;
393 .name(name() + ".overall_accesses")
394 .desc("number of overall (read+write) accesses")
397 overallAccesses
= overallHits
+ overallMisses
;
399 // miss rate formulas
400 for (int access_idx
= 0; access_idx
< NUM_MEM_CMDS
; ++access_idx
) {
401 Packet::Command cmd
= (Packet::Command
)access_idx
;
402 const string
&cstr
= temp_pkt
.cmdIdxToString(cmd
);
405 .name(name() + "." + cstr
+ "_miss_rate")
406 .desc("miss rate for " + cstr
+ " accesses")
407 .flags(total
| nozero
| nonan
)
410 missRate
[access_idx
] = misses
[access_idx
] / accesses
[access_idx
];
414 .name(name() + ".demand_miss_rate")
415 .desc("miss rate for demand accesses")
418 demandMissRate
= demandMisses
/ demandAccesses
;
421 .name(name() + ".overall_miss_rate")
422 .desc("miss rate for overall accesses")
425 overallMissRate
= overallMisses
/ overallAccesses
;
427 // miss latency formulas
428 for (int access_idx
= 0; access_idx
< NUM_MEM_CMDS
; ++access_idx
) {
429 Packet::Command cmd
= (Packet::Command
)access_idx
;
430 const string
&cstr
= temp_pkt
.cmdIdxToString(cmd
);
432 avgMissLatency
[access_idx
]
433 .name(name() + "." + cstr
+ "_avg_miss_latency")
434 .desc("average " + cstr
+ " miss latency")
435 .flags(total
| nozero
| nonan
)
438 avgMissLatency
[access_idx
] =
439 missLatency
[access_idx
] / misses
[access_idx
];
443 .name(name() + ".demand_avg_miss_latency")
444 .desc("average overall miss latency")
447 demandAvgMissLatency
= demandMissLatency
/ demandMisses
;
449 overallAvgMissLatency
450 .name(name() + ".overall_avg_miss_latency")
451 .desc("average overall miss latency")
454 overallAvgMissLatency
= overallMissLatency
/ overallMisses
;
456 blocked_cycles
.init(NUM_BLOCKED_CAUSES
);
458 .name(name() + ".blocked_cycles")
459 .desc("number of cycles access was blocked")
460 .subname(Blocked_NoMSHRs
, "no_mshrs")
461 .subname(Blocked_NoTargets
, "no_targets")
465 blocked_causes
.init(NUM_BLOCKED_CAUSES
);
467 .name(name() + ".blocked")
468 .desc("number of cycles access was blocked")
469 .subname(Blocked_NoMSHRs
, "no_mshrs")
470 .subname(Blocked_NoTargets
, "no_targets")
474 .name(name() + ".avg_blocked_cycles")
475 .desc("average number of cycles each access was blocked")
476 .subname(Blocked_NoMSHRs
, "no_mshrs")
477 .subname(Blocked_NoTargets
, "no_targets")
480 avg_blocked
= blocked_cycles
/ blocked_causes
;
483 .name(name() + ".fast_writes")
484 .desc("number of fast writes performed")
488 .name(name() + ".cache_copies")
489 .desc("number of cache copies performed")