2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
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8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Authors: Erik Hallnor
33 * Definition of BaseCache functions.
36 #include "mem/cache/base_cache.hh"
38 #include "cpu/base.hh"
42 BaseCache::CachePort::CachePort(const std::string
&_name
, BaseCache
*_cache
,
44 : Port(_name
), cache(_cache
), isCpuSide(_isCpuSide
)
47 //Start ports at null if more than one is created we should panic
53 BaseCache::CachePort::recvStatusChange(Port::Status status
)
55 cache
->recvStatusChange(status
, isCpuSide
);
59 BaseCache::CachePort::getDeviceAddressRanges(AddrRangeList
&resp
,
62 cache
->getAddressRanges(resp
, snoop
, isCpuSide
);
66 BaseCache::CachePort::deviceBlockSize()
68 return cache
->getBlockSize();
72 BaseCache::CachePort::recvTiming(Packet
*pkt
)
74 if (pkt
->isRequest() && blocked
)
76 DPRINTF(Cache
,"Scheduling a retry while blocked\n");
80 return cache
->doTimingAccess(pkt
, this, isCpuSide
);
84 BaseCache::CachePort::recvAtomic(Packet
*pkt
)
86 return cache
->doAtomicAccess(pkt
, isCpuSide
);
90 BaseCache::CachePort::recvFunctional(Packet
*pkt
)
92 cache
->doFunctionalAccess(pkt
, isCpuSide
);
96 BaseCache::CachePort::recvRetry()
99 if (!drainList
.empty()) {
100 //We have some responses to drain first
102 while (result
&& !drainList
.empty()) {
103 result
= sendTiming(drainList
.front());
105 drainList
.pop_front();
111 pkt
= cache
->getPacket();
112 bool success
= sendTiming(pkt
);
113 DPRINTF(Cache
, "Address %x was %s in sending the timing request\n",
114 pkt
->getAddr(), success
? "succesful" : "unsuccesful");
115 cache
->sendResult(pkt
, success
);
116 if (success
&& cache
->doMasterRequest())
118 //Still more to issue, rerequest in 1 cycle
120 BaseCache::CacheEvent
* reqCpu
= new BaseCache::CacheEvent(this);
121 reqCpu
->schedule(curTick
+ 1);
126 pkt
= cache
->getCoherencePacket();
127 bool success
= sendTiming(pkt
);
128 if (success
&& cache
->doSlaveRequest())
130 //Still more to issue, rerequest in 1 cycle
132 BaseCache::CacheEvent
* reqCpu
= new BaseCache::CacheEvent(this);
133 reqCpu
->schedule(curTick
+ 1);
140 BaseCache::CachePort::setBlocked()
143 DPRINTF(Cache
, "Cache Blocking\n");
145 //Clear the retry flag
146 mustSendRetry
= false;
150 BaseCache::CachePort::clearBlocked()
153 DPRINTF(Cache
, "Cache Unblocking\n");
157 DPRINTF(Cache
, "Cache Sending Retry\n");
158 mustSendRetry
= false;
163 BaseCache::CacheEvent::CacheEvent(CachePort
*_cachePort
)
164 : Event(&mainEventQueue
, CPU_Tick_Pri
), cachePort(_cachePort
)
166 this->setFlags(AutoDelete
);
170 BaseCache::CacheEvent::CacheEvent(CachePort
*_cachePort
, Packet
*_pkt
)
171 : Event(&mainEventQueue
, CPU_Tick_Pri
), cachePort(_cachePort
), pkt(_pkt
)
173 this->setFlags(AutoDelete
);
177 BaseCache::CacheEvent::process()
181 if (!cachePort
->isCpuSide
)
184 pkt
= cachePort
->cache
->getPacket();
185 bool success
= cachePort
->sendTiming(pkt
);
186 DPRINTF(Cache
, "Address %x was %s in sending the timing request\n",
187 pkt
->getAddr(), success
? "succesful" : "unsuccesful");
188 cachePort
->cache
->sendResult(pkt
, success
);
189 if (success
&& cachePort
->cache
->doMasterRequest())
191 //Still more to issue, rerequest in 1 cycle
193 this->schedule(curTick
+1);
199 pkt
= cachePort
->cache
->getCoherencePacket();
200 bool success
= cachePort
->sendTiming(pkt
);
201 if (success
&& cachePort
->cache
->doSlaveRequest())
203 //Still more to issue, rerequest in 1 cycle
205 this->schedule(curTick
+1);
211 //Know the packet to send
212 pkt
->result
= Packet::Success
;
213 pkt
->makeTimingResponse();
214 if (!cachePort
->drainList
.empty()) {
215 //Already blocked waiting for bus, just append
216 cachePort
->drainList
.push_back(pkt
);
218 else if (!cachePort
->sendTiming(pkt
)) {
219 //It failed, save it to list of drain events
220 cachePort
->drainList
.push_back(pkt
);
225 BaseCache::CacheEvent::description()
227 return "timing event\n";
231 BaseCache::getPort(const std::string
&if_name
, int idx
)
235 if(cpuSidePort
== NULL
)
236 cpuSidePort
= new CachePort(name() + "-cpu_side_port", this, true);
239 else if (if_name
== "functional")
241 if(cpuSidePort
== NULL
)
242 cpuSidePort
= new CachePort(name() + "-cpu_side_port", this, true);
245 else if (if_name
== "cpu_side")
247 if(cpuSidePort
== NULL
)
248 cpuSidePort
= new CachePort(name() + "-cpu_side_port", this, true);
251 else if (if_name
== "mem_side")
253 if (memSidePort
!= NULL
)
254 panic("Already have a mem side for this cache\n");
255 memSidePort
= new CachePort(name() + "-mem_side_port", this, false);
258 else panic("Port name %s unrecognized\n", if_name
);
264 if (!cpuSidePort
|| !memSidePort
)
265 panic("Cache not hooked up on both sides\n");
266 cpuSidePort
->sendStatusChange(Port::RangeChange
);
270 BaseCache::regStats()
272 Request
temp_req((Addr
) NULL
, 4, 0);
273 Packet::Command temp_cmd
= Packet::ReadReq
;
274 Packet
temp_pkt(&temp_req
, temp_cmd
, 0); //@todo FIx command strings so this isn't neccessary
275 temp_pkt
.allocate(); //Temp allocate, all need data
277 using namespace Stats
;
280 for (int access_idx
= 0; access_idx
< NUM_MEM_CMDS
; ++access_idx
) {
281 Packet::Command cmd
= (Packet::Command
)access_idx
;
282 const string
&cstr
= temp_pkt
.cmdIdxToString(cmd
);
285 .init(maxThreadsPerCPU
)
286 .name(name() + "." + cstr
+ "_hits")
287 .desc("number of " + cstr
+ " hits")
288 .flags(total
| nozero
| nonan
)
293 .name(name() + ".demand_hits")
294 .desc("number of demand (read+write) hits")
297 demandHits
= hits
[Packet::ReadReq
] + hits
[Packet::WriteReq
];
300 .name(name() + ".overall_hits")
301 .desc("number of overall hits")
304 overallHits
= demandHits
+ hits
[Packet::SoftPFReq
] + hits
[Packet::HardPFReq
]
305 + hits
[Packet::Writeback
];
308 for (int access_idx
= 0; access_idx
< NUM_MEM_CMDS
; ++access_idx
) {
309 Packet::Command cmd
= (Packet::Command
)access_idx
;
310 const string
&cstr
= temp_pkt
.cmdIdxToString(cmd
);
313 .init(maxThreadsPerCPU
)
314 .name(name() + "." + cstr
+ "_misses")
315 .desc("number of " + cstr
+ " misses")
316 .flags(total
| nozero
| nonan
)
321 .name(name() + ".demand_misses")
322 .desc("number of demand (read+write) misses")
325 demandMisses
= misses
[Packet::ReadReq
] + misses
[Packet::WriteReq
];
328 .name(name() + ".overall_misses")
329 .desc("number of overall misses")
332 overallMisses
= demandMisses
+ misses
[Packet::SoftPFReq
] +
333 misses
[Packet::HardPFReq
] + misses
[Packet::Writeback
];
335 // Miss latency statistics
336 for (int access_idx
= 0; access_idx
< NUM_MEM_CMDS
; ++access_idx
) {
337 Packet::Command cmd
= (Packet::Command
)access_idx
;
338 const string
&cstr
= temp_pkt
.cmdIdxToString(cmd
);
340 missLatency
[access_idx
]
341 .init(maxThreadsPerCPU
)
342 .name(name() + "." + cstr
+ "_miss_latency")
343 .desc("number of " + cstr
+ " miss cycles")
344 .flags(total
| nozero
| nonan
)
349 .name(name() + ".demand_miss_latency")
350 .desc("number of demand (read+write) miss cycles")
353 demandMissLatency
= missLatency
[Packet::ReadReq
] + missLatency
[Packet::WriteReq
];
356 .name(name() + ".overall_miss_latency")
357 .desc("number of overall miss cycles")
360 overallMissLatency
= demandMissLatency
+ missLatency
[Packet::SoftPFReq
] +
361 missLatency
[Packet::HardPFReq
];
364 for (int access_idx
= 0; access_idx
< NUM_MEM_CMDS
; ++access_idx
) {
365 Packet::Command cmd
= (Packet::Command
)access_idx
;
366 const string
&cstr
= temp_pkt
.cmdIdxToString(cmd
);
369 .name(name() + "." + cstr
+ "_accesses")
370 .desc("number of " + cstr
+ " accesses(hits+misses)")
371 .flags(total
| nozero
| nonan
)
374 accesses
[access_idx
] = hits
[access_idx
] + misses
[access_idx
];
378 .name(name() + ".demand_accesses")
379 .desc("number of demand (read+write) accesses")
382 demandAccesses
= demandHits
+ demandMisses
;
385 .name(name() + ".overall_accesses")
386 .desc("number of overall (read+write) accesses")
389 overallAccesses
= overallHits
+ overallMisses
;
391 // miss rate formulas
392 for (int access_idx
= 0; access_idx
< NUM_MEM_CMDS
; ++access_idx
) {
393 Packet::Command cmd
= (Packet::Command
)access_idx
;
394 const string
&cstr
= temp_pkt
.cmdIdxToString(cmd
);
397 .name(name() + "." + cstr
+ "_miss_rate")
398 .desc("miss rate for " + cstr
+ " accesses")
399 .flags(total
| nozero
| nonan
)
402 missRate
[access_idx
] = misses
[access_idx
] / accesses
[access_idx
];
406 .name(name() + ".demand_miss_rate")
407 .desc("miss rate for demand accesses")
410 demandMissRate
= demandMisses
/ demandAccesses
;
413 .name(name() + ".overall_miss_rate")
414 .desc("miss rate for overall accesses")
417 overallMissRate
= overallMisses
/ overallAccesses
;
419 // miss latency formulas
420 for (int access_idx
= 0; access_idx
< NUM_MEM_CMDS
; ++access_idx
) {
421 Packet::Command cmd
= (Packet::Command
)access_idx
;
422 const string
&cstr
= temp_pkt
.cmdIdxToString(cmd
);
424 avgMissLatency
[access_idx
]
425 .name(name() + "." + cstr
+ "_avg_miss_latency")
426 .desc("average " + cstr
+ " miss latency")
427 .flags(total
| nozero
| nonan
)
430 avgMissLatency
[access_idx
] =
431 missLatency
[access_idx
] / misses
[access_idx
];
435 .name(name() + ".demand_avg_miss_latency")
436 .desc("average overall miss latency")
439 demandAvgMissLatency
= demandMissLatency
/ demandMisses
;
441 overallAvgMissLatency
442 .name(name() + ".overall_avg_miss_latency")
443 .desc("average overall miss latency")
446 overallAvgMissLatency
= overallMissLatency
/ overallMisses
;
448 blocked_cycles
.init(NUM_BLOCKED_CAUSES
);
450 .name(name() + ".blocked_cycles")
451 .desc("number of cycles access was blocked")
452 .subname(Blocked_NoMSHRs
, "no_mshrs")
453 .subname(Blocked_NoTargets
, "no_targets")
457 blocked_causes
.init(NUM_BLOCKED_CAUSES
);
459 .name(name() + ".blocked")
460 .desc("number of cycles access was blocked")
461 .subname(Blocked_NoMSHRs
, "no_mshrs")
462 .subname(Blocked_NoTargets
, "no_targets")
466 .name(name() + ".avg_blocked_cycles")
467 .desc("average number of cycles each access was blocked")
468 .subname(Blocked_NoMSHRs
, "no_mshrs")
469 .subname(Blocked_NoTargets
, "no_targets")
472 avg_blocked
= blocked_cycles
/ blocked_causes
;
475 .name(name() + ".fast_writes")
476 .desc("number of fast writes performed")
480 .name(name() + ".cache_copies")
481 .desc("number of cache copies performed")