src/mem/cache/base_cache.cc

   1 /*
   2  * Copyright (c) 2003-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Erik Hallnor
  29  */
  30
  31 /**
  32  * @file
  33  * Definition of BaseCache functions.
  34  */
  35
  36 #include "mem/cache/base_cache.hh"
  37 #include "cpu/smt.hh"
  38 #include "cpu/base.hh"
  39
  40 using namespace std;
  41
  42 BaseCache::CachePort::CachePort(const std::string &_name, BaseCache *_cache,
  43                                 bool _isCpuSide)
  44     : Port(_name), cache(_cache), isCpuSide(_isCpuSide)
  45 {
  46     blocked = false;
  47     cshrRetry = NULL;
  48     waitingOnRetry = false;
  49     //Start ports at null if more than one is created we should panic
  50     //cpuSidePort = NULL;
  51     //memSidePort = NULL;
  52 }
  53
  54 void
  55 BaseCache::CachePort::recvStatusChange(Port::Status status)
  56 {
  57     cache->recvStatusChange(status, isCpuSide);
  58 }
  59
  60 void
  61 BaseCache::CachePort::getDeviceAddressRanges(AddrRangeList &resp,
  62                                        AddrRangeList &snoop)
  63 {
  64     cache->getAddressRanges(resp, snoop, isCpuSide);
  65 }
  66
  67 int
  68 BaseCache::CachePort::deviceBlockSize()
  69 {
  70     return cache->getBlockSize();
  71 }
  72
  73 bool
  74 BaseCache::CachePort::recvTiming(Packet *pkt)
  75 {
  76     if (isCpuSide
  77         && !pkt->req->isUncacheable()
  78         && pkt->isInvalidate()
  79         && !pkt->isRead() && !pkt->isWrite()) {
  80         //Upgrade or Invalidate
  81         //Look into what happens if two slave caches on bus
  82         DPRINTF(Cache, "%s %x ? blk_addr: %x\n", pkt->cmdString(),
  83                 pkt->getAddr() & (((ULL(1))<<48)-1),
  84                 pkt->getAddr() & ~((Addr)cache->blkSize - 1));
  85
  86         assert(!(pkt->flags & SATISFIED));
  87         pkt->flags |= SATISFIED;
  88         //Invalidates/Upgrades need no response if they get the bus
  89         return true;
  90     }
  91
  92     if (pkt->isRequest() && blocked)
  93     {
  94         DPRINTF(Cache,"Scheduling a retry while blocked\n");
  95         mustSendRetry = true;
  96         return false;
  97     }
  98     return cache->doTimingAccess(pkt, this, isCpuSide);
  99 }
 100
 101 Tick
 102 BaseCache::CachePort::recvAtomic(Packet *pkt)
 103 {
 104     return cache->doAtomicAccess(pkt, isCpuSide);
 105 }
 106
 107 void
 108 BaseCache::CachePort::recvFunctional(Packet *pkt)
 109 {
 110     cache->doFunctionalAccess(pkt, isCpuSide);
 111 }
 112
 113 void
 114 BaseCache::CachePort::recvRetry()
 115 {
 116     Packet *pkt;
 117     assert(waitingOnRetry);
 118     if (!drainList.empty()) {
 119         DPRINTF(CachePort, "%s attempting to send a retry for response\n", name());
 120         //We have some responses to drain first
 121         if (sendTiming(drainList.front())) {
 122             DPRINTF(CachePort, "%s sucessful in sending a retry for response\n", name());
 123             drainList.pop_front();
 124             if (!drainList.empty() ||
 125                 !isCpuSide && cache->doMasterRequest() ||
 126                 isCpuSide && cache->doSlaveRequest()) {
 127
 128                 DPRINTF(CachePort, "%s has more responses/requests\n", name());
 129                 BaseCache::CacheEvent * reqCpu = new BaseCache::CacheEvent(this);
 130                 reqCpu->schedule(curTick + 1);
 131             }
 132             waitingOnRetry = false;
 133         }
 134     }
 135     else if (!isCpuSide)
 136     {
 137         DPRINTF(CachePort, "%s attempting to send a retry for MSHR\n", name());
 138         if (!cache->doMasterRequest()) {
 139             //This can happen if I am the owner of a block and see an upgrade
 140             //while the block was in my WB Buffers.  I just remove the
 141             //wb and de-assert the masterRequest
 142             waitingOnRetry = false;
 143             return;
 144         }
 145         pkt = cache->getPacket();
 146         MSHR* mshr = (MSHR*)pkt->senderState;
 147         bool success = sendTiming(pkt);
 148         DPRINTF(Cache, "Address %x was %s in sending the timing request\n",
 149                 pkt->getAddr(), success ? "succesful" : "unsuccesful");
 150         cache->sendResult(pkt, mshr, success);
 151         waitingOnRetry = !success;
 152         if (success && cache->doMasterRequest())
 153         {
 154             DPRINTF(CachePort, "%s has more requests\n", name());
 155             //Still more to issue, rerequest in 1 cycle
 156             pkt = NULL;
 157             BaseCache::CacheEvent * reqCpu = new BaseCache::CacheEvent(this);
 158             reqCpu->schedule(curTick + 1);
 159         }
 160     }
 161     else
 162     {
 163         assert(cshrRetry);
 164         //pkt = cache->getCoherencePacket();
 165         //We save the packet, no reordering on CSHRS
 166         pkt = cshrRetry;
 167         bool success = sendTiming(pkt);
 168         waitingOnRetry = !success;
 169         if (success && cache->doSlaveRequest())
 170         {
 171             //Still more to issue, rerequest in 1 cycle
 172             pkt = NULL;
 173             BaseCache::CacheEvent * reqCpu = new BaseCache::CacheEvent(this);
 174             reqCpu->schedule(curTick + 1);
 175             cshrRetry = NULL;
 176         }
 177     }
 178     if (waitingOnRetry) DPRINTF(CachePort, "%s STILL Waiting on retry\n", name());
 179     else DPRINTF(CachePort, "%s no longer waiting on retry\n", name());
 180     return;
 181 }
 182 void
 183 BaseCache::CachePort::setBlocked()
 184 {
 185     assert(!blocked);
 186     DPRINTF(Cache, "Cache Blocking\n");
 187     blocked = true;
 188     //Clear the retry flag
 189     mustSendRetry = false;
 190 }
 191
 192 void
 193 BaseCache::CachePort::clearBlocked()
 194 {
 195     assert(blocked);
 196     DPRINTF(Cache, "Cache Unblocking\n");
 197     blocked = false;
 198     if (mustSendRetry)
 199     {
 200         DPRINTF(Cache, "Cache Sending Retry\n");
 201         mustSendRetry = false;
 202         sendRetry();
 203     }
 204 }
 205
 206 BaseCache::CacheEvent::CacheEvent(CachePort *_cachePort)
 207     : Event(&mainEventQueue, CPU_Tick_Pri), cachePort(_cachePort)
 208 {
 209     this->setFlags(AutoDelete);
 210     pkt = NULL;
 211 }
 212
 213 BaseCache::CacheEvent::CacheEvent(CachePort *_cachePort, Packet *_pkt)
 214     : Event(&mainEventQueue, CPU_Tick_Pri), cachePort(_cachePort), pkt(_pkt)
 215 {
 216     this->setFlags(AutoDelete);
 217 }
 218
 219 void
 220 BaseCache::CacheEvent::process()
 221 {
 222     if (!pkt)
 223     {
 224         if (cachePort->waitingOnRetry) return;
 225        //We have some responses to drain first
 226         if (!cachePort->drainList.empty()) {
 227             DPRINTF(CachePort, "%s trying to drain a response\n", cachePort->name());
 228             if (cachePort->sendTiming(cachePort->drainList.front())) {
 229                 DPRINTF(CachePort, "%s drains a response succesfully\n", cachePort->name());
 230                 cachePort->drainList.pop_front();
 231                 if (!cachePort->drainList.empty() ||
 232                     !cachePort->isCpuSide && cachePort->cache->doMasterRequest() ||
 233                     cachePort->isCpuSide && cachePort->cache->doSlaveRequest()) {
 234
 235                     DPRINTF(CachePort, "%s still has outstanding bus reqs\n", cachePort->name());
 236                     this->schedule(curTick + 1);
 237                 }
 238             }
 239             else {
 240                 cachePort->waitingOnRetry = true;
 241                 DPRINTF(CachePort, "%s now waiting on a retry\n", cachePort->name());
 242             }
 243         }
 244         else if (!cachePort->isCpuSide)
 245         {            //MSHR
 246             DPRINTF(CachePort, "%s trying to send a MSHR request\n", cachePort->name());
 247             if (!cachePort->cache->doMasterRequest()) {
 248                 //This can happen if I am the owner of a block and see an upgrade
 249                 //while the block was in my WB Buffers.  I just remove the
 250                 //wb and de-assert the masterRequest
 251                 return;
 252             }
 253
 254             pkt = cachePort->cache->getPacket();
 255             MSHR* mshr = (MSHR*) pkt->senderState;
 256             bool success = cachePort->sendTiming(pkt);
 257             DPRINTF(Cache, "Address %x was %s in sending the timing request\n",
 258                     pkt->getAddr(), success ? "succesful" : "unsuccesful");
 259             cachePort->cache->sendResult(pkt, mshr, success);
 260             cachePort->waitingOnRetry = !success;
 261             if (cachePort->waitingOnRetry) DPRINTF(CachePort, "%s now waiting on a retry\n", cachePort->name());
 262             if (success && cachePort->cache->doMasterRequest())
 263             {
 264                 DPRINTF(CachePort, "%s still more MSHR requests to send\n", cachePort->name());
 265                 //Still more to issue, rerequest in 1 cycle
 266                 pkt = NULL;
 267                 this->schedule(curTick+1);
 268             }
 269         }
 270         else
 271         {
 272             assert(cachePort->cache->doSlaveRequest());
 273             //CSHR
 274             pkt = cachePort->cache->getCoherencePacket();
 275             bool success = cachePort->sendTiming(pkt);
 276             if (!success) {
 277                 //Need to send on a retry
 278                 cachePort->cshrRetry = pkt;
 279                 cachePort->waitingOnRetry = true;
 280             }
 281             else if (cachePort->cache->doSlaveRequest())
 282             {
 283                 //Still more to issue, rerequest in 1 cycle
 284                 pkt = NULL;
 285                 this->schedule(curTick+1);
 286             }
 287         }
 288         return;
 289     }
 290     //Response
 291     //Know the packet to send
 292     if (pkt->flags & NACKED_LINE)
 293         pkt->result = Packet::Nacked;
 294     else
 295         pkt->result = Packet::Success;
 296     pkt->makeTimingResponse();
 297     DPRINTF(CachePort, "%s attempting to send a response\n", cachePort->name());
 298     if (!cachePort->drainList.empty() || cachePort->waitingOnRetry) {
 299         //Already have a list, just append
 300         cachePort->drainList.push_back(pkt);
 301         DPRINTF(CachePort, "%s appending response onto drain list\n", cachePort->name());
 302     }
 303     else if (!cachePort->sendTiming(pkt)) {
 304         //It failed, save it to list of drain events
 305         DPRINTF(CachePort, "%s now waiting for a retry\n", cachePort->name());
 306         cachePort->drainList.push_back(pkt);
 307         cachePort->waitingOnRetry = true;
 308     }
 309 }
 310
 311 const char *
 312 BaseCache::CacheEvent::description()
 313 {
 314     return "timing event\n";
 315 }
 316
 317 Port*
 318 BaseCache::getPort(const std::string &if_name, int idx)
 319 {
 320     if (if_name == "")
 321     {
 322         if(cpuSidePort == NULL)
 323             cpuSidePort = new CachePort(name() + "-cpu_side_port", this, true);
 324         return cpuSidePort;
 325     }
 326     else if (if_name == "functional")
 327     {
 328         if(cpuSidePort == NULL)
 329             cpuSidePort = new CachePort(name() + "-cpu_side_port", this, true);
 330         return cpuSidePort;
 331     }
 332     else if (if_name == "cpu_side")
 333     {
 334         if(cpuSidePort == NULL)
 335             cpuSidePort = new CachePort(name() + "-cpu_side_port", this, true);
 336         return cpuSidePort;
 337     }
 338     else if (if_name == "mem_side")
 339     {
 340         if (memSidePort != NULL)
 341             panic("Already have a mem side for this cache\n");
 342         memSidePort = new CachePort(name() + "-mem_side_port", this, false);
 343         return memSidePort;
 344     }
 345     else panic("Port name %s unrecognized\n", if_name);
 346 }
 347
 348 void
 349 BaseCache::init()
 350 {
 351     if (!cpuSidePort || !memSidePort)
 352         panic("Cache not hooked up on both sides\n");
 353     cpuSidePort->sendStatusChange(Port::RangeChange);
 354 }
 355
 356 void
 357 BaseCache::regStats()
 358 {
 359     Request temp_req((Addr) NULL, 4, 0);
 360     Packet::Command temp_cmd = Packet::ReadReq;
 361     Packet temp_pkt(&temp_req, temp_cmd, 0);  //@todo FIx command strings so this isn't neccessary
 362     temp_pkt.allocate(); //Temp allocate, all need data
 363
 364     using namespace Stats;
 365
 366     // Hit statistics
 367     for (int access_idx = 0; access_idx < NUM_MEM_CMDS; ++access_idx) {
 368         Packet::Command cmd = (Packet::Command)access_idx;
 369         const string &cstr = temp_pkt.cmdIdxToString(cmd);
 370
 371         hits[access_idx]
 372             .init(maxThreadsPerCPU)
 373             .name(name() + "." + cstr + "_hits")
 374             .desc("number of " + cstr + " hits")
 375             .flags(total | nozero | nonan)
 376             ;
 377     }
 378
 379     demandHits
 380         .name(name() + ".demand_hits")
 381         .desc("number of demand (read+write) hits")
 382         .flags(total)
 383         ;
 384     demandHits = hits[Packet::ReadReq] + hits[Packet::WriteReq];
 385
 386     overallHits
 387         .name(name() + ".overall_hits")
 388         .desc("number of overall hits")
 389         .flags(total)
 390         ;
 391     overallHits = demandHits + hits[Packet::SoftPFReq] + hits[Packet::HardPFReq]
 392         + hits[Packet::Writeback];
 393
 394     // Miss statistics
 395     for (int access_idx = 0; access_idx < NUM_MEM_CMDS; ++access_idx) {
 396         Packet::Command cmd = (Packet::Command)access_idx;
 397         const string &cstr = temp_pkt.cmdIdxToString(cmd);
 398
 399         misses[access_idx]
 400             .init(maxThreadsPerCPU)
 401             .name(name() + "." + cstr + "_misses")
 402             .desc("number of " + cstr + " misses")
 403             .flags(total | nozero | nonan)
 404             ;
 405     }
 406
 407     demandMisses
 408         .name(name() + ".demand_misses")
 409         .desc("number of demand (read+write) misses")
 410         .flags(total)
 411         ;
 412     demandMisses = misses[Packet::ReadReq] + misses[Packet::WriteReq];
 413
 414     overallMisses
 415         .name(name() + ".overall_misses")
 416         .desc("number of overall misses")
 417         .flags(total)
 418         ;
 419     overallMisses = demandMisses + misses[Packet::SoftPFReq] +
 420         misses[Packet::HardPFReq] + misses[Packet::Writeback];
 421
 422     // Miss latency statistics
 423     for (int access_idx = 0; access_idx < NUM_MEM_CMDS; ++access_idx) {
 424         Packet::Command cmd = (Packet::Command)access_idx;
 425         const string &cstr = temp_pkt.cmdIdxToString(cmd);
 426
 427         missLatency[access_idx]
 428             .init(maxThreadsPerCPU)
 429             .name(name() + "." + cstr + "_miss_latency")
 430             .desc("number of " + cstr + " miss cycles")
 431             .flags(total | nozero | nonan)
 432             ;
 433     }
 434
 435     demandMissLatency
 436         .name(name() + ".demand_miss_latency")
 437         .desc("number of demand (read+write) miss cycles")
 438         .flags(total)
 439         ;
 440     demandMissLatency = missLatency[Packet::ReadReq] + missLatency[Packet::WriteReq];
 441
 442     overallMissLatency
 443         .name(name() + ".overall_miss_latency")
 444         .desc("number of overall miss cycles")
 445         .flags(total)
 446         ;
 447     overallMissLatency = demandMissLatency + missLatency[Packet::SoftPFReq] +
 448         missLatency[Packet::HardPFReq];
 449
 450     // access formulas
 451     for (int access_idx = 0; access_idx < NUM_MEM_CMDS; ++access_idx) {
 452         Packet::Command cmd = (Packet::Command)access_idx;
 453         const string &cstr = temp_pkt.cmdIdxToString(cmd);
 454
 455         accesses[access_idx]
 456             .name(name() + "." + cstr + "_accesses")
 457             .desc("number of " + cstr + " accesses(hits+misses)")
 458             .flags(total | nozero | nonan)
 459             ;
 460
 461         accesses[access_idx] = hits[access_idx] + misses[access_idx];
 462     }
 463
 464     demandAccesses
 465         .name(name() + ".demand_accesses")
 466         .desc("number of demand (read+write) accesses")
 467         .flags(total)
 468         ;
 469     demandAccesses = demandHits + demandMisses;
 470
 471     overallAccesses
 472         .name(name() + ".overall_accesses")
 473         .desc("number of overall (read+write) accesses")
 474         .flags(total)
 475         ;
 476     overallAccesses = overallHits + overallMisses;
 477
 478     // miss rate formulas
 479     for (int access_idx = 0; access_idx < NUM_MEM_CMDS; ++access_idx) {
 480         Packet::Command cmd = (Packet::Command)access_idx;
 481         const string &cstr = temp_pkt.cmdIdxToString(cmd);
 482
 483         missRate[access_idx]
 484             .name(name() + "." + cstr + "_miss_rate")
 485             .desc("miss rate for " + cstr + " accesses")
 486             .flags(total | nozero | nonan)
 487             ;
 488
 489         missRate[access_idx] = misses[access_idx] / accesses[access_idx];
 490     }
 491
 492     demandMissRate
 493         .name(name() + ".demand_miss_rate")
 494         .desc("miss rate for demand accesses")
 495         .flags(total)
 496         ;
 497     demandMissRate = demandMisses / demandAccesses;
 498
 499     overallMissRate
 500         .name(name() + ".overall_miss_rate")
 501         .desc("miss rate for overall accesses")
 502         .flags(total)
 503         ;
 504     overallMissRate = overallMisses / overallAccesses;
 505
 506     // miss latency formulas
 507     for (int access_idx = 0; access_idx < NUM_MEM_CMDS; ++access_idx) {
 508         Packet::Command cmd = (Packet::Command)access_idx;
 509         const string &cstr = temp_pkt.cmdIdxToString(cmd);
 510
 511         avgMissLatency[access_idx]
 512             .name(name() + "." + cstr + "_avg_miss_latency")
 513             .desc("average " + cstr + " miss latency")
 514             .flags(total | nozero | nonan)
 515             ;
 516
 517         avgMissLatency[access_idx] =
 518             missLatency[access_idx] / misses[access_idx];
 519     }
 520
 521     demandAvgMissLatency
 522         .name(name() + ".demand_avg_miss_latency")
 523         .desc("average overall miss latency")
 524         .flags(total)
 525         ;
 526     demandAvgMissLatency = demandMissLatency / demandMisses;
 527
 528     overallAvgMissLatency
 529         .name(name() + ".overall_avg_miss_latency")
 530         .desc("average overall miss latency")
 531         .flags(total)
 532         ;
 533     overallAvgMissLatency = overallMissLatency / overallMisses;
 534
 535     blocked_cycles.init(NUM_BLOCKED_CAUSES);
 536     blocked_cycles
 537         .name(name() + ".blocked_cycles")
 538         .desc("number of cycles access was blocked")
 539         .subname(Blocked_NoMSHRs, "no_mshrs")
 540         .subname(Blocked_NoTargets, "no_targets")
 541         ;
 542
 543
 544     blocked_causes.init(NUM_BLOCKED_CAUSES);
 545     blocked_causes
 546         .name(name() + ".blocked")
 547         .desc("number of cycles access was blocked")
 548         .subname(Blocked_NoMSHRs, "no_mshrs")
 549         .subname(Blocked_NoTargets, "no_targets")
 550         ;
 551
 552     avg_blocked
 553         .name(name() + ".avg_blocked_cycles")
 554         .desc("average number of cycles each access was blocked")
 555         .subname(Blocked_NoMSHRs, "no_mshrs")
 556         .subname(Blocked_NoTargets, "no_targets")
 557         ;
 558
 559     avg_blocked = blocked_cycles / blocked_causes;
 560
 561     fastWrites
 562         .name(name() + ".fast_writes")
 563         .desc("number of fast writes performed")
 564         ;
 565
 566     cacheCopies
 567         .name(name() + ".cache_copies")
 568         .desc("number of cache copies performed")
 569         ;
 570
 571 }