2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Authors: Erik Hallnor
33 * Definition of BaseCache functions.
36 #include "mem/cache/base_cache.hh"
38 #include "cpu/base.hh"
42 BaseCache::CachePort::CachePort(const std::string
&_name
, BaseCache
*_cache
,
44 : Port(_name
), cache(_cache
), isCpuSide(_isCpuSide
)
47 //Start ports at null if more than one is created we should panic
53 BaseCache::CachePort::recvStatusChange(Port::Status status
)
55 cache
->recvStatusChange(status
, isCpuSide
);
59 BaseCache::CachePort::getDeviceAddressRanges(AddrRangeList
&resp
,
62 cache
->getAddressRanges(resp
, snoop
, isCpuSide
);
66 BaseCache::CachePort::deviceBlockSize()
68 return cache
->getBlockSize();
72 BaseCache::CachePort::recvTiming(Packet
*pkt
)
76 DPRINTF(Cache
,"Scheduling a retry while blocked\n");
80 return cache
->doTimingAccess(pkt
, this, isCpuSide
);
84 BaseCache::CachePort::recvAtomic(Packet
*pkt
)
86 return cache
->doAtomicAccess(pkt
, isCpuSide
);
90 BaseCache::CachePort::recvFunctional(Packet
*pkt
)
92 cache
->doFunctionalAccess(pkt
, isCpuSide
);
96 BaseCache::CachePort::recvRetry()
102 pkt
= cache
->getPacket();
103 bool success
= sendTiming(pkt
);
104 DPRINTF(Cache
, "Address %x was %s in sending the timing request\n",
105 pkt
->getAddr(), success
? "succesful" : "unsuccesful");
106 cache
->sendResult(pkt
, success
);
107 if (success
&& cache
->doMasterRequest())
109 //Still more to issue, rerequest in 1 cycle
111 BaseCache::CacheEvent
* reqCpu
= new BaseCache::CacheEvent(this);
112 reqCpu
->schedule(curTick
+ 1);
117 pkt
= cache
->getCoherencePacket();
118 bool success
= sendTiming(pkt
);
119 if (success
&& cache
->doSlaveRequest())
121 //Still more to issue, rerequest in 1 cycle
123 BaseCache::CacheEvent
* reqCpu
= new BaseCache::CacheEvent(this);
124 reqCpu
->schedule(curTick
+ 1);
131 BaseCache::CachePort::setBlocked()
134 DPRINTF(Cache
, "Cache Blocking\n");
136 //Clear the retry flag
137 mustSendRetry
= false;
141 BaseCache::CachePort::clearBlocked()
144 DPRINTF(Cache
, "Cache Unblocking\n");
148 DPRINTF(Cache
, "Cache Sending Retry\n");
149 mustSendRetry
= false;
154 BaseCache::CacheEvent::CacheEvent(CachePort
*_cachePort
)
155 : Event(&mainEventQueue
, CPU_Tick_Pri
), cachePort(_cachePort
)
157 this->setFlags(AutoDelete
);
161 BaseCache::CacheEvent::CacheEvent(CachePort
*_cachePort
, Packet
*_pkt
)
162 : Event(&mainEventQueue
, CPU_Tick_Pri
), cachePort(_cachePort
), pkt(_pkt
)
164 this->setFlags(AutoDelete
);
168 BaseCache::CacheEvent::process()
172 if (!cachePort
->isCpuSide
)
175 pkt
= cachePort
->cache
->getPacket();
176 bool success
= cachePort
->sendTiming(pkt
);
177 DPRINTF(Cache
, "Address %x was %s in sending the timing request\n",
178 pkt
->getAddr(), success
? "succesful" : "unsuccesful");
179 cachePort
->cache
->sendResult(pkt
, success
);
180 if (success
&& cachePort
->cache
->doMasterRequest())
182 //Still more to issue, rerequest in 1 cycle
184 this->schedule(curTick
+1);
190 pkt
= cachePort
->cache
->getCoherencePacket();
191 bool success
= cachePort
->sendTiming(pkt
);
192 if (success
&& cachePort
->cache
->doSlaveRequest())
194 //Still more to issue, rerequest in 1 cycle
196 this->schedule(curTick
+1);
202 //Know the packet to send, no need to mark in service (must succed)
203 assert(cachePort
->sendTiming(pkt
));
207 BaseCache::CacheEvent::description()
209 return "timing event\n";
213 BaseCache::getPort(const std::string
&if_name
, int idx
)
217 if(cpuSidePort
== NULL
)
218 cpuSidePort
= new CachePort(name() + "-cpu_side_port", this, true);
221 else if (if_name
== "functional")
223 if(cpuSidePort
== NULL
)
224 cpuSidePort
= new CachePort(name() + "-cpu_side_port", this, true);
227 else if (if_name
== "cpu_side")
229 if(cpuSidePort
== NULL
)
230 cpuSidePort
= new CachePort(name() + "-cpu_side_port", this, true);
233 else if (if_name
== "mem_side")
235 if (memSidePort
!= NULL
)
236 panic("Already have a mem side for this cache\n");
237 memSidePort
= new CachePort(name() + "-mem_side_port", this, false);
240 else panic("Port name %s unrecognized\n", if_name
);
246 if (!cpuSidePort
|| !memSidePort
)
247 panic("Cache not hooked up on both sides\n");
248 cpuSidePort
->sendStatusChange(Port::RangeChange
);
252 BaseCache::regStats()
254 Request
temp_req((Addr
) NULL
, 4, 0);
255 Packet::Command temp_cmd
= Packet::ReadReq
;
256 Packet
temp_pkt(&temp_req
, temp_cmd
, 0); //@todo FIx command strings so this isn't neccessary
257 temp_pkt
.allocate(); //Temp allocate, all need data
259 using namespace Stats
;
262 for (int access_idx
= 0; access_idx
< NUM_MEM_CMDS
; ++access_idx
) {
263 Packet::Command cmd
= (Packet::Command
)access_idx
;
264 const string
&cstr
= temp_pkt
.cmdIdxToString(cmd
);
267 .init(maxThreadsPerCPU
)
268 .name(name() + "." + cstr
+ "_hits")
269 .desc("number of " + cstr
+ " hits")
270 .flags(total
| nozero
| nonan
)
275 .name(name() + ".demand_hits")
276 .desc("number of demand (read+write) hits")
279 demandHits
= hits
[Packet::ReadReq
] + hits
[Packet::WriteReq
];
282 .name(name() + ".overall_hits")
283 .desc("number of overall hits")
286 overallHits
= demandHits
+ hits
[Packet::SoftPFReq
] + hits
[Packet::HardPFReq
]
287 + hits
[Packet::Writeback
];
290 for (int access_idx
= 0; access_idx
< NUM_MEM_CMDS
; ++access_idx
) {
291 Packet::Command cmd
= (Packet::Command
)access_idx
;
292 const string
&cstr
= temp_pkt
.cmdIdxToString(cmd
);
295 .init(maxThreadsPerCPU
)
296 .name(name() + "." + cstr
+ "_misses")
297 .desc("number of " + cstr
+ " misses")
298 .flags(total
| nozero
| nonan
)
303 .name(name() + ".demand_misses")
304 .desc("number of demand (read+write) misses")
307 demandMisses
= misses
[Packet::ReadReq
] + misses
[Packet::WriteReq
];
310 .name(name() + ".overall_misses")
311 .desc("number of overall misses")
314 overallMisses
= demandMisses
+ misses
[Packet::SoftPFReq
] +
315 misses
[Packet::HardPFReq
] + misses
[Packet::Writeback
];
317 // Miss latency statistics
318 for (int access_idx
= 0; access_idx
< NUM_MEM_CMDS
; ++access_idx
) {
319 Packet::Command cmd
= (Packet::Command
)access_idx
;
320 const string
&cstr
= temp_pkt
.cmdIdxToString(cmd
);
322 missLatency
[access_idx
]
323 .init(maxThreadsPerCPU
)
324 .name(name() + "." + cstr
+ "_miss_latency")
325 .desc("number of " + cstr
+ " miss cycles")
326 .flags(total
| nozero
| nonan
)
331 .name(name() + ".demand_miss_latency")
332 .desc("number of demand (read+write) miss cycles")
335 demandMissLatency
= missLatency
[Packet::ReadReq
] + missLatency
[Packet::WriteReq
];
338 .name(name() + ".overall_miss_latency")
339 .desc("number of overall miss cycles")
342 overallMissLatency
= demandMissLatency
+ missLatency
[Packet::SoftPFReq
] +
343 missLatency
[Packet::HardPFReq
];
346 for (int access_idx
= 0; access_idx
< NUM_MEM_CMDS
; ++access_idx
) {
347 Packet::Command cmd
= (Packet::Command
)access_idx
;
348 const string
&cstr
= temp_pkt
.cmdIdxToString(cmd
);
351 .name(name() + "." + cstr
+ "_accesses")
352 .desc("number of " + cstr
+ " accesses(hits+misses)")
353 .flags(total
| nozero
| nonan
)
356 accesses
[access_idx
] = hits
[access_idx
] + misses
[access_idx
];
360 .name(name() + ".demand_accesses")
361 .desc("number of demand (read+write) accesses")
364 demandAccesses
= demandHits
+ demandMisses
;
367 .name(name() + ".overall_accesses")
368 .desc("number of overall (read+write) accesses")
371 overallAccesses
= overallHits
+ overallMisses
;
373 // miss rate formulas
374 for (int access_idx
= 0; access_idx
< NUM_MEM_CMDS
; ++access_idx
) {
375 Packet::Command cmd
= (Packet::Command
)access_idx
;
376 const string
&cstr
= temp_pkt
.cmdIdxToString(cmd
);
379 .name(name() + "." + cstr
+ "_miss_rate")
380 .desc("miss rate for " + cstr
+ " accesses")
381 .flags(total
| nozero
| nonan
)
384 missRate
[access_idx
] = misses
[access_idx
] / accesses
[access_idx
];
388 .name(name() + ".demand_miss_rate")
389 .desc("miss rate for demand accesses")
392 demandMissRate
= demandMisses
/ demandAccesses
;
395 .name(name() + ".overall_miss_rate")
396 .desc("miss rate for overall accesses")
399 overallMissRate
= overallMisses
/ overallAccesses
;
401 // miss latency formulas
402 for (int access_idx
= 0; access_idx
< NUM_MEM_CMDS
; ++access_idx
) {
403 Packet::Command cmd
= (Packet::Command
)access_idx
;
404 const string
&cstr
= temp_pkt
.cmdIdxToString(cmd
);
406 avgMissLatency
[access_idx
]
407 .name(name() + "." + cstr
+ "_avg_miss_latency")
408 .desc("average " + cstr
+ " miss latency")
409 .flags(total
| nozero
| nonan
)
412 avgMissLatency
[access_idx
] =
413 missLatency
[access_idx
] / misses
[access_idx
];
417 .name(name() + ".demand_avg_miss_latency")
418 .desc("average overall miss latency")
421 demandAvgMissLatency
= demandMissLatency
/ demandMisses
;
423 overallAvgMissLatency
424 .name(name() + ".overall_avg_miss_latency")
425 .desc("average overall miss latency")
428 overallAvgMissLatency
= overallMissLatency
/ overallMisses
;
430 blocked_cycles
.init(NUM_BLOCKED_CAUSES
);
432 .name(name() + ".blocked_cycles")
433 .desc("number of cycles access was blocked")
434 .subname(Blocked_NoMSHRs
, "no_mshrs")
435 .subname(Blocked_NoTargets
, "no_targets")
439 blocked_causes
.init(NUM_BLOCKED_CAUSES
);
441 .name(name() + ".blocked")
442 .desc("number of cycles access was blocked")
443 .subname(Blocked_NoMSHRs
, "no_mshrs")
444 .subname(Blocked_NoTargets
, "no_targets")
448 .name(name() + ".avg_blocked_cycles")
449 .desc("average number of cycles each access was blocked")
450 .subname(Blocked_NoMSHRs
, "no_mshrs")
451 .subname(Blocked_NoTargets
, "no_targets")
454 avg_blocked
= blocked_cycles
/ blocked_causes
;
457 .name(name() + ".fast_writes")
458 .desc("number of fast writes performed")
462 .name(name() + ".cache_copies")
463 .desc("number of cache copies performed")