2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
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14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Authors: Erik Hallnor
33 * Definition of BaseCache functions.
36 #include "mem/cache/base_cache.hh"
38 #include "cpu/base.hh"
42 BaseCache::CachePort::CachePort(const std::string
&_name
, BaseCache
*_cache
,
44 : Port(_name
), cache(_cache
), isCpuSide(_isCpuSide
)
47 //Start ports at null if more than one is created we should panic
53 BaseCache::CachePort::recvStatusChange(Port::Status status
)
55 cache
->recvStatusChange(status
, isCpuSide
);
59 BaseCache::CachePort::getDeviceAddressRanges(AddrRangeList
&resp
,
62 cache
->getAddressRanges(resp
, snoop
, isCpuSide
);
66 BaseCache::CachePort::deviceBlockSize()
68 return cache
->getBlockSize();
72 BaseCache::CachePort::recvTiming(Packet
*pkt
)
74 if (pkt
->isRequest() && blocked
)
76 DPRINTF(Cache
,"Scheduling a retry while blocked\n");
80 return cache
->doTimingAccess(pkt
, this, isCpuSide
);
84 BaseCache::CachePort::recvAtomic(Packet
*pkt
)
86 return cache
->doAtomicAccess(pkt
, isCpuSide
);
90 BaseCache::CachePort::recvFunctional(Packet
*pkt
)
92 cache
->doFunctionalAccess(pkt
, isCpuSide
);
96 BaseCache::CachePort::recvRetry()
99 if (!drainList
.empty()) {
100 //We have some responses to drain first
102 while (result
&& !drainList
.empty()) {
103 result
= sendTiming(drainList
.front());
105 drainList
.pop_front();
110 pkt
= cache
->getPacket();
111 MSHR
* mshr
= (MSHR
*)pkt
->senderState
;
112 bool success
= sendTiming(pkt
);
113 DPRINTF(Cache
, "Address %x was %s in sending the timing request\n",
114 pkt
->getAddr(), success
? "succesful" : "unsuccesful");
115 cache
->sendResult(pkt
, mshr
, success
);
116 if (success
&& cache
->doMasterRequest())
118 //Still more to issue, rerequest in 1 cycle
120 BaseCache::CacheEvent
* reqCpu
= new BaseCache::CacheEvent(this);
121 reqCpu
->schedule(curTick
+ 1);
126 //pkt = cache->getCoherencePacket();
127 //We save the packet, no reordering on CSHRS
129 bool success
= sendTiming(pkt
);
130 if (success
&& cache
->doSlaveRequest())
132 //Still more to issue, rerequest in 1 cycle
134 BaseCache::CacheEvent
* reqCpu
= new BaseCache::CacheEvent(this);
135 reqCpu
->schedule(curTick
+ 1);
142 BaseCache::CachePort::setBlocked()
145 DPRINTF(Cache
, "Cache Blocking\n");
147 //Clear the retry flag
148 mustSendRetry
= false;
152 BaseCache::CachePort::clearBlocked()
155 DPRINTF(Cache
, "Cache Unblocking\n");
159 DPRINTF(Cache
, "Cache Sending Retry\n");
160 mustSendRetry
= false;
165 BaseCache::CacheEvent::CacheEvent(CachePort
*_cachePort
)
166 : Event(&mainEventQueue
, CPU_Tick_Pri
), cachePort(_cachePort
)
168 this->setFlags(AutoDelete
);
172 BaseCache::CacheEvent::CacheEvent(CachePort
*_cachePort
, Packet
*_pkt
)
173 : Event(&mainEventQueue
, CPU_Tick_Pri
), cachePort(_cachePort
), pkt(_pkt
)
175 this->setFlags(AutoDelete
);
179 BaseCache::CacheEvent::process()
183 if (!cachePort
->isCpuSide
)
186 pkt
= cachePort
->cache
->getPacket();
187 MSHR
* mshr
= (MSHR
*) pkt
->senderState
;
188 bool success
= cachePort
->sendTiming(pkt
);
189 DPRINTF(Cache
, "Address %x was %s in sending the timing request\n",
190 pkt
->getAddr(), success
? "succesful" : "unsuccesful");
191 cachePort
->cache
->sendResult(pkt
, mshr
, success
);
192 if (success
&& cachePort
->cache
->doMasterRequest())
194 //Still more to issue, rerequest in 1 cycle
196 this->schedule(curTick
+1);
202 pkt
= cachePort
->cache
->getCoherencePacket();
203 bool success
= cachePort
->sendTiming(pkt
);
205 //Need to send on a retry
206 cachePort
->cshrRetry
= pkt
;
208 else if (cachePort
->cache
->doSlaveRequest())
210 //Still more to issue, rerequest in 1 cycle
212 this->schedule(curTick
+1);
218 //Know the packet to send
219 pkt
->result
= Packet::Success
;
220 pkt
->makeTimingResponse();
221 if (!cachePort
->drainList
.empty()) {
222 //Already blocked waiting for bus, just append
223 cachePort
->drainList
.push_back(pkt
);
225 else if (!cachePort
->sendTiming(pkt
)) {
226 //It failed, save it to list of drain events
227 cachePort
->drainList
.push_back(pkt
);
232 BaseCache::CacheEvent::description()
234 return "timing event\n";
238 BaseCache::getPort(const std::string
&if_name
, int idx
)
242 if(cpuSidePort
== NULL
)
243 cpuSidePort
= new CachePort(name() + "-cpu_side_port", this, true);
246 else if (if_name
== "functional")
248 if(cpuSidePort
== NULL
)
249 cpuSidePort
= new CachePort(name() + "-cpu_side_port", this, true);
252 else if (if_name
== "cpu_side")
254 if(cpuSidePort
== NULL
)
255 cpuSidePort
= new CachePort(name() + "-cpu_side_port", this, true);
258 else if (if_name
== "mem_side")
260 if (memSidePort
!= NULL
)
261 panic("Already have a mem side for this cache\n");
262 memSidePort
= new CachePort(name() + "-mem_side_port", this, false);
265 else panic("Port name %s unrecognized\n", if_name
);
271 if (!cpuSidePort
|| !memSidePort
)
272 panic("Cache not hooked up on both sides\n");
273 cpuSidePort
->sendStatusChange(Port::RangeChange
);
277 BaseCache::regStats()
279 Request
temp_req((Addr
) NULL
, 4, 0);
280 Packet::Command temp_cmd
= Packet::ReadReq
;
281 Packet
temp_pkt(&temp_req
, temp_cmd
, 0); //@todo FIx command strings so this isn't neccessary
282 temp_pkt
.allocate(); //Temp allocate, all need data
284 using namespace Stats
;
287 for (int access_idx
= 0; access_idx
< NUM_MEM_CMDS
; ++access_idx
) {
288 Packet::Command cmd
= (Packet::Command
)access_idx
;
289 const string
&cstr
= temp_pkt
.cmdIdxToString(cmd
);
292 .init(maxThreadsPerCPU
)
293 .name(name() + "." + cstr
+ "_hits")
294 .desc("number of " + cstr
+ " hits")
295 .flags(total
| nozero
| nonan
)
300 .name(name() + ".demand_hits")
301 .desc("number of demand (read+write) hits")
304 demandHits
= hits
[Packet::ReadReq
] + hits
[Packet::WriteReq
];
307 .name(name() + ".overall_hits")
308 .desc("number of overall hits")
311 overallHits
= demandHits
+ hits
[Packet::SoftPFReq
] + hits
[Packet::HardPFReq
]
312 + hits
[Packet::Writeback
];
315 for (int access_idx
= 0; access_idx
< NUM_MEM_CMDS
; ++access_idx
) {
316 Packet::Command cmd
= (Packet::Command
)access_idx
;
317 const string
&cstr
= temp_pkt
.cmdIdxToString(cmd
);
320 .init(maxThreadsPerCPU
)
321 .name(name() + "." + cstr
+ "_misses")
322 .desc("number of " + cstr
+ " misses")
323 .flags(total
| nozero
| nonan
)
328 .name(name() + ".demand_misses")
329 .desc("number of demand (read+write) misses")
332 demandMisses
= misses
[Packet::ReadReq
] + misses
[Packet::WriteReq
];
335 .name(name() + ".overall_misses")
336 .desc("number of overall misses")
339 overallMisses
= demandMisses
+ misses
[Packet::SoftPFReq
] +
340 misses
[Packet::HardPFReq
] + misses
[Packet::Writeback
];
342 // Miss latency statistics
343 for (int access_idx
= 0; access_idx
< NUM_MEM_CMDS
; ++access_idx
) {
344 Packet::Command cmd
= (Packet::Command
)access_idx
;
345 const string
&cstr
= temp_pkt
.cmdIdxToString(cmd
);
347 missLatency
[access_idx
]
348 .init(maxThreadsPerCPU
)
349 .name(name() + "." + cstr
+ "_miss_latency")
350 .desc("number of " + cstr
+ " miss cycles")
351 .flags(total
| nozero
| nonan
)
356 .name(name() + ".demand_miss_latency")
357 .desc("number of demand (read+write) miss cycles")
360 demandMissLatency
= missLatency
[Packet::ReadReq
] + missLatency
[Packet::WriteReq
];
363 .name(name() + ".overall_miss_latency")
364 .desc("number of overall miss cycles")
367 overallMissLatency
= demandMissLatency
+ missLatency
[Packet::SoftPFReq
] +
368 missLatency
[Packet::HardPFReq
];
371 for (int access_idx
= 0; access_idx
< NUM_MEM_CMDS
; ++access_idx
) {
372 Packet::Command cmd
= (Packet::Command
)access_idx
;
373 const string
&cstr
= temp_pkt
.cmdIdxToString(cmd
);
376 .name(name() + "." + cstr
+ "_accesses")
377 .desc("number of " + cstr
+ " accesses(hits+misses)")
378 .flags(total
| nozero
| nonan
)
381 accesses
[access_idx
] = hits
[access_idx
] + misses
[access_idx
];
385 .name(name() + ".demand_accesses")
386 .desc("number of demand (read+write) accesses")
389 demandAccesses
= demandHits
+ demandMisses
;
392 .name(name() + ".overall_accesses")
393 .desc("number of overall (read+write) accesses")
396 overallAccesses
= overallHits
+ overallMisses
;
398 // miss rate formulas
399 for (int access_idx
= 0; access_idx
< NUM_MEM_CMDS
; ++access_idx
) {
400 Packet::Command cmd
= (Packet::Command
)access_idx
;
401 const string
&cstr
= temp_pkt
.cmdIdxToString(cmd
);
404 .name(name() + "." + cstr
+ "_miss_rate")
405 .desc("miss rate for " + cstr
+ " accesses")
406 .flags(total
| nozero
| nonan
)
409 missRate
[access_idx
] = misses
[access_idx
] / accesses
[access_idx
];
413 .name(name() + ".demand_miss_rate")
414 .desc("miss rate for demand accesses")
417 demandMissRate
= demandMisses
/ demandAccesses
;
420 .name(name() + ".overall_miss_rate")
421 .desc("miss rate for overall accesses")
424 overallMissRate
= overallMisses
/ overallAccesses
;
426 // miss latency formulas
427 for (int access_idx
= 0; access_idx
< NUM_MEM_CMDS
; ++access_idx
) {
428 Packet::Command cmd
= (Packet::Command
)access_idx
;
429 const string
&cstr
= temp_pkt
.cmdIdxToString(cmd
);
431 avgMissLatency
[access_idx
]
432 .name(name() + "." + cstr
+ "_avg_miss_latency")
433 .desc("average " + cstr
+ " miss latency")
434 .flags(total
| nozero
| nonan
)
437 avgMissLatency
[access_idx
] =
438 missLatency
[access_idx
] / misses
[access_idx
];
442 .name(name() + ".demand_avg_miss_latency")
443 .desc("average overall miss latency")
446 demandAvgMissLatency
= demandMissLatency
/ demandMisses
;
448 overallAvgMissLatency
449 .name(name() + ".overall_avg_miss_latency")
450 .desc("average overall miss latency")
453 overallAvgMissLatency
= overallMissLatency
/ overallMisses
;
455 blocked_cycles
.init(NUM_BLOCKED_CAUSES
);
457 .name(name() + ".blocked_cycles")
458 .desc("number of cycles access was blocked")
459 .subname(Blocked_NoMSHRs
, "no_mshrs")
460 .subname(Blocked_NoTargets
, "no_targets")
464 blocked_causes
.init(NUM_BLOCKED_CAUSES
);
466 .name(name() + ".blocked")
467 .desc("number of cycles access was blocked")
468 .subname(Blocked_NoMSHRs
, "no_mshrs")
469 .subname(Blocked_NoTargets
, "no_targets")
473 .name(name() + ".avg_blocked_cycles")
474 .desc("average number of cycles each access was blocked")
475 .subname(Blocked_NoMSHRs
, "no_mshrs")
476 .subname(Blocked_NoTargets
, "no_targets")
479 avg_blocked
= blocked_cycles
/ blocked_causes
;
482 .name(name() + ".fast_writes")
483 .desc("number of fast writes performed")
487 .name(name() + ".cache_copies")
488 .desc("number of cache copies performed")