src/mem/cache/base_cache.cc

   1 /*
   2  * Copyright (c) 2003-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Erik Hallnor
  29  */
  30
  31 /**
  32  * @file
  33  * Definition of BaseCache functions.
  34  */
  35
  36 #include "mem/cache/base_cache.hh"
  37 #include "cpu/smt.hh"
  38 #include "cpu/base.hh"
  39
  40 using namespace std;
  41
  42 BaseCache::CachePort::CachePort(const std::string &_name, BaseCache *_cache,
  43                                 bool _isCpuSide)
  44     : Port(_name), cache(_cache), isCpuSide(_isCpuSide)
  45 {
  46     blocked = false;
  47     //Start ports at null if more than one is created we should panic
  48     //cpuSidePort = NULL;
  49     //memSidePort = NULL;
  50 }
  51
  52 void
  53 BaseCache::CachePort::recvStatusChange(Port::Status status)
  54 {
  55     cache->recvStatusChange(status, isCpuSide);
  56 }
  57
  58 void
  59 BaseCache::CachePort::getDeviceAddressRanges(AddrRangeList &resp,
  60                                        AddrRangeList &snoop)
  61 {
  62     cache->getAddressRanges(resp, snoop, isCpuSide);
  63 }
  64
  65 int
  66 BaseCache::CachePort::deviceBlockSize()
  67 {
  68     return cache->getBlockSize();
  69 }
  70
  71 bool
  72 BaseCache::CachePort::recvTiming(Packet *pkt)
  73 {
  74     if (pkt->isRequest() && blocked)
  75     {
  76         DPRINTF(Cache,"Scheduling a retry while blocked\n");
  77         mustSendRetry = true;
  78         return false;
  79     }
  80     return cache->doTimingAccess(pkt, this, isCpuSide);
  81 }
  82
  83 Tick
  84 BaseCache::CachePort::recvAtomic(Packet *pkt)
  85 {
  86     return cache->doAtomicAccess(pkt, isCpuSide);
  87 }
  88
  89 void
  90 BaseCache::CachePort::recvFunctional(Packet *pkt)
  91 {
  92     cache->doFunctionalAccess(pkt, isCpuSide);
  93 }
  94
  95 void
  96 BaseCache::CachePort::recvRetry()
  97 {
  98     Packet *pkt;
  99     if (!drainList.empty()) {
 100         //We have some responses to drain first
 101         bool result = true;
 102         while (result && !drainList.empty()) {
 103             result = sendTiming(drainList.front());
 104             if (result)
 105                 drainList.pop_front();
 106         }
 107     }
 108     else if (!isCpuSide)
 109     {
 110         pkt = cache->getPacket();
 111         MSHR* mshr = (MSHR*)pkt->senderState;
 112         bool success = sendTiming(pkt);
 113         DPRINTF(Cache, "Address %x was %s in sending the timing request\n",
 114                 pkt->getAddr(), success ? "succesful" : "unsuccesful");
 115         cache->sendResult(pkt, mshr, success);
 116         if (success && cache->doMasterRequest())
 117         {
 118             //Still more to issue, rerequest in 1 cycle
 119             pkt = NULL;
 120             BaseCache::CacheEvent * reqCpu = new BaseCache::CacheEvent(this);
 121             reqCpu->schedule(curTick + 1);
 122         }
 123     }
 124     else
 125     {
 126         //pkt = cache->getCoherencePacket();
 127         //We save the packet, no reordering on CSHRS
 128         pkt = cshrRetry;
 129         bool success = sendTiming(pkt);
 130         if (success && cache->doSlaveRequest())
 131         {
 132             //Still more to issue, rerequest in 1 cycle
 133             pkt = NULL;
 134             BaseCache::CacheEvent * reqCpu = new BaseCache::CacheEvent(this);
 135             reqCpu->schedule(curTick + 1);
 136         }
 137
 138     }
 139     return;
 140 }
 141 void
 142 BaseCache::CachePort::setBlocked()
 143 {
 144     assert(!blocked);
 145     DPRINTF(Cache, "Cache Blocking\n");
 146     blocked = true;
 147     //Clear the retry flag
 148     mustSendRetry = false;
 149 }
 150
 151 void
 152 BaseCache::CachePort::clearBlocked()
 153 {
 154     assert(blocked);
 155     DPRINTF(Cache, "Cache Unblocking\n");
 156     blocked = false;
 157     if (mustSendRetry)
 158     {
 159         DPRINTF(Cache, "Cache Sending Retry\n");
 160         mustSendRetry = false;
 161         sendRetry();
 162     }
 163 }
 164
 165 BaseCache::CacheEvent::CacheEvent(CachePort *_cachePort)
 166     : Event(&mainEventQueue, CPU_Tick_Pri), cachePort(_cachePort)
 167 {
 168     this->setFlags(AutoDelete);
 169     pkt = NULL;
 170 }
 171
 172 BaseCache::CacheEvent::CacheEvent(CachePort *_cachePort, Packet *_pkt)
 173     : Event(&mainEventQueue, CPU_Tick_Pri), cachePort(_cachePort), pkt(_pkt)
 174 {
 175     this->setFlags(AutoDelete);
 176 }
 177
 178 void
 179 BaseCache::CacheEvent::process()
 180 {
 181     if (!pkt)
 182     {
 183         if (!cachePort->isCpuSide)
 184         {
 185             //MSHR
 186             pkt = cachePort->cache->getPacket();
 187             MSHR* mshr = (MSHR*) pkt->senderState;
 188             bool success = cachePort->sendTiming(pkt);
 189             DPRINTF(Cache, "Address %x was %s in sending the timing request\n",
 190                     pkt->getAddr(), success ? "succesful" : "unsuccesful");
 191             cachePort->cache->sendResult(pkt, mshr, success);
 192             if (success && cachePort->cache->doMasterRequest())
 193             {
 194                 //Still more to issue, rerequest in 1 cycle
 195                 pkt = NULL;
 196                 this->schedule(curTick+1);
 197             }
 198         }
 199         else
 200         {
 201             //CSHR
 202             pkt = cachePort->cache->getCoherencePacket();
 203             bool success = cachePort->sendTiming(pkt);
 204             if (!success) {
 205                 //Need to send on a retry
 206                 cachePort->cshrRetry = pkt;
 207             }
 208             else if (cachePort->cache->doSlaveRequest())
 209             {
 210                 //Still more to issue, rerequest in 1 cycle
 211                 pkt = NULL;
 212                 this->schedule(curTick+1);
 213             }
 214         }
 215         return;
 216     }
 217     //Response
 218     //Know the packet to send
 219     if (pkt->flags & NACKED_LINE)
 220         pkt->result = Packet::Nacked;
 221     else
 222         pkt->result = Packet::Success;
 223     pkt->makeTimingResponse();
 224     if (!cachePort->drainList.empty()) {
 225         //Already blocked waiting for bus, just append
 226         cachePort->drainList.push_back(pkt);
 227     }
 228     else if (!cachePort->sendTiming(pkt)) {
 229         //It failed, save it to list of drain events
 230         cachePort->drainList.push_back(pkt);
 231     }
 232 }
 233
 234 const char *
 235 BaseCache::CacheEvent::description()
 236 {
 237     return "timing event\n";
 238 }
 239
 240 Port*
 241 BaseCache::getPort(const std::string &if_name, int idx)
 242 {
 243     if (if_name == "")
 244     {
 245         if(cpuSidePort == NULL)
 246             cpuSidePort = new CachePort(name() + "-cpu_side_port", this, true);
 247         return cpuSidePort;
 248     }
 249     else if (if_name == "functional")
 250     {
 251         if(cpuSidePort == NULL)
 252             cpuSidePort = new CachePort(name() + "-cpu_side_port", this, true);
 253         return cpuSidePort;
 254     }
 255     else if (if_name == "cpu_side")
 256     {
 257         if(cpuSidePort == NULL)
 258             cpuSidePort = new CachePort(name() + "-cpu_side_port", this, true);
 259         return cpuSidePort;
 260     }
 261     else if (if_name == "mem_side")
 262     {
 263         if (memSidePort != NULL)
 264             panic("Already have a mem side for this cache\n");
 265         memSidePort = new CachePort(name() + "-mem_side_port", this, false);
 266         return memSidePort;
 267     }
 268     else panic("Port name %s unrecognized\n", if_name);
 269 }
 270
 271 void
 272 BaseCache::init()
 273 {
 274     if (!cpuSidePort || !memSidePort)
 275         panic("Cache not hooked up on both sides\n");
 276     cpuSidePort->sendStatusChange(Port::RangeChange);
 277 }
 278
 279 void
 280 BaseCache::regStats()
 281 {
 282     Request temp_req((Addr) NULL, 4, 0);
 283     Packet::Command temp_cmd = Packet::ReadReq;
 284     Packet temp_pkt(&temp_req, temp_cmd, 0);  //@todo FIx command strings so this isn't neccessary
 285     temp_pkt.allocate(); //Temp allocate, all need data
 286
 287     using namespace Stats;
 288
 289     // Hit statistics
 290     for (int access_idx = 0; access_idx < NUM_MEM_CMDS; ++access_idx) {
 291         Packet::Command cmd = (Packet::Command)access_idx;
 292         const string &cstr = temp_pkt.cmdIdxToString(cmd);
 293
 294         hits[access_idx]
 295             .init(maxThreadsPerCPU)
 296             .name(name() + "." + cstr + "_hits")
 297             .desc("number of " + cstr + " hits")
 298             .flags(total | nozero | nonan)
 299             ;
 300     }
 301
 302     demandHits
 303         .name(name() + ".demand_hits")
 304         .desc("number of demand (read+write) hits")
 305         .flags(total)
 306         ;
 307     demandHits = hits[Packet::ReadReq] + hits[Packet::WriteReq];
 308
 309     overallHits
 310         .name(name() + ".overall_hits")
 311         .desc("number of overall hits")
 312         .flags(total)
 313         ;
 314     overallHits = demandHits + hits[Packet::SoftPFReq] + hits[Packet::HardPFReq]
 315         + hits[Packet::Writeback];
 316
 317     // Miss statistics
 318     for (int access_idx = 0; access_idx < NUM_MEM_CMDS; ++access_idx) {
 319         Packet::Command cmd = (Packet::Command)access_idx;
 320         const string &cstr = temp_pkt.cmdIdxToString(cmd);
 321
 322         misses[access_idx]
 323             .init(maxThreadsPerCPU)
 324             .name(name() + "." + cstr + "_misses")
 325             .desc("number of " + cstr + " misses")
 326             .flags(total | nozero | nonan)
 327             ;
 328     }
 329
 330     demandMisses
 331         .name(name() + ".demand_misses")
 332         .desc("number of demand (read+write) misses")
 333         .flags(total)
 334         ;
 335     demandMisses = misses[Packet::ReadReq] + misses[Packet::WriteReq];
 336
 337     overallMisses
 338         .name(name() + ".overall_misses")
 339         .desc("number of overall misses")
 340         .flags(total)
 341         ;
 342     overallMisses = demandMisses + misses[Packet::SoftPFReq] +
 343         misses[Packet::HardPFReq] + misses[Packet::Writeback];
 344
 345     // Miss latency statistics
 346     for (int access_idx = 0; access_idx < NUM_MEM_CMDS; ++access_idx) {
 347         Packet::Command cmd = (Packet::Command)access_idx;
 348         const string &cstr = temp_pkt.cmdIdxToString(cmd);
 349
 350         missLatency[access_idx]
 351             .init(maxThreadsPerCPU)
 352             .name(name() + "." + cstr + "_miss_latency")
 353             .desc("number of " + cstr + " miss cycles")
 354             .flags(total | nozero | nonan)
 355             ;
 356     }
 357
 358     demandMissLatency
 359         .name(name() + ".demand_miss_latency")
 360         .desc("number of demand (read+write) miss cycles")
 361         .flags(total)
 362         ;
 363     demandMissLatency = missLatency[Packet::ReadReq] + missLatency[Packet::WriteReq];
 364
 365     overallMissLatency
 366         .name(name() + ".overall_miss_latency")
 367         .desc("number of overall miss cycles")
 368         .flags(total)
 369         ;
 370     overallMissLatency = demandMissLatency + missLatency[Packet::SoftPFReq] +
 371         missLatency[Packet::HardPFReq];
 372
 373     // access formulas
 374     for (int access_idx = 0; access_idx < NUM_MEM_CMDS; ++access_idx) {
 375         Packet::Command cmd = (Packet::Command)access_idx;
 376         const string &cstr = temp_pkt.cmdIdxToString(cmd);
 377
 378         accesses[access_idx]
 379             .name(name() + "." + cstr + "_accesses")
 380             .desc("number of " + cstr + " accesses(hits+misses)")
 381             .flags(total | nozero | nonan)
 382             ;
 383
 384         accesses[access_idx] = hits[access_idx] + misses[access_idx];
 385     }
 386
 387     demandAccesses
 388         .name(name() + ".demand_accesses")
 389         .desc("number of demand (read+write) accesses")
 390         .flags(total)
 391         ;
 392     demandAccesses = demandHits + demandMisses;
 393
 394     overallAccesses
 395         .name(name() + ".overall_accesses")
 396         .desc("number of overall (read+write) accesses")
 397         .flags(total)
 398         ;
 399     overallAccesses = overallHits + overallMisses;
 400
 401     // miss rate formulas
 402     for (int access_idx = 0; access_idx < NUM_MEM_CMDS; ++access_idx) {
 403         Packet::Command cmd = (Packet::Command)access_idx;
 404         const string &cstr = temp_pkt.cmdIdxToString(cmd);
 405
 406         missRate[access_idx]
 407             .name(name() + "." + cstr + "_miss_rate")
 408             .desc("miss rate for " + cstr + " accesses")
 409             .flags(total | nozero | nonan)
 410             ;
 411
 412         missRate[access_idx] = misses[access_idx] / accesses[access_idx];
 413     }
 414
 415     demandMissRate
 416         .name(name() + ".demand_miss_rate")
 417         .desc("miss rate for demand accesses")
 418         .flags(total)
 419         ;
 420     demandMissRate = demandMisses / demandAccesses;
 421
 422     overallMissRate
 423         .name(name() + ".overall_miss_rate")
 424         .desc("miss rate for overall accesses")
 425         .flags(total)
 426         ;
 427     overallMissRate = overallMisses / overallAccesses;
 428
 429     // miss latency formulas
 430     for (int access_idx = 0; access_idx < NUM_MEM_CMDS; ++access_idx) {
 431         Packet::Command cmd = (Packet::Command)access_idx;
 432         const string &cstr = temp_pkt.cmdIdxToString(cmd);
 433
 434         avgMissLatency[access_idx]
 435             .name(name() + "." + cstr + "_avg_miss_latency")
 436             .desc("average " + cstr + " miss latency")
 437             .flags(total | nozero | nonan)
 438             ;
 439
 440         avgMissLatency[access_idx] =
 441             missLatency[access_idx] / misses[access_idx];
 442     }
 443
 444     demandAvgMissLatency
 445         .name(name() + ".demand_avg_miss_latency")
 446         .desc("average overall miss latency")
 447         .flags(total)
 448         ;
 449     demandAvgMissLatency = demandMissLatency / demandMisses;
 450
 451     overallAvgMissLatency
 452         .name(name() + ".overall_avg_miss_latency")
 453         .desc("average overall miss latency")
 454         .flags(total)
 455         ;
 456     overallAvgMissLatency = overallMissLatency / overallMisses;
 457
 458     blocked_cycles.init(NUM_BLOCKED_CAUSES);
 459     blocked_cycles
 460         .name(name() + ".blocked_cycles")
 461         .desc("number of cycles access was blocked")
 462         .subname(Blocked_NoMSHRs, "no_mshrs")
 463         .subname(Blocked_NoTargets, "no_targets")
 464         ;
 465
 466
 467     blocked_causes.init(NUM_BLOCKED_CAUSES);
 468     blocked_causes
 469         .name(name() + ".blocked")
 470         .desc("number of cycles access was blocked")
 471         .subname(Blocked_NoMSHRs, "no_mshrs")
 472         .subname(Blocked_NoTargets, "no_targets")
 473         ;
 474
 475     avg_blocked
 476         .name(name() + ".avg_blocked_cycles")
 477         .desc("average number of cycles each access was blocked")
 478         .subname(Blocked_NoMSHRs, "no_mshrs")
 479         .subname(Blocked_NoTargets, "no_targets")
 480         ;
 481
 482     avg_blocked = blocked_cycles / blocked_causes;
 483
 484     fastWrites
 485         .name(name() + ".fast_writes")
 486         .desc("number of fast writes performed")
 487         ;
 488
 489     cacheCopies
 490         .name(name() + ".cache_copies")
 491         .desc("number of cache copies performed")
 492         ;
 493
 494 }