2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Authors: Erik Hallnor
33 * Definition of BaseCache functions.
36 #include "mem/cache/base_cache.hh"
38 #include "cpu/base.hh"
42 BaseCache::CachePort::CachePort(const std::string
&_name
, BaseCache
*_cache
,
44 : Port(_name
), cache(_cache
), isCpuSide(_isCpuSide
)
47 //Start ports at null if more than one is created we should panic
53 BaseCache::CachePort::recvStatusChange(Port::Status status
)
55 cache
->recvStatusChange(status
, isCpuSide
);
59 BaseCache::CachePort::getDeviceAddressRanges(AddrRangeList
&resp
,
62 cache
->getAddressRanges(resp
, snoop
, isCpuSide
);
66 BaseCache::CachePort::deviceBlockSize()
68 return cache
->getBlockSize();
72 BaseCache::CachePort::recvTiming(Packet
*pkt
)
76 DPRINTF(Cache
,"Scheduling a retry while blocked\n");
80 return cache
->doTimingAccess(pkt
, this, isCpuSide
);
84 BaseCache::CachePort::recvAtomic(Packet
*pkt
)
86 return cache
->doAtomicAccess(pkt
, isCpuSide
);
90 BaseCache::CachePort::recvFunctional(Packet
*pkt
)
92 cache
->doFunctionalAccess(pkt
, isCpuSide
);
96 BaseCache::CachePort::recvRetry()
102 pkt
= cache
->getPacket();
103 bool success
= sendTiming(pkt
);
104 DPRINTF(Cache
, "Address %x was %s in sending the timing request\n",
105 pkt
->getAddr(), success
? "succesful" : "unsuccesful");
106 cache
->sendResult(pkt
, success
);
107 if (success
&& cache
->doMasterRequest())
109 //Still more to issue, rerequest in 1 cycle
111 BaseCache::CacheEvent
* reqCpu
= new BaseCache::CacheEvent(this);
112 reqCpu
->schedule(curTick
+ 1);
117 pkt
= cache
->getCoherencePacket();
118 bool success
= sendTiming(pkt
);
119 if (success
&& cache
->doSlaveRequest())
121 //Still more to issue, rerequest in 1 cycle
123 BaseCache::CacheEvent
* reqCpu
= new BaseCache::CacheEvent(this);
124 reqCpu
->schedule(curTick
+ 1);
131 BaseCache::CachePort::setBlocked()
134 DPRINTF(Cache
, "Cache Blocking\n");
136 //Clear the retry flag
137 mustSendRetry
= false;
141 BaseCache::CachePort::clearBlocked()
144 DPRINTF(Cache
, "Cache Unblocking\n");
148 DPRINTF(Cache
, "Cache Sending Retry\n");
149 mustSendRetry
= false;
154 BaseCache::CacheEvent::CacheEvent(CachePort
*_cachePort
)
155 : Event(&mainEventQueue
, CPU_Tick_Pri
), cachePort(_cachePort
)
157 this->setFlags(AutoDelete
);
161 BaseCache::CacheEvent::CacheEvent(CachePort
*_cachePort
, Packet
*_pkt
)
162 : Event(&mainEventQueue
, CPU_Tick_Pri
), cachePort(_cachePort
), pkt(_pkt
)
164 this->setFlags(AutoDelete
);
168 BaseCache::CacheEvent::process()
172 if (!cachePort
->isCpuSide
)
175 pkt
= cachePort
->cache
->getPacket();
176 bool success
= cachePort
->sendTiming(pkt
);
177 DPRINTF(Cache
, "Address %x was %s in sending the timing request\n",
178 pkt
->getAddr(), success
? "succesful" : "unsuccesful");
179 cachePort
->cache
->sendResult(pkt
, success
);
180 if (success
&& cachePort
->cache
->doMasterRequest())
182 //Still more to issue, rerequest in 1 cycle
184 this->schedule(curTick
+1);
190 pkt
= cachePort
->cache
->getCoherencePacket();
191 bool success
= cachePort
->sendTiming(pkt
);
192 if (success
&& cachePort
->cache
->doSlaveRequest())
194 //Still more to issue, rerequest in 1 cycle
196 this->schedule(curTick
+1);
202 //Know the packet to send
203 pkt
->result
= Packet::Success
;
204 pkt
->makeTimingResponse();
205 assert(cachePort
->sendTiming(pkt
));
209 BaseCache::CacheEvent::description()
211 return "timing event\n";
215 BaseCache::getPort(const std::string
&if_name
, int idx
)
219 if(cpuSidePort
== NULL
)
220 cpuSidePort
= new CachePort(name() + "-cpu_side_port", this, true);
223 else if (if_name
== "functional")
225 if(cpuSidePort
== NULL
)
226 cpuSidePort
= new CachePort(name() + "-cpu_side_port", this, true);
229 else if (if_name
== "cpu_side")
231 if(cpuSidePort
== NULL
)
232 cpuSidePort
= new CachePort(name() + "-cpu_side_port", this, true);
235 else if (if_name
== "mem_side")
237 if (memSidePort
!= NULL
)
238 panic("Already have a mem side for this cache\n");
239 memSidePort
= new CachePort(name() + "-mem_side_port", this, false);
242 else panic("Port name %s unrecognized\n", if_name
);
248 if (!cpuSidePort
|| !memSidePort
)
249 panic("Cache not hooked up on both sides\n");
250 cpuSidePort
->sendStatusChange(Port::RangeChange
);
254 BaseCache::regStats()
256 Request
temp_req((Addr
) NULL
, 4, 0);
257 Packet::Command temp_cmd
= Packet::ReadReq
;
258 Packet
temp_pkt(&temp_req
, temp_cmd
, 0); //@todo FIx command strings so this isn't neccessary
259 temp_pkt
.allocate(); //Temp allocate, all need data
261 using namespace Stats
;
264 for (int access_idx
= 0; access_idx
< NUM_MEM_CMDS
; ++access_idx
) {
265 Packet::Command cmd
= (Packet::Command
)access_idx
;
266 const string
&cstr
= temp_pkt
.cmdIdxToString(cmd
);
269 .init(maxThreadsPerCPU
)
270 .name(name() + "." + cstr
+ "_hits")
271 .desc("number of " + cstr
+ " hits")
272 .flags(total
| nozero
| nonan
)
277 .name(name() + ".demand_hits")
278 .desc("number of demand (read+write) hits")
281 demandHits
= hits
[Packet::ReadReq
] + hits
[Packet::WriteReq
];
284 .name(name() + ".overall_hits")
285 .desc("number of overall hits")
288 overallHits
= demandHits
+ hits
[Packet::SoftPFReq
] + hits
[Packet::HardPFReq
]
289 + hits
[Packet::Writeback
];
292 for (int access_idx
= 0; access_idx
< NUM_MEM_CMDS
; ++access_idx
) {
293 Packet::Command cmd
= (Packet::Command
)access_idx
;
294 const string
&cstr
= temp_pkt
.cmdIdxToString(cmd
);
297 .init(maxThreadsPerCPU
)
298 .name(name() + "." + cstr
+ "_misses")
299 .desc("number of " + cstr
+ " misses")
300 .flags(total
| nozero
| nonan
)
305 .name(name() + ".demand_misses")
306 .desc("number of demand (read+write) misses")
309 demandMisses
= misses
[Packet::ReadReq
] + misses
[Packet::WriteReq
];
312 .name(name() + ".overall_misses")
313 .desc("number of overall misses")
316 overallMisses
= demandMisses
+ misses
[Packet::SoftPFReq
] +
317 misses
[Packet::HardPFReq
] + misses
[Packet::Writeback
];
319 // Miss latency statistics
320 for (int access_idx
= 0; access_idx
< NUM_MEM_CMDS
; ++access_idx
) {
321 Packet::Command cmd
= (Packet::Command
)access_idx
;
322 const string
&cstr
= temp_pkt
.cmdIdxToString(cmd
);
324 missLatency
[access_idx
]
325 .init(maxThreadsPerCPU
)
326 .name(name() + "." + cstr
+ "_miss_latency")
327 .desc("number of " + cstr
+ " miss cycles")
328 .flags(total
| nozero
| nonan
)
333 .name(name() + ".demand_miss_latency")
334 .desc("number of demand (read+write) miss cycles")
337 demandMissLatency
= missLatency
[Packet::ReadReq
] + missLatency
[Packet::WriteReq
];
340 .name(name() + ".overall_miss_latency")
341 .desc("number of overall miss cycles")
344 overallMissLatency
= demandMissLatency
+ missLatency
[Packet::SoftPFReq
] +
345 missLatency
[Packet::HardPFReq
];
348 for (int access_idx
= 0; access_idx
< NUM_MEM_CMDS
; ++access_idx
) {
349 Packet::Command cmd
= (Packet::Command
)access_idx
;
350 const string
&cstr
= temp_pkt
.cmdIdxToString(cmd
);
353 .name(name() + "." + cstr
+ "_accesses")
354 .desc("number of " + cstr
+ " accesses(hits+misses)")
355 .flags(total
| nozero
| nonan
)
358 accesses
[access_idx
] = hits
[access_idx
] + misses
[access_idx
];
362 .name(name() + ".demand_accesses")
363 .desc("number of demand (read+write) accesses")
366 demandAccesses
= demandHits
+ demandMisses
;
369 .name(name() + ".overall_accesses")
370 .desc("number of overall (read+write) accesses")
373 overallAccesses
= overallHits
+ overallMisses
;
375 // miss rate formulas
376 for (int access_idx
= 0; access_idx
< NUM_MEM_CMDS
; ++access_idx
) {
377 Packet::Command cmd
= (Packet::Command
)access_idx
;
378 const string
&cstr
= temp_pkt
.cmdIdxToString(cmd
);
381 .name(name() + "." + cstr
+ "_miss_rate")
382 .desc("miss rate for " + cstr
+ " accesses")
383 .flags(total
| nozero
| nonan
)
386 missRate
[access_idx
] = misses
[access_idx
] / accesses
[access_idx
];
390 .name(name() + ".demand_miss_rate")
391 .desc("miss rate for demand accesses")
394 demandMissRate
= demandMisses
/ demandAccesses
;
397 .name(name() + ".overall_miss_rate")
398 .desc("miss rate for overall accesses")
401 overallMissRate
= overallMisses
/ overallAccesses
;
403 // miss latency formulas
404 for (int access_idx
= 0; access_idx
< NUM_MEM_CMDS
; ++access_idx
) {
405 Packet::Command cmd
= (Packet::Command
)access_idx
;
406 const string
&cstr
= temp_pkt
.cmdIdxToString(cmd
);
408 avgMissLatency
[access_idx
]
409 .name(name() + "." + cstr
+ "_avg_miss_latency")
410 .desc("average " + cstr
+ " miss latency")
411 .flags(total
| nozero
| nonan
)
414 avgMissLatency
[access_idx
] =
415 missLatency
[access_idx
] / misses
[access_idx
];
419 .name(name() + ".demand_avg_miss_latency")
420 .desc("average overall miss latency")
423 demandAvgMissLatency
= demandMissLatency
/ demandMisses
;
425 overallAvgMissLatency
426 .name(name() + ".overall_avg_miss_latency")
427 .desc("average overall miss latency")
430 overallAvgMissLatency
= overallMissLatency
/ overallMisses
;
432 blocked_cycles
.init(NUM_BLOCKED_CAUSES
);
434 .name(name() + ".blocked_cycles")
435 .desc("number of cycles access was blocked")
436 .subname(Blocked_NoMSHRs
, "no_mshrs")
437 .subname(Blocked_NoTargets
, "no_targets")
441 blocked_causes
.init(NUM_BLOCKED_CAUSES
);
443 .name(name() + ".blocked")
444 .desc("number of cycles access was blocked")
445 .subname(Blocked_NoMSHRs
, "no_mshrs")
446 .subname(Blocked_NoTargets
, "no_targets")
450 .name(name() + ".avg_blocked_cycles")
451 .desc("average number of cycles each access was blocked")
452 .subname(Blocked_NoMSHRs
, "no_mshrs")
453 .subname(Blocked_NoTargets
, "no_targets")
456 avg_blocked
= blocked_cycles
/ blocked_causes
;
459 .name(name() + ".fast_writes")
460 .desc("number of fast writes performed")
464 .name(name() + ".cache_copies")
465 .desc("number of cache copies performed")