2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Authors: Erik Hallnor
33 * Definition of BaseCache functions.
36 #include "mem/cache/base_cache.hh"
38 #include "cpu/base.hh"
42 BaseCache::CachePort::CachePort(const std::string
&_name
, BaseCache
*_cache
,
44 : Port(_name
), cache(_cache
), isCpuSide(_isCpuSide
)
47 //Start ports at null if more than one is created we should panic
53 BaseCache::CachePort::recvStatusChange(Port::Status status
)
55 cache
->recvStatusChange(status
, isCpuSide
);
59 BaseCache::CachePort::getDeviceAddressRanges(AddrRangeList
&resp
,
62 cache
->getAddressRanges(resp
, snoop
, isCpuSide
);
66 BaseCache::CachePort::deviceBlockSize()
68 return cache
->getBlockSize();
72 BaseCache::CachePort::recvTiming(Packet
*pkt
)
76 DPRINTF(Cache
,"Scheduling a retry while blocked\n");
80 return cache
->doTimingAccess(pkt
, this, isCpuSide
);
84 BaseCache::CachePort::recvAtomic(Packet
*pkt
)
86 return cache
->doAtomicAccess(pkt
, isCpuSide
);
90 BaseCache::CachePort::recvFunctional(Packet
*pkt
)
92 cache
->doFunctionalAccess(pkt
, isCpuSide
);
96 BaseCache::CachePort::recvRetry()
99 if (!drainList
.empty()) {
100 //We have some responses to drain first
102 while (result
&& !drainList
.empty()) {
103 result
= sendTiming(drainList
.front());
105 drainList
.pop_front();
111 pkt
= cache
->getPacket();
112 bool success
= sendTiming(pkt
);
113 DPRINTF(Cache
, "Address %x was %s in sending the timing request\n",
114 pkt
->getAddr(), success
? "succesful" : "unsuccesful");
115 cache
->sendResult(pkt
, success
);
116 if (success
&& cache
->doMasterRequest())
118 //Still more to issue, rerequest in 1 cycle
120 BaseCache::CacheEvent
* reqCpu
= new BaseCache::CacheEvent(this);
121 reqCpu
->schedule(curTick
+ 1);
126 pkt
= cache
->getCoherencePacket();
127 bool success
= sendTiming(pkt
);
128 if (success
&& cache
->doSlaveRequest())
130 //Still more to issue, rerequest in 1 cycle
132 BaseCache::CacheEvent
* reqCpu
= new BaseCache::CacheEvent(this);
133 reqCpu
->schedule(curTick
+ 1);
140 BaseCache::CachePort::setBlocked()
143 DPRINTF(Cache
, "Cache Blocking\n");
145 //Clear the retry flag
146 mustSendRetry
= false;
150 BaseCache::CachePort::clearBlocked()
153 DPRINTF(Cache
, "Cache Unblocking\n");
157 DPRINTF(Cache
, "Cache Sending Retry\n");
158 mustSendRetry
= false;
163 BaseCache::CacheEvent::CacheEvent(CachePort
*_cachePort
)
164 : Event(&mainEventQueue
, CPU_Tick_Pri
), cachePort(_cachePort
)
166 this->setFlags(AutoDelete
);
170 BaseCache::CacheEvent::CacheEvent(CachePort
*_cachePort
, Packet
*_pkt
)
171 : Event(&mainEventQueue
, CPU_Tick_Pri
), cachePort(_cachePort
), pkt(_pkt
)
173 this->setFlags(AutoDelete
);
177 BaseCache::CacheEvent::process()
181 if (!cachePort
->isCpuSide
)
184 pkt
= cachePort
->cache
->getPacket();
185 bool success
= cachePort
->sendTiming(pkt
);
186 DPRINTF(Cache
, "Address %x was %s in sending the timing request\n",
187 pkt
->getAddr(), success
? "succesful" : "unsuccesful");
188 cachePort
->cache
->sendResult(pkt
, success
);
189 if (success
&& cachePort
->cache
->doMasterRequest())
191 //Still more to issue, rerequest in 1 cycle
193 this->schedule(curTick
+1);
199 pkt
= cachePort
->cache
->getCoherencePacket();
200 bool success
= cachePort
->sendTiming(pkt
);
201 if (success
&& cachePort
->cache
->doSlaveRequest())
203 //Still more to issue, rerequest in 1 cycle
205 this->schedule(curTick
+1);
211 //Know the packet to send
212 pkt
->result
= Packet::Success
;
213 pkt
->makeTimingResponse();
214 if (!cachePort
->sendTiming(pkt
)) {
215 //It failed, save it to list of drain events
216 cachePort
->drainList
.push_back(pkt
);
221 BaseCache::CacheEvent::description()
223 return "timing event\n";
227 BaseCache::getPort(const std::string
&if_name
, int idx
)
231 if(cpuSidePort
== NULL
)
232 cpuSidePort
= new CachePort(name() + "-cpu_side_port", this, true);
235 else if (if_name
== "functional")
237 if(cpuSidePort
== NULL
)
238 cpuSidePort
= new CachePort(name() + "-cpu_side_port", this, true);
241 else if (if_name
== "cpu_side")
243 if(cpuSidePort
== NULL
)
244 cpuSidePort
= new CachePort(name() + "-cpu_side_port", this, true);
247 else if (if_name
== "mem_side")
249 if (memSidePort
!= NULL
)
250 panic("Already have a mem side for this cache\n");
251 memSidePort
= new CachePort(name() + "-mem_side_port", this, false);
254 else panic("Port name %s unrecognized\n", if_name
);
260 if (!cpuSidePort
|| !memSidePort
)
261 panic("Cache not hooked up on both sides\n");
262 cpuSidePort
->sendStatusChange(Port::RangeChange
);
266 BaseCache::regStats()
268 Request
temp_req((Addr
) NULL
, 4, 0);
269 Packet::Command temp_cmd
= Packet::ReadReq
;
270 Packet
temp_pkt(&temp_req
, temp_cmd
, 0); //@todo FIx command strings so this isn't neccessary
271 temp_pkt
.allocate(); //Temp allocate, all need data
273 using namespace Stats
;
276 for (int access_idx
= 0; access_idx
< NUM_MEM_CMDS
; ++access_idx
) {
277 Packet::Command cmd
= (Packet::Command
)access_idx
;
278 const string
&cstr
= temp_pkt
.cmdIdxToString(cmd
);
281 .init(maxThreadsPerCPU
)
282 .name(name() + "." + cstr
+ "_hits")
283 .desc("number of " + cstr
+ " hits")
284 .flags(total
| nozero
| nonan
)
289 .name(name() + ".demand_hits")
290 .desc("number of demand (read+write) hits")
293 demandHits
= hits
[Packet::ReadReq
] + hits
[Packet::WriteReq
];
296 .name(name() + ".overall_hits")
297 .desc("number of overall hits")
300 overallHits
= demandHits
+ hits
[Packet::SoftPFReq
] + hits
[Packet::HardPFReq
]
301 + hits
[Packet::Writeback
];
304 for (int access_idx
= 0; access_idx
< NUM_MEM_CMDS
; ++access_idx
) {
305 Packet::Command cmd
= (Packet::Command
)access_idx
;
306 const string
&cstr
= temp_pkt
.cmdIdxToString(cmd
);
309 .init(maxThreadsPerCPU
)
310 .name(name() + "." + cstr
+ "_misses")
311 .desc("number of " + cstr
+ " misses")
312 .flags(total
| nozero
| nonan
)
317 .name(name() + ".demand_misses")
318 .desc("number of demand (read+write) misses")
321 demandMisses
= misses
[Packet::ReadReq
] + misses
[Packet::WriteReq
];
324 .name(name() + ".overall_misses")
325 .desc("number of overall misses")
328 overallMisses
= demandMisses
+ misses
[Packet::SoftPFReq
] +
329 misses
[Packet::HardPFReq
] + misses
[Packet::Writeback
];
331 // Miss latency statistics
332 for (int access_idx
= 0; access_idx
< NUM_MEM_CMDS
; ++access_idx
) {
333 Packet::Command cmd
= (Packet::Command
)access_idx
;
334 const string
&cstr
= temp_pkt
.cmdIdxToString(cmd
);
336 missLatency
[access_idx
]
337 .init(maxThreadsPerCPU
)
338 .name(name() + "." + cstr
+ "_miss_latency")
339 .desc("number of " + cstr
+ " miss cycles")
340 .flags(total
| nozero
| nonan
)
345 .name(name() + ".demand_miss_latency")
346 .desc("number of demand (read+write) miss cycles")
349 demandMissLatency
= missLatency
[Packet::ReadReq
] + missLatency
[Packet::WriteReq
];
352 .name(name() + ".overall_miss_latency")
353 .desc("number of overall miss cycles")
356 overallMissLatency
= demandMissLatency
+ missLatency
[Packet::SoftPFReq
] +
357 missLatency
[Packet::HardPFReq
];
360 for (int access_idx
= 0; access_idx
< NUM_MEM_CMDS
; ++access_idx
) {
361 Packet::Command cmd
= (Packet::Command
)access_idx
;
362 const string
&cstr
= temp_pkt
.cmdIdxToString(cmd
);
365 .name(name() + "." + cstr
+ "_accesses")
366 .desc("number of " + cstr
+ " accesses(hits+misses)")
367 .flags(total
| nozero
| nonan
)
370 accesses
[access_idx
] = hits
[access_idx
] + misses
[access_idx
];
374 .name(name() + ".demand_accesses")
375 .desc("number of demand (read+write) accesses")
378 demandAccesses
= demandHits
+ demandMisses
;
381 .name(name() + ".overall_accesses")
382 .desc("number of overall (read+write) accesses")
385 overallAccesses
= overallHits
+ overallMisses
;
387 // miss rate formulas
388 for (int access_idx
= 0; access_idx
< NUM_MEM_CMDS
; ++access_idx
) {
389 Packet::Command cmd
= (Packet::Command
)access_idx
;
390 const string
&cstr
= temp_pkt
.cmdIdxToString(cmd
);
393 .name(name() + "." + cstr
+ "_miss_rate")
394 .desc("miss rate for " + cstr
+ " accesses")
395 .flags(total
| nozero
| nonan
)
398 missRate
[access_idx
] = misses
[access_idx
] / accesses
[access_idx
];
402 .name(name() + ".demand_miss_rate")
403 .desc("miss rate for demand accesses")
406 demandMissRate
= demandMisses
/ demandAccesses
;
409 .name(name() + ".overall_miss_rate")
410 .desc("miss rate for overall accesses")
413 overallMissRate
= overallMisses
/ overallAccesses
;
415 // miss latency formulas
416 for (int access_idx
= 0; access_idx
< NUM_MEM_CMDS
; ++access_idx
) {
417 Packet::Command cmd
= (Packet::Command
)access_idx
;
418 const string
&cstr
= temp_pkt
.cmdIdxToString(cmd
);
420 avgMissLatency
[access_idx
]
421 .name(name() + "." + cstr
+ "_avg_miss_latency")
422 .desc("average " + cstr
+ " miss latency")
423 .flags(total
| nozero
| nonan
)
426 avgMissLatency
[access_idx
] =
427 missLatency
[access_idx
] / misses
[access_idx
];
431 .name(name() + ".demand_avg_miss_latency")
432 .desc("average overall miss latency")
435 demandAvgMissLatency
= demandMissLatency
/ demandMisses
;
437 overallAvgMissLatency
438 .name(name() + ".overall_avg_miss_latency")
439 .desc("average overall miss latency")
442 overallAvgMissLatency
= overallMissLatency
/ overallMisses
;
444 blocked_cycles
.init(NUM_BLOCKED_CAUSES
);
446 .name(name() + ".blocked_cycles")
447 .desc("number of cycles access was blocked")
448 .subname(Blocked_NoMSHRs
, "no_mshrs")
449 .subname(Blocked_NoTargets
, "no_targets")
453 blocked_causes
.init(NUM_BLOCKED_CAUSES
);
455 .name(name() + ".blocked")
456 .desc("number of cycles access was blocked")
457 .subname(Blocked_NoMSHRs
, "no_mshrs")
458 .subname(Blocked_NoTargets
, "no_targets")
462 .name(name() + ".avg_blocked_cycles")
463 .desc("average number of cycles each access was blocked")
464 .subname(Blocked_NoMSHRs
, "no_mshrs")
465 .subname(Blocked_NoTargets
, "no_targets")
468 avg_blocked
= blocked_cycles
/ blocked_causes
;
471 .name(name() + ".fast_writes")
472 .desc("number of fast writes performed")
476 .name(name() + ".cache_copies")
477 .desc("number of cache copies performed")