src/mem/cache/base_cache.cc

   1 /*
   2  * Copyright (c) 2003-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Erik Hallnor
  29  */
  30
  31 /**
  32  * @file
  33  * Definition of BaseCache functions.
  34  */
  35
  36 #include "mem/cache/base_cache.hh"
  37 #include "cpu/smt.hh"
  38 #include "cpu/base.hh"
  39 #include "mem/cache/miss/mshr.hh"
  40
  41 using namespace std;
  42
  43 BaseCache::CachePort::CachePort(const std::string &_name, BaseCache *_cache,
  44                                 bool _isCpuSide)
  45     : Port(_name), cache(_cache), isCpuSide(_isCpuSide)
  46 {
  47     blocked = false;
  48     waitingOnRetry = false;
  49     //Start ports at null if more than one is created we should panic
  50     //cpuSidePort = NULL;
  51     //memSidePort = NULL;
  52 }
  53
  54 void
  55 BaseCache::CachePort::recvStatusChange(Port::Status status)
  56 {
  57     cache->recvStatusChange(status, isCpuSide);
  58 }
  59
  60 void
  61 BaseCache::CachePort::getDeviceAddressRanges(AddrRangeList &resp,
  62                                        AddrRangeList &snoop)
  63 {
  64     cache->getAddressRanges(resp, snoop, isCpuSide);
  65 }
  66
  67 int
  68 BaseCache::CachePort::deviceBlockSize()
  69 {
  70     return cache->getBlockSize();
  71 }
  72
  73 bool
  74 BaseCache::CachePort::recvTiming(Packet *pkt)
  75 {
  76     if (isCpuSide
  77         && !pkt->req->isUncacheable()
  78         && pkt->isInvalidate()
  79         && !pkt->isRead() && !pkt->isWrite()) {
  80         //Upgrade or Invalidate
  81         //Look into what happens if two slave caches on bus
  82         DPRINTF(Cache, "%s %x ? blk_addr: %x\n", pkt->cmdString(),
  83                 pkt->getAddr() & (((ULL(1))<<48)-1),
  84                 pkt->getAddr() & ~((Addr)cache->blkSize - 1));
  85
  86         assert(!(pkt->flags & SATISFIED));
  87         pkt->flags |= SATISFIED;
  88         //Invalidates/Upgrades need no response if they get the bus
  89         return true;
  90     }
  91
  92     if (pkt->isRequest() && blocked)
  93     {
  94         DPRINTF(Cache,"Scheduling a retry while blocked\n");
  95         mustSendRetry = true;
  96         return false;
  97     }
  98     return cache->doTimingAccess(pkt, this, isCpuSide);
  99 }
 100
 101 Tick
 102 BaseCache::CachePort::recvAtomic(Packet *pkt)
 103 {
 104     return cache->doAtomicAccess(pkt, isCpuSide);
 105 }
 106
 107 void
 108 BaseCache::CachePort::recvFunctional(Packet *pkt)
 109 {
 110     //Check storage here first
 111     list<Packet *>::iterator i = drainList.begin();
 112     list<Packet *>::iterator end = drainList.end();
 113     for (; i != end; ++i) {
 114         Packet * target = *i;
 115         // If the target contains data, and it overlaps the
 116         // probed request, need to update data
 117         if (target->intersect(pkt)) {
 118             uint8_t* pkt_data;
 119             uint8_t* write_data;
 120             int data_size;
 121             if (target->getAddr() < pkt->getAddr()) {
 122                 int offset = pkt->getAddr() - target->getAddr();
 123                             pkt_data = pkt->getPtr<uint8_t>();
 124                             write_data = target->getPtr<uint8_t>() + offset;
 125                             data_size = target->getSize() - offset;
 126                             assert(data_size > 0);
 127                             if (data_size > pkt->getSize())
 128                                 data_size = pkt->getSize();
 129             } else {
 130                 int offset = target->getAddr() - pkt->getAddr();
 131                 pkt_data = pkt->getPtr<uint8_t>() + offset;
 132                 write_data = target->getPtr<uint8_t>();
 133                 data_size = pkt->getSize() - offset;
 134                 assert(data_size > pkt->getSize());
 135                 if (data_size > target->getSize())
 136                     data_size = target->getSize();
 137             }
 138
 139             if (pkt->isWrite()) {
 140                 memcpy(pkt_data, write_data, data_size);
 141             } else {
 142                 memcpy(write_data, pkt_data, data_size);
 143             }
 144         }
 145     }
 146     cache->doFunctionalAccess(pkt, isCpuSide);
 147 }
 148
 149 void
 150 BaseCache::CachePort::recvRetry()
 151 {
 152     Packet *pkt;
 153     assert(waitingOnRetry);
 154     if (!drainList.empty()) {
 155         DPRINTF(CachePort, "%s attempting to send a retry for response\n", name());
 156         //We have some responses to drain first
 157         if (sendTiming(drainList.front())) {
 158             DPRINTF(CachePort, "%s sucessful in sending a retry for response\n", name());
 159             drainList.pop_front();
 160             if (!drainList.empty() ||
 161                 !isCpuSide && cache->doMasterRequest() ||
 162                 isCpuSide && cache->doSlaveRequest()) {
 163
 164                 DPRINTF(CachePort, "%s has more responses/requests\n", name());
 165                 BaseCache::CacheEvent * reqCpu = new BaseCache::CacheEvent(this);
 166                 reqCpu->schedule(curTick + 1);
 167             }
 168             waitingOnRetry = false;
 169         }
 170     }
 171     else if (!isCpuSide)
 172     {
 173         DPRINTF(CachePort, "%s attempting to send a retry for MSHR\n", name());
 174         if (!cache->doMasterRequest()) {
 175             //This can happen if I am the owner of a block and see an upgrade
 176             //while the block was in my WB Buffers.  I just remove the
 177             //wb and de-assert the masterRequest
 178             waitingOnRetry = false;
 179             return;
 180         }
 181         pkt = cache->getPacket();
 182         MSHR* mshr = (MSHR*)pkt->senderState;
 183         //Copy the packet, it may be modified/destroyed elsewhere
 184         Packet * copyPkt = new Packet(*pkt);
 185         copyPkt->dataStatic<uint8_t>(pkt->getPtr<uint8_t>());
 186         mshr->pkt = copyPkt;
 187         bool success = sendTiming(pkt);
 188         DPRINTF(Cache, "Address %x was %s in sending the timing request\n",
 189                 pkt->getAddr(), success ? "succesful" : "unsuccesful");
 190         cache->sendResult(pkt, mshr, success);
 191         waitingOnRetry = !success;
 192         if (success && cache->doMasterRequest())
 193         {
 194             DPRINTF(CachePort, "%s has more requests\n", name());
 195             //Still more to issue, rerequest in 1 cycle
 196             BaseCache::CacheEvent * reqCpu = new BaseCache::CacheEvent(this);
 197             reqCpu->schedule(curTick + 1);
 198         }
 199     }
 200     else
 201     {
 202         assert(cache->doSlaveRequest());
 203         //pkt = cache->getCoherencePacket();
 204         //We save the packet, no reordering on CSHRS
 205         pkt = cache->getCoherencePacket();
 206         MSHR* cshr = (MSHR*)pkt->senderState;
 207         bool success = sendTiming(pkt);
 208         cache->sendCoherenceResult(pkt, cshr, success);
 209         waitingOnRetry = !success;
 210         if (success && cache->doSlaveRequest())
 211         {
 212             DPRINTF(CachePort, "%s has more requests\n", name());
 213             //Still more to issue, rerequest in 1 cycle
 214             BaseCache::CacheEvent * reqCpu = new BaseCache::CacheEvent(this);
 215             reqCpu->schedule(curTick + 1);
 216         }
 217     }
 218     if (waitingOnRetry) DPRINTF(CachePort, "%s STILL Waiting on retry\n", name());
 219     else DPRINTF(CachePort, "%s no longer waiting on retry\n", name());
 220     return;
 221 }
 222 void
 223 BaseCache::CachePort::setBlocked()
 224 {
 225     assert(!blocked);
 226     DPRINTF(Cache, "Cache Blocking\n");
 227     blocked = true;
 228     //Clear the retry flag
 229     mustSendRetry = false;
 230 }
 231
 232 void
 233 BaseCache::CachePort::clearBlocked()
 234 {
 235     assert(blocked);
 236     DPRINTF(Cache, "Cache Unblocking\n");
 237     blocked = false;
 238     if (mustSendRetry)
 239     {
 240         DPRINTF(Cache, "Cache Sending Retry\n");
 241         mustSendRetry = false;
 242         sendRetry();
 243     }
 244 }
 245
 246 BaseCache::CacheEvent::CacheEvent(CachePort *_cachePort)
 247     : Event(&mainEventQueue, CPU_Tick_Pri), cachePort(_cachePort)
 248 {
 249     this->setFlags(AutoDelete);
 250     pkt = NULL;
 251 }
 252
 253 BaseCache::CacheEvent::CacheEvent(CachePort *_cachePort, Packet *_pkt)
 254     : Event(&mainEventQueue, CPU_Tick_Pri), cachePort(_cachePort), pkt(_pkt)
 255 {
 256     this->setFlags(AutoDelete);
 257 }
 258
 259 void
 260 BaseCache::CacheEvent::process()
 261 {
 262     if (!pkt)
 263     {
 264         if (cachePort->waitingOnRetry) return;
 265        //We have some responses to drain first
 266         if (!cachePort->drainList.empty()) {
 267             DPRINTF(CachePort, "%s trying to drain a response\n", cachePort->name());
 268             if (cachePort->sendTiming(cachePort->drainList.front())) {
 269                 DPRINTF(CachePort, "%s drains a response succesfully\n", cachePort->name());
 270                 cachePort->drainList.pop_front();
 271                 if (!cachePort->drainList.empty() ||
 272                     !cachePort->isCpuSide && cachePort->cache->doMasterRequest() ||
 273                     cachePort->isCpuSide && cachePort->cache->doSlaveRequest()) {
 274
 275                     DPRINTF(CachePort, "%s still has outstanding bus reqs\n", cachePort->name());
 276                     this->schedule(curTick + 1);
 277                 }
 278             }
 279             else {
 280                 cachePort->waitingOnRetry = true;
 281                 DPRINTF(CachePort, "%s now waiting on a retry\n", cachePort->name());
 282             }
 283         }
 284         else if (!cachePort->isCpuSide)
 285         {            //MSHR
 286             DPRINTF(CachePort, "%s trying to send a MSHR request\n", cachePort->name());
 287             if (!cachePort->cache->doMasterRequest()) {
 288                 //This can happen if I am the owner of a block and see an upgrade
 289                 //while the block was in my WB Buffers.  I just remove the
 290                 //wb and de-assert the masterRequest
 291                 return;
 292             }
 293
 294             pkt = cachePort->cache->getPacket();
 295             MSHR* mshr = (MSHR*) pkt->senderState;
 296             //Copy the packet, it may be modified/destroyed elsewhere
 297             Packet * copyPkt = new Packet(*pkt);
 298             copyPkt->dataStatic<uint8_t>(pkt->getPtr<uint8_t>());
 299             mshr->pkt = copyPkt;
 300
 301             bool success = cachePort->sendTiming(pkt);
 302             DPRINTF(Cache, "Address %x was %s in sending the timing request\n",
 303                     pkt->getAddr(), success ? "succesful" : "unsuccesful");
 304             cachePort->cache->sendResult(pkt, mshr, success);
 305             cachePort->waitingOnRetry = !success;
 306             if (cachePort->waitingOnRetry)
 307                 DPRINTF(CachePort, "%s now waiting on a retry\n", cachePort->name());
 308             if (success && cachePort->cache->doMasterRequest())
 309             {
 310                 DPRINTF(CachePort, "%s still more MSHR requests to send\n",
 311                         cachePort->name());
 312                 //Still more to issue, rerequest in 1 cycle
 313                 pkt = NULL;
 314                 this->schedule(curTick+1);
 315             }
 316         }
 317         else
 318         {
 319             //CSHR
 320             assert(cachePort->cache->doSlaveRequest());
 321             pkt = cachePort->cache->getCoherencePacket();
 322             MSHR* cshr = (MSHR*) pkt->senderState;
 323             bool success = cachePort->sendTiming(pkt);
 324             cachePort->cache->sendResult(pkt, cshr, success);
 325             cachePort->waitingOnRetry = !success;
 326             if (cachePort->waitingOnRetry)
 327                 DPRINTF(CachePort, "%s now waiting on a retry\n", cachePort->name());
 328             if (success && cachePort->cache->doSlaveRequest())
 329             {
 330                 DPRINTF(CachePort, "%s still more CSHR requests to send\n",
 331                         cachePort->name());
 332                 //Still more to issue, rerequest in 1 cycle
 333                 pkt = NULL;
 334                 this->schedule(curTick+1);
 335             }
 336         }
 337         return;
 338     }
 339     //Response
 340     //Know the packet to send
 341     if (pkt->flags & NACKED_LINE)
 342         pkt->result = Packet::Nacked;
 343     else
 344         pkt->result = Packet::Success;
 345     pkt->makeTimingResponse();
 346     DPRINTF(CachePort, "%s attempting to send a response\n", cachePort->name());
 347     if (!cachePort->drainList.empty() || cachePort->waitingOnRetry) {
 348         //Already have a list, just append
 349         cachePort->drainList.push_back(pkt);
 350         DPRINTF(CachePort, "%s appending response onto drain list\n", cachePort->name());
 351     }
 352     else if (!cachePort->sendTiming(pkt)) {
 353         //It failed, save it to list of drain events
 354         DPRINTF(CachePort, "%s now waiting for a retry\n", cachePort->name());
 355         cachePort->drainList.push_back(pkt);
 356         cachePort->waitingOnRetry = true;
 357     }
 358 }
 359
 360 const char *
 361 BaseCache::CacheEvent::description()
 362 {
 363     return "timing event\n";
 364 }
 365
 366 Port*
 367 BaseCache::getPort(const std::string &if_name, int idx)
 368 {
 369     if (if_name == "")
 370     {
 371         if(cpuSidePort == NULL)
 372             cpuSidePort = new CachePort(name() + "-cpu_side_port", this, true);
 373         return cpuSidePort;
 374     }
 375     else if (if_name == "functional")
 376     {
 377         if(cpuSidePort == NULL)
 378             cpuSidePort = new CachePort(name() + "-cpu_side_port", this, true);
 379         return cpuSidePort;
 380     }
 381     else if (if_name == "cpu_side")
 382     {
 383         if(cpuSidePort == NULL)
 384             cpuSidePort = new CachePort(name() + "-cpu_side_port", this, true);
 385         return cpuSidePort;
 386     }
 387     else if (if_name == "mem_side")
 388     {
 389         if (memSidePort != NULL)
 390             panic("Already have a mem side for this cache\n");
 391         memSidePort = new CachePort(name() + "-mem_side_port", this, false);
 392         return memSidePort;
 393     }
 394     else panic("Port name %s unrecognized\n", if_name);
 395 }
 396
 397 void
 398 BaseCache::init()
 399 {
 400     if (!cpuSidePort || !memSidePort)
 401         panic("Cache not hooked up on both sides\n");
 402     cpuSidePort->sendStatusChange(Port::RangeChange);
 403 }
 404
 405 void
 406 BaseCache::regStats()
 407 {
 408     Request temp_req((Addr) NULL, 4, 0);
 409     Packet::Command temp_cmd = Packet::ReadReq;
 410     Packet temp_pkt(&temp_req, temp_cmd, 0);  //@todo FIx command strings so this isn't neccessary
 411     temp_pkt.allocate(); //Temp allocate, all need data
 412
 413     using namespace Stats;
 414
 415     // Hit statistics
 416     for (int access_idx = 0; access_idx < NUM_MEM_CMDS; ++access_idx) {
 417         Packet::Command cmd = (Packet::Command)access_idx;
 418         const string &cstr = temp_pkt.cmdIdxToString(cmd);
 419
 420         hits[access_idx]
 421             .init(maxThreadsPerCPU)
 422             .name(name() + "." + cstr + "_hits")
 423             .desc("number of " + cstr + " hits")
 424             .flags(total | nozero | nonan)
 425             ;
 426     }
 427
 428     demandHits
 429         .name(name() + ".demand_hits")
 430         .desc("number of demand (read+write) hits")
 431         .flags(total)
 432         ;
 433     demandHits = hits[Packet::ReadReq] + hits[Packet::WriteReq];
 434
 435     overallHits
 436         .name(name() + ".overall_hits")
 437         .desc("number of overall hits")
 438         .flags(total)
 439         ;
 440     overallHits = demandHits + hits[Packet::SoftPFReq] + hits[Packet::HardPFReq]
 441         + hits[Packet::Writeback];
 442
 443     // Miss statistics
 444     for (int access_idx = 0; access_idx < NUM_MEM_CMDS; ++access_idx) {
 445         Packet::Command cmd = (Packet::Command)access_idx;
 446         const string &cstr = temp_pkt.cmdIdxToString(cmd);
 447
 448         misses[access_idx]
 449             .init(maxThreadsPerCPU)
 450             .name(name() + "." + cstr + "_misses")
 451             .desc("number of " + cstr + " misses")
 452             .flags(total | nozero | nonan)
 453             ;
 454     }
 455
 456     demandMisses
 457         .name(name() + ".demand_misses")
 458         .desc("number of demand (read+write) misses")
 459         .flags(total)
 460         ;
 461     demandMisses = misses[Packet::ReadReq] + misses[Packet::WriteReq];
 462
 463     overallMisses
 464         .name(name() + ".overall_misses")
 465         .desc("number of overall misses")
 466         .flags(total)
 467         ;
 468     overallMisses = demandMisses + misses[Packet::SoftPFReq] +
 469         misses[Packet::HardPFReq] + misses[Packet::Writeback];
 470
 471     // Miss latency statistics
 472     for (int access_idx = 0; access_idx < NUM_MEM_CMDS; ++access_idx) {
 473         Packet::Command cmd = (Packet::Command)access_idx;
 474         const string &cstr = temp_pkt.cmdIdxToString(cmd);
 475
 476         missLatency[access_idx]
 477             .init(maxThreadsPerCPU)
 478             .name(name() + "." + cstr + "_miss_latency")
 479             .desc("number of " + cstr + " miss cycles")
 480             .flags(total | nozero | nonan)
 481             ;
 482     }
 483
 484     demandMissLatency
 485         .name(name() + ".demand_miss_latency")
 486         .desc("number of demand (read+write) miss cycles")
 487         .flags(total)
 488         ;
 489     demandMissLatency = missLatency[Packet::ReadReq] + missLatency[Packet::WriteReq];
 490
 491     overallMissLatency
 492         .name(name() + ".overall_miss_latency")
 493         .desc("number of overall miss cycles")
 494         .flags(total)
 495         ;
 496     overallMissLatency = demandMissLatency + missLatency[Packet::SoftPFReq] +
 497         missLatency[Packet::HardPFReq];
 498
 499     // access formulas
 500     for (int access_idx = 0; access_idx < NUM_MEM_CMDS; ++access_idx) {
 501         Packet::Command cmd = (Packet::Command)access_idx;
 502         const string &cstr = temp_pkt.cmdIdxToString(cmd);
 503
 504         accesses[access_idx]
 505             .name(name() + "." + cstr + "_accesses")
 506             .desc("number of " + cstr + " accesses(hits+misses)")
 507             .flags(total | nozero | nonan)
 508             ;
 509
 510         accesses[access_idx] = hits[access_idx] + misses[access_idx];
 511     }
 512
 513     demandAccesses
 514         .name(name() + ".demand_accesses")
 515         .desc("number of demand (read+write) accesses")
 516         .flags(total)
 517         ;
 518     demandAccesses = demandHits + demandMisses;
 519
 520     overallAccesses
 521         .name(name() + ".overall_accesses")
 522         .desc("number of overall (read+write) accesses")
 523         .flags(total)
 524         ;
 525     overallAccesses = overallHits + overallMisses;
 526
 527     // miss rate formulas
 528     for (int access_idx = 0; access_idx < NUM_MEM_CMDS; ++access_idx) {
 529         Packet::Command cmd = (Packet::Command)access_idx;
 530         const string &cstr = temp_pkt.cmdIdxToString(cmd);
 531
 532         missRate[access_idx]
 533             .name(name() + "." + cstr + "_miss_rate")
 534             .desc("miss rate for " + cstr + " accesses")
 535             .flags(total | nozero | nonan)
 536             ;
 537
 538         missRate[access_idx] = misses[access_idx] / accesses[access_idx];
 539     }
 540
 541     demandMissRate
 542         .name(name() + ".demand_miss_rate")
 543         .desc("miss rate for demand accesses")
 544         .flags(total)
 545         ;
 546     demandMissRate = demandMisses / demandAccesses;
 547
 548     overallMissRate
 549         .name(name() + ".overall_miss_rate")
 550         .desc("miss rate for overall accesses")
 551         .flags(total)
 552         ;
 553     overallMissRate = overallMisses / overallAccesses;
 554
 555     // miss latency formulas
 556     for (int access_idx = 0; access_idx < NUM_MEM_CMDS; ++access_idx) {
 557         Packet::Command cmd = (Packet::Command)access_idx;
 558         const string &cstr = temp_pkt.cmdIdxToString(cmd);
 559
 560         avgMissLatency[access_idx]
 561             .name(name() + "." + cstr + "_avg_miss_latency")
 562             .desc("average " + cstr + " miss latency")
 563             .flags(total | nozero | nonan)
 564             ;
 565
 566         avgMissLatency[access_idx] =
 567             missLatency[access_idx] / misses[access_idx];
 568     }
 569
 570     demandAvgMissLatency
 571         .name(name() + ".demand_avg_miss_latency")
 572         .desc("average overall miss latency")
 573         .flags(total)
 574         ;
 575     demandAvgMissLatency = demandMissLatency / demandMisses;
 576
 577     overallAvgMissLatency
 578         .name(name() + ".overall_avg_miss_latency")
 579         .desc("average overall miss latency")
 580         .flags(total)
 581         ;
 582     overallAvgMissLatency = overallMissLatency / overallMisses;
 583
 584     blocked_cycles.init(NUM_BLOCKED_CAUSES);
 585     blocked_cycles
 586         .name(name() + ".blocked_cycles")
 587         .desc("number of cycles access was blocked")
 588         .subname(Blocked_NoMSHRs, "no_mshrs")
 589         .subname(Blocked_NoTargets, "no_targets")
 590         ;
 591
 592
 593     blocked_causes.init(NUM_BLOCKED_CAUSES);
 594     blocked_causes
 595         .name(name() + ".blocked")
 596         .desc("number of cycles access was blocked")
 597         .subname(Blocked_NoMSHRs, "no_mshrs")
 598         .subname(Blocked_NoTargets, "no_targets")
 599         ;
 600
 601     avg_blocked
 602         .name(name() + ".avg_blocked_cycles")
 603         .desc("average number of cycles each access was blocked")
 604         .subname(Blocked_NoMSHRs, "no_mshrs")
 605         .subname(Blocked_NoTargets, "no_targets")
 606         ;
 607
 608     avg_blocked = blocked_cycles / blocked_causes;
 609
 610     fastWrites
 611         .name(name() + ".fast_writes")
 612         .desc("number of fast writes performed")
 613         ;
 614
 615     cacheCopies
 616         .name(name() + ".cache_copies")
 617         .desc("number of cache copies performed")
 618         ;
 619
 620 }