2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Authors: Erik Hallnor
33 * Definition of BaseCache functions.
36 #include "mem/cache/base_cache.hh"
37 #include "mem/cache/miss/mshr.hh"
38 #include "mem/packet_impl.hh"
40 #include "cpu/base.hh"
44 BaseCache::CachePort::CachePort(const std::string
&_name
, BaseCache
*_cache
,
46 : Port(_name
), cache(_cache
), isCpuSide(_isCpuSide
)
49 waitingOnRetry
= false;
50 //Start ports at null if more than one is created we should panic
56 BaseCache::CachePort::recvStatusChange(Port::Status status
)
58 cache
->recvStatusChange(status
, isCpuSide
);
62 BaseCache::CachePort::getDeviceAddressRanges(AddrRangeList
&resp
,
65 cache
->getAddressRanges(resp
, snoop
, isCpuSide
);
69 BaseCache::CachePort::deviceBlockSize()
71 return cache
->getBlockSize();
75 BaseCache::CachePort::recvTiming(Packet
*pkt
)
78 && !pkt
->req
->isUncacheable()
79 && pkt
->isInvalidate()
80 && !pkt
->isRead() && !pkt
->isWrite()) {
81 //Upgrade or Invalidate
82 //Look into what happens if two slave caches on bus
83 DPRINTF(Cache
, "%s %x ? blk_addr: %x\n", pkt
->cmdString(),
84 pkt
->getAddr() & (((ULL(1))<<48)-1),
85 pkt
->getAddr() & ~((Addr
)cache
->blkSize
- 1));
87 assert(!(pkt
->flags
& SATISFIED
));
88 pkt
->flags
|= SATISFIED
;
89 //Invalidates/Upgrades need no response if they get the bus
93 if (pkt
->isRequest() && blocked
)
95 DPRINTF(Cache
,"Scheduling a retry while blocked\n");
99 return cache
->doTimingAccess(pkt
, this, isCpuSide
);
103 BaseCache::CachePort::recvAtomic(Packet
*pkt
)
105 return cache
->doAtomicAccess(pkt
, isCpuSide
);
109 BaseCache::CachePort::recvFunctional(Packet
*pkt
)
111 //Check storage here first
112 list
<Packet
*>::iterator i
= drainList
.begin();
113 list
<Packet
*>::iterator end
= drainList
.end();
114 for (; i
!= end
; ++i
) {
115 Packet
* target
= *i
;
116 // If the target contains data, and it overlaps the
117 // probed request, need to update data
118 if (target
->intersect(pkt
)) {
122 if (target
->getAddr() < pkt
->getAddr()) {
123 int offset
= pkt
->getAddr() - target
->getAddr();
124 pkt_data
= pkt
->getPtr
<uint8_t>();
125 write_data
= target
->getPtr
<uint8_t>() + offset
;
126 data_size
= target
->getSize() - offset
;
127 assert(data_size
> 0);
128 if (data_size
> pkt
->getSize())
129 data_size
= pkt
->getSize();
131 int offset
= target
->getAddr() - pkt
->getAddr();
132 pkt_data
= pkt
->getPtr
<uint8_t>() + offset
;
133 write_data
= target
->getPtr
<uint8_t>();
134 data_size
= pkt
->getSize() - offset
;
135 assert(data_size
>= pkt
->getSize());
136 if (data_size
> target
->getSize())
137 data_size
= target
->getSize();
140 if (pkt
->isWrite()) {
141 memcpy(pkt_data
, write_data
, data_size
);
143 memcpy(write_data
, pkt_data
, data_size
);
147 cache
->doFunctionalAccess(pkt
, isCpuSide
);
151 BaseCache::CachePort::recvRetry()
154 assert(waitingOnRetry
);
155 if (!drainList
.empty()) {
156 DPRINTF(CachePort
, "%s attempting to send a retry for response\n", name());
157 //We have some responses to drain first
158 if (sendTiming(drainList
.front())) {
159 DPRINTF(CachePort
, "%s sucessful in sending a retry for response\n", name());
160 drainList
.pop_front();
161 if (!drainList
.empty() ||
162 !isCpuSide
&& cache
->doMasterRequest() ||
163 isCpuSide
&& cache
->doSlaveRequest()) {
165 DPRINTF(CachePort
, "%s has more responses/requests\n", name());
166 BaseCache::CacheEvent
* reqCpu
= new BaseCache::CacheEvent(this);
167 reqCpu
->schedule(curTick
+ 1);
169 waitingOnRetry
= false;
174 DPRINTF(CachePort
, "%s attempting to send a retry for MSHR\n", name());
175 if (!cache
->doMasterRequest()) {
176 //This can happen if I am the owner of a block and see an upgrade
177 //while the block was in my WB Buffers. I just remove the
178 //wb and de-assert the masterRequest
179 waitingOnRetry
= false;
182 pkt
= cache
->getPacket();
183 MSHR
* mshr
= (MSHR
*) pkt
->senderState
;
184 //Copy the packet, it may be modified/destroyed elsewhere
185 Packet
* copyPkt
= new Packet(*pkt
);
186 copyPkt
->dataStatic
<uint8_t>(pkt
->getPtr
<uint8_t>());
189 bool success
= sendTiming(pkt
);
190 DPRINTF(Cache
, "Address %x was %s in sending the timing request\n",
191 pkt
->getAddr(), success
? "succesful" : "unsuccesful");
193 waitingOnRetry
= !success
;
194 if (waitingOnRetry
) {
195 DPRINTF(CachePort
, "%s now waiting on a retry\n", name());
198 cache
->sendResult(pkt
, mshr
, success
);
200 if (success
&& cache
->doMasterRequest())
202 DPRINTF(CachePort
, "%s has more requests\n", name());
203 //Still more to issue, rerequest in 1 cycle
204 BaseCache::CacheEvent
* reqCpu
= new BaseCache::CacheEvent(this);
205 reqCpu
->schedule(curTick
+ 1);
210 assert(cache
->doSlaveRequest());
211 //pkt = cache->getCoherencePacket();
212 //We save the packet, no reordering on CSHRS
213 pkt
= cache
->getCoherencePacket();
214 MSHR
* cshr
= (MSHR
*)pkt
->senderState
;
215 bool success
= sendTiming(pkt
);
216 cache
->sendCoherenceResult(pkt
, cshr
, success
);
217 waitingOnRetry
= !success
;
218 if (success
&& cache
->doSlaveRequest())
220 DPRINTF(CachePort
, "%s has more requests\n", name());
221 //Still more to issue, rerequest in 1 cycle
222 BaseCache::CacheEvent
* reqCpu
= new BaseCache::CacheEvent(this);
223 reqCpu
->schedule(curTick
+ 1);
226 if (waitingOnRetry
) DPRINTF(CachePort
, "%s STILL Waiting on retry\n", name());
227 else DPRINTF(CachePort
, "%s no longer waiting on retry\n", name());
231 BaseCache::CachePort::setBlocked()
234 DPRINTF(Cache
, "Cache Blocking\n");
236 //Clear the retry flag
237 mustSendRetry
= false;
241 BaseCache::CachePort::clearBlocked()
244 DPRINTF(Cache
, "Cache Unblocking\n");
248 DPRINTF(Cache
, "Cache Sending Retry\n");
249 mustSendRetry
= false;
254 BaseCache::CacheEvent::CacheEvent(CachePort
*_cachePort
)
255 : Event(&mainEventQueue
, CPU_Tick_Pri
), cachePort(_cachePort
)
257 this->setFlags(AutoDelete
);
261 BaseCache::CacheEvent::CacheEvent(CachePort
*_cachePort
, Packet
*_pkt
)
262 : Event(&mainEventQueue
, CPU_Tick_Pri
), cachePort(_cachePort
), pkt(_pkt
)
264 this->setFlags(AutoDelete
);
268 BaseCache::CacheEvent::process()
272 if (cachePort
->waitingOnRetry
) return;
273 //We have some responses to drain first
274 if (!cachePort
->drainList
.empty()) {
275 DPRINTF(CachePort
, "%s trying to drain a response\n", cachePort
->name());
276 if (cachePort
->sendTiming(cachePort
->drainList
.front())) {
277 DPRINTF(CachePort
, "%s drains a response succesfully\n", cachePort
->name());
278 cachePort
->drainList
.pop_front();
279 if (!cachePort
->drainList
.empty() ||
280 !cachePort
->isCpuSide
&& cachePort
->cache
->doMasterRequest() ||
281 cachePort
->isCpuSide
&& cachePort
->cache
->doSlaveRequest()) {
283 DPRINTF(CachePort
, "%s still has outstanding bus reqs\n", cachePort
->name());
284 this->schedule(curTick
+ 1);
288 cachePort
->waitingOnRetry
= true;
289 DPRINTF(CachePort
, "%s now waiting on a retry\n", cachePort
->name());
292 else if (!cachePort
->isCpuSide
)
294 DPRINTF(CachePort
, "%s trying to send a MSHR request\n", cachePort
->name());
295 if (!cachePort
->cache
->doMasterRequest()) {
296 //This can happen if I am the owner of a block and see an upgrade
297 //while the block was in my WB Buffers. I just remove the
298 //wb and de-assert the masterRequest
302 pkt
= cachePort
->cache
->getPacket();
303 MSHR
* mshr
= (MSHR
*) pkt
->senderState
;
304 //Copy the packet, it may be modified/destroyed elsewhere
305 Packet
* copyPkt
= new Packet(*pkt
);
306 copyPkt
->dataStatic
<uint8_t>(pkt
->getPtr
<uint8_t>());
309 bool success
= cachePort
->sendTiming(pkt
);
310 DPRINTF(Cache
, "Address %x was %s in sending the timing request\n",
311 pkt
->getAddr(), success
? "succesful" : "unsuccesful");
313 cachePort
->waitingOnRetry
= !success
;
314 if (cachePort
->waitingOnRetry
) {
315 DPRINTF(CachePort
, "%s now waiting on a retry\n", cachePort
->name());
318 cachePort
->cache
->sendResult(pkt
, mshr
, success
);
319 if (success
&& cachePort
->cache
->doMasterRequest())
321 DPRINTF(CachePort
, "%s still more MSHR requests to send\n",
323 //Still more to issue, rerequest in 1 cycle
325 this->schedule(curTick
+1);
331 assert(cachePort
->cache
->doSlaveRequest());
332 pkt
= cachePort
->cache
->getCoherencePacket();
333 MSHR
* cshr
= (MSHR
*) pkt
->senderState
;
334 bool success
= cachePort
->sendTiming(pkt
);
335 cachePort
->cache
->sendCoherenceResult(pkt
, cshr
, success
);
336 cachePort
->waitingOnRetry
= !success
;
337 if (cachePort
->waitingOnRetry
)
338 DPRINTF(CachePort
, "%s now waiting on a retry\n", cachePort
->name());
339 if (success
&& cachePort
->cache
->doSlaveRequest())
341 DPRINTF(CachePort
, "%s still more CSHR requests to send\n",
343 //Still more to issue, rerequest in 1 cycle
345 this->schedule(curTick
+1);
351 //Know the packet to send
352 if (pkt
->flags
& NACKED_LINE
)
353 pkt
->result
= Packet::Nacked
;
355 pkt
->result
= Packet::Success
;
356 pkt
->makeTimingResponse();
357 DPRINTF(CachePort
, "%s attempting to send a response\n", cachePort
->name());
358 if (!cachePort
->drainList
.empty() || cachePort
->waitingOnRetry
) {
359 //Already have a list, just append
360 cachePort
->drainList
.push_back(pkt
);
361 DPRINTF(CachePort
, "%s appending response onto drain list\n", cachePort
->name());
363 else if (!cachePort
->sendTiming(pkt
)) {
364 //It failed, save it to list of drain events
365 DPRINTF(CachePort
, "%s now waiting for a retry\n", cachePort
->name());
366 cachePort
->drainList
.push_back(pkt
);
367 cachePort
->waitingOnRetry
= true;
372 BaseCache::CacheEvent::description()
374 return "timing event\n";
378 BaseCache::getPort(const std::string
&if_name
, int idx
)
382 if(cpuSidePort
== NULL
)
383 cpuSidePort
= new CachePort(name() + "-cpu_side_port", this, true);
386 else if (if_name
== "functional")
388 if(cpuSidePort
== NULL
)
389 cpuSidePort
= new CachePort(name() + "-cpu_side_port", this, true);
392 else if (if_name
== "cpu_side")
394 if(cpuSidePort
== NULL
)
395 cpuSidePort
= new CachePort(name() + "-cpu_side_port", this, true);
398 else if (if_name
== "mem_side")
400 if (memSidePort
!= NULL
)
401 panic("Already have a mem side for this cache\n");
402 memSidePort
= new CachePort(name() + "-mem_side_port", this, false);
405 else panic("Port name %s unrecognized\n", if_name
);
411 if (!cpuSidePort
|| !memSidePort
)
412 panic("Cache not hooked up on both sides\n");
413 cpuSidePort
->sendStatusChange(Port::RangeChange
);
417 BaseCache::regStats()
419 Request
temp_req((Addr
) NULL
, 4, 0);
420 Packet::Command temp_cmd
= Packet::ReadReq
;
421 Packet
temp_pkt(&temp_req
, temp_cmd
, 0); //@todo FIx command strings so this isn't neccessary
422 temp_pkt
.allocate(); //Temp allocate, all need data
424 using namespace Stats
;
427 for (int access_idx
= 0; access_idx
< NUM_MEM_CMDS
; ++access_idx
) {
428 Packet::Command cmd
= (Packet::Command
)access_idx
;
429 const string
&cstr
= temp_pkt
.cmdIdxToString(cmd
);
432 .init(maxThreadsPerCPU
)
433 .name(name() + "." + cstr
+ "_hits")
434 .desc("number of " + cstr
+ " hits")
435 .flags(total
| nozero
| nonan
)
440 .name(name() + ".demand_hits")
441 .desc("number of demand (read+write) hits")
444 demandHits
= hits
[Packet::ReadReq
] + hits
[Packet::WriteReq
];
447 .name(name() + ".overall_hits")
448 .desc("number of overall hits")
451 overallHits
= demandHits
+ hits
[Packet::SoftPFReq
] + hits
[Packet::HardPFReq
]
452 + hits
[Packet::Writeback
];
455 for (int access_idx
= 0; access_idx
< NUM_MEM_CMDS
; ++access_idx
) {
456 Packet::Command cmd
= (Packet::Command
)access_idx
;
457 const string
&cstr
= temp_pkt
.cmdIdxToString(cmd
);
460 .init(maxThreadsPerCPU
)
461 .name(name() + "." + cstr
+ "_misses")
462 .desc("number of " + cstr
+ " misses")
463 .flags(total
| nozero
| nonan
)
468 .name(name() + ".demand_misses")
469 .desc("number of demand (read+write) misses")
472 demandMisses
= misses
[Packet::ReadReq
] + misses
[Packet::WriteReq
];
475 .name(name() + ".overall_misses")
476 .desc("number of overall misses")
479 overallMisses
= demandMisses
+ misses
[Packet::SoftPFReq
] +
480 misses
[Packet::HardPFReq
] + misses
[Packet::Writeback
];
482 // Miss latency statistics
483 for (int access_idx
= 0; access_idx
< NUM_MEM_CMDS
; ++access_idx
) {
484 Packet::Command cmd
= (Packet::Command
)access_idx
;
485 const string
&cstr
= temp_pkt
.cmdIdxToString(cmd
);
487 missLatency
[access_idx
]
488 .init(maxThreadsPerCPU
)
489 .name(name() + "." + cstr
+ "_miss_latency")
490 .desc("number of " + cstr
+ " miss cycles")
491 .flags(total
| nozero
| nonan
)
496 .name(name() + ".demand_miss_latency")
497 .desc("number of demand (read+write) miss cycles")
500 demandMissLatency
= missLatency
[Packet::ReadReq
] + missLatency
[Packet::WriteReq
];
503 .name(name() + ".overall_miss_latency")
504 .desc("number of overall miss cycles")
507 overallMissLatency
= demandMissLatency
+ missLatency
[Packet::SoftPFReq
] +
508 missLatency
[Packet::HardPFReq
];
511 for (int access_idx
= 0; access_idx
< NUM_MEM_CMDS
; ++access_idx
) {
512 Packet::Command cmd
= (Packet::Command
)access_idx
;
513 const string
&cstr
= temp_pkt
.cmdIdxToString(cmd
);
516 .name(name() + "." + cstr
+ "_accesses")
517 .desc("number of " + cstr
+ " accesses(hits+misses)")
518 .flags(total
| nozero
| nonan
)
521 accesses
[access_idx
] = hits
[access_idx
] + misses
[access_idx
];
525 .name(name() + ".demand_accesses")
526 .desc("number of demand (read+write) accesses")
529 demandAccesses
= demandHits
+ demandMisses
;
532 .name(name() + ".overall_accesses")
533 .desc("number of overall (read+write) accesses")
536 overallAccesses
= overallHits
+ overallMisses
;
538 // miss rate formulas
539 for (int access_idx
= 0; access_idx
< NUM_MEM_CMDS
; ++access_idx
) {
540 Packet::Command cmd
= (Packet::Command
)access_idx
;
541 const string
&cstr
= temp_pkt
.cmdIdxToString(cmd
);
544 .name(name() + "." + cstr
+ "_miss_rate")
545 .desc("miss rate for " + cstr
+ " accesses")
546 .flags(total
| nozero
| nonan
)
549 missRate
[access_idx
] = misses
[access_idx
] / accesses
[access_idx
];
553 .name(name() + ".demand_miss_rate")
554 .desc("miss rate for demand accesses")
557 demandMissRate
= demandMisses
/ demandAccesses
;
560 .name(name() + ".overall_miss_rate")
561 .desc("miss rate for overall accesses")
564 overallMissRate
= overallMisses
/ overallAccesses
;
566 // miss latency formulas
567 for (int access_idx
= 0; access_idx
< NUM_MEM_CMDS
; ++access_idx
) {
568 Packet::Command cmd
= (Packet::Command
)access_idx
;
569 const string
&cstr
= temp_pkt
.cmdIdxToString(cmd
);
571 avgMissLatency
[access_idx
]
572 .name(name() + "." + cstr
+ "_avg_miss_latency")
573 .desc("average " + cstr
+ " miss latency")
574 .flags(total
| nozero
| nonan
)
577 avgMissLatency
[access_idx
] =
578 missLatency
[access_idx
] / misses
[access_idx
];
582 .name(name() + ".demand_avg_miss_latency")
583 .desc("average overall miss latency")
586 demandAvgMissLatency
= demandMissLatency
/ demandMisses
;
588 overallAvgMissLatency
589 .name(name() + ".overall_avg_miss_latency")
590 .desc("average overall miss latency")
593 overallAvgMissLatency
= overallMissLatency
/ overallMisses
;
595 blocked_cycles
.init(NUM_BLOCKED_CAUSES
);
597 .name(name() + ".blocked_cycles")
598 .desc("number of cycles access was blocked")
599 .subname(Blocked_NoMSHRs
, "no_mshrs")
600 .subname(Blocked_NoTargets
, "no_targets")
604 blocked_causes
.init(NUM_BLOCKED_CAUSES
);
606 .name(name() + ".blocked")
607 .desc("number of cycles access was blocked")
608 .subname(Blocked_NoMSHRs
, "no_mshrs")
609 .subname(Blocked_NoTargets
, "no_targets")
613 .name(name() + ".avg_blocked_cycles")
614 .desc("average number of cycles each access was blocked")
615 .subname(Blocked_NoMSHRs
, "no_mshrs")
616 .subname(Blocked_NoTargets
, "no_targets")
619 avg_blocked
= blocked_cycles
/ blocked_causes
;
622 .name(name() + ".fast_writes")
623 .desc("number of fast writes performed")
627 .name(name() + ".cache_copies")
628 .desc("number of cache copies performed")