src/mem/cache/base_cache.cc

   1 /*
   2  * Copyright (c) 2003-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Erik Hallnor
  29  */
  30
  31 /**
  32  * @file
  33  * Definition of BaseCache functions.
  34  */
  35
  36 #include "mem/cache/base_cache.hh"
  37 #include "cpu/smt.hh"
  38 #include "cpu/base.hh"
  39
  40 using namespace std;
  41
  42 BaseCache::CachePort::CachePort(const std::string &_name, BaseCache *_cache,
  43                                 bool _isCpuSide)
  44     : Port(_name), cache(_cache), isCpuSide(_isCpuSide)
  45 {
  46     blocked = false;
  47     waitingOnRetry = false;
  48     //Start ports at null if more than one is created we should panic
  49     //cpuSidePort = NULL;
  50     //memSidePort = NULL;
  51 }
  52
  53 void
  54 BaseCache::CachePort::recvStatusChange(Port::Status status)
  55 {
  56     cache->recvStatusChange(status, isCpuSide);
  57 }
  58
  59 void
  60 BaseCache::CachePort::getDeviceAddressRanges(AddrRangeList &resp,
  61                                        AddrRangeList &snoop)
  62 {
  63     cache->getAddressRanges(resp, snoop, isCpuSide);
  64 }
  65
  66 int
  67 BaseCache::CachePort::deviceBlockSize()
  68 {
  69     return cache->getBlockSize();
  70 }
  71
  72 bool
  73 BaseCache::CachePort::recvTiming(Packet *pkt)
  74 {
  75     if (isCpuSide
  76         && !pkt->req->isUncacheable()
  77         && pkt->isInvalidate()
  78         && !pkt->isRead() && !pkt->isWrite()) {
  79         //Upgrade or Invalidate
  80         //Look into what happens if two slave caches on bus
  81         DPRINTF(Cache, "%s %x ? blk_addr: %x\n", pkt->cmdString(),
  82                 pkt->getAddr() & (((ULL(1))<<48)-1),
  83                 pkt->getAddr() & ~((Addr)cache->blkSize - 1));
  84
  85         assert(!(pkt->flags & SATISFIED));
  86         pkt->flags |= SATISFIED;
  87         //Invalidates/Upgrades need no response if they get the bus
  88         return true;
  89     }
  90
  91     if (pkt->isRequest() && blocked)
  92     {
  93         DPRINTF(Cache,"Scheduling a retry while blocked\n");
  94         mustSendRetry = true;
  95         return false;
  96     }
  97     return cache->doTimingAccess(pkt, this, isCpuSide);
  98 }
  99
 100 Tick
 101 BaseCache::CachePort::recvAtomic(Packet *pkt)
 102 {
 103     return cache->doAtomicAccess(pkt, isCpuSide);
 104 }
 105
 106 void
 107 BaseCache::CachePort::recvFunctional(Packet *pkt)
 108 {
 109     //Check storage here first
 110     list<Packet *>::iterator i = drainList.begin();
 111     list<Packet *>::iterator end = drainList.end();
 112     for (; i != end; ++i) {
 113         Packet * target = *i;
 114         // If the target contains data, and it overlaps the
 115         // probed request, need to update data
 116         if (target->intersect(pkt)) {
 117             uint8_t* pkt_data;
 118             uint8_t* write_data;
 119             int data_size;
 120             if (target->getAddr() < pkt->getAddr()) {
 121                 int offset = pkt->getAddr() - target->getAddr();
 122                             pkt_data = pkt->getPtr<uint8_t>();
 123                             write_data = target->getPtr<uint8_t>() + offset;
 124                             data_size = target->getSize() - offset;
 125                             assert(data_size > 0);
 126                             if (data_size > pkt->getSize())
 127                                 data_size = pkt->getSize();
 128             } else {
 129                 int offset = target->getAddr() - pkt->getAddr();
 130                 pkt_data = pkt->getPtr<uint8_t>() + offset;
 131                 write_data = target->getPtr<uint8_t>();
 132                 data_size = pkt->getSize() - offset;
 133                 assert(data_size > pkt->getSize());
 134                 if (data_size > target->getSize())
 135                     data_size = target->getSize();
 136             }
 137
 138             if (pkt->isWrite()) {
 139                 memcpy(pkt_data, write_data, data_size);
 140             } else {
 141                 memcpy(write_data, pkt_data, data_size);
 142             }
 143         }
 144     }
 145     cache->doFunctionalAccess(pkt, isCpuSide);
 146 }
 147
 148 void
 149 BaseCache::CachePort::recvRetry()
 150 {
 151     Packet *pkt;
 152     assert(waitingOnRetry);
 153     if (!drainList.empty()) {
 154         DPRINTF(CachePort, "%s attempting to send a retry for response\n", name());
 155         //We have some responses to drain first
 156         if (sendTiming(drainList.front())) {
 157             DPRINTF(CachePort, "%s sucessful in sending a retry for response\n", name());
 158             drainList.pop_front();
 159             if (!drainList.empty() ||
 160                 !isCpuSide && cache->doMasterRequest() ||
 161                 isCpuSide && cache->doSlaveRequest()) {
 162
 163                 DPRINTF(CachePort, "%s has more responses/requests\n", name());
 164                 BaseCache::CacheEvent * reqCpu = new BaseCache::CacheEvent(this);
 165                 reqCpu->schedule(curTick + 1);
 166             }
 167             waitingOnRetry = false;
 168         }
 169     }
 170     else if (!isCpuSide)
 171     {
 172         DPRINTF(CachePort, "%s attempting to send a retry for MSHR\n", name());
 173         if (!cache->doMasterRequest()) {
 174             //This can happen if I am the owner of a block and see an upgrade
 175             //while the block was in my WB Buffers.  I just remove the
 176             //wb and de-assert the masterRequest
 177             waitingOnRetry = false;
 178             return;
 179         }
 180         pkt = cache->getPacket();
 181         MSHR* mshr = (MSHR*)pkt->senderState;
 182         bool success = sendTiming(pkt);
 183         DPRINTF(Cache, "Address %x was %s in sending the timing request\n",
 184                 pkt->getAddr(), success ? "succesful" : "unsuccesful");
 185         cache->sendResult(pkt, mshr, success);
 186         waitingOnRetry = !success;
 187         if (success && cache->doMasterRequest())
 188         {
 189             DPRINTF(CachePort, "%s has more requests\n", name());
 190             //Still more to issue, rerequest in 1 cycle
 191             BaseCache::CacheEvent * reqCpu = new BaseCache::CacheEvent(this);
 192             reqCpu->schedule(curTick + 1);
 193         }
 194     }
 195     else
 196     {
 197         assert(cache->doSlaveRequest());
 198         //pkt = cache->getCoherencePacket();
 199         //We save the packet, no reordering on CSHRS
 200         pkt = cache->getCoherencePacket();
 201         MSHR* cshr = (MSHR*)pkt->senderState;
 202         bool success = sendTiming(pkt);
 203         cache->sendCoherenceResult(pkt, cshr, success);
 204         waitingOnRetry = !success;
 205         if (success && cache->doSlaveRequest())
 206         {
 207             DPRINTF(CachePort, "%s has more requests\n", name());
 208             //Still more to issue, rerequest in 1 cycle
 209             BaseCache::CacheEvent * reqCpu = new BaseCache::CacheEvent(this);
 210             reqCpu->schedule(curTick + 1);
 211         }
 212     }
 213     if (waitingOnRetry) DPRINTF(CachePort, "%s STILL Waiting on retry\n", name());
 214     else DPRINTF(CachePort, "%s no longer waiting on retry\n", name());
 215     return;
 216 }
 217 void
 218 BaseCache::CachePort::setBlocked()
 219 {
 220     assert(!blocked);
 221     DPRINTF(Cache, "Cache Blocking\n");
 222     blocked = true;
 223     //Clear the retry flag
 224     mustSendRetry = false;
 225 }
 226
 227 void
 228 BaseCache::CachePort::clearBlocked()
 229 {
 230     assert(blocked);
 231     DPRINTF(Cache, "Cache Unblocking\n");
 232     blocked = false;
 233     if (mustSendRetry)
 234     {
 235         DPRINTF(Cache, "Cache Sending Retry\n");
 236         mustSendRetry = false;
 237         sendRetry();
 238     }
 239 }
 240
 241 BaseCache::CacheEvent::CacheEvent(CachePort *_cachePort)
 242     : Event(&mainEventQueue, CPU_Tick_Pri), cachePort(_cachePort)
 243 {
 244     this->setFlags(AutoDelete);
 245     pkt = NULL;
 246 }
 247
 248 BaseCache::CacheEvent::CacheEvent(CachePort *_cachePort, Packet *_pkt)
 249     : Event(&mainEventQueue, CPU_Tick_Pri), cachePort(_cachePort), pkt(_pkt)
 250 {
 251     this->setFlags(AutoDelete);
 252 }
 253
 254 void
 255 BaseCache::CacheEvent::process()
 256 {
 257     if (!pkt)
 258     {
 259         if (cachePort->waitingOnRetry) return;
 260        //We have some responses to drain first
 261         if (!cachePort->drainList.empty()) {
 262             DPRINTF(CachePort, "%s trying to drain a response\n", cachePort->name());
 263             if (cachePort->sendTiming(cachePort->drainList.front())) {
 264                 DPRINTF(CachePort, "%s drains a response succesfully\n", cachePort->name());
 265                 cachePort->drainList.pop_front();
 266                 if (!cachePort->drainList.empty() ||
 267                     !cachePort->isCpuSide && cachePort->cache->doMasterRequest() ||
 268                     cachePort->isCpuSide && cachePort->cache->doSlaveRequest()) {
 269
 270                     DPRINTF(CachePort, "%s still has outstanding bus reqs\n", cachePort->name());
 271                     this->schedule(curTick + 1);
 272                 }
 273             }
 274             else {
 275                 cachePort->waitingOnRetry = true;
 276                 DPRINTF(CachePort, "%s now waiting on a retry\n", cachePort->name());
 277             }
 278         }
 279         else if (!cachePort->isCpuSide)
 280         {            //MSHR
 281             DPRINTF(CachePort, "%s trying to send a MSHR request\n", cachePort->name());
 282             if (!cachePort->cache->doMasterRequest()) {
 283                 //This can happen if I am the owner of a block and see an upgrade
 284                 //while the block was in my WB Buffers.  I just remove the
 285                 //wb and de-assert the masterRequest
 286                 return;
 287             }
 288
 289             pkt = cachePort->cache->getPacket();
 290             MSHR* mshr = (MSHR*) pkt->senderState;
 291             bool success = cachePort->sendTiming(pkt);
 292             DPRINTF(Cache, "Address %x was %s in sending the timing request\n",
 293                     pkt->getAddr(), success ? "succesful" : "unsuccesful");
 294             cachePort->cache->sendResult(pkt, mshr, success);
 295             cachePort->waitingOnRetry = !success;
 296             if (cachePort->waitingOnRetry)
 297                 DPRINTF(CachePort, "%s now waiting on a retry\n", cachePort->name());
 298             if (success && cachePort->cache->doMasterRequest())
 299             {
 300                 DPRINTF(CachePort, "%s still more MSHR requests to send\n",
 301                         cachePort->name());
 302                 //Still more to issue, rerequest in 1 cycle
 303                 pkt = NULL;
 304                 this->schedule(curTick+1);
 305             }
 306         }
 307         else
 308         {
 309             //CSHR
 310             assert(cachePort->cache->doSlaveRequest());
 311             pkt = cachePort->cache->getCoherencePacket();
 312             MSHR* cshr = (MSHR*) pkt->senderState;
 313             bool success = cachePort->sendTiming(pkt);
 314             cachePort->cache->sendResult(pkt, cshr, success);
 315             cachePort->waitingOnRetry = !success;
 316             if (cachePort->waitingOnRetry)
 317                 DPRINTF(CachePort, "%s now waiting on a retry\n", cachePort->name());
 318             if (success && cachePort->cache->doSlaveRequest())
 319             {
 320                 DPRINTF(CachePort, "%s still more CSHR requests to send\n",
 321                         cachePort->name());
 322                 //Still more to issue, rerequest in 1 cycle
 323                 pkt = NULL;
 324                 this->schedule(curTick+1);
 325             }
 326         }
 327         return;
 328     }
 329     //Response
 330     //Know the packet to send
 331     if (pkt->flags & NACKED_LINE)
 332         pkt->result = Packet::Nacked;
 333     else
 334         pkt->result = Packet::Success;
 335     pkt->makeTimingResponse();
 336     DPRINTF(CachePort, "%s attempting to send a response\n", cachePort->name());
 337     if (!cachePort->drainList.empty() || cachePort->waitingOnRetry) {
 338         //Already have a list, just append
 339         cachePort->drainList.push_back(pkt);
 340         DPRINTF(CachePort, "%s appending response onto drain list\n", cachePort->name());
 341     }
 342     else if (!cachePort->sendTiming(pkt)) {
 343         //It failed, save it to list of drain events
 344         DPRINTF(CachePort, "%s now waiting for a retry\n", cachePort->name());
 345         cachePort->drainList.push_back(pkt);
 346         cachePort->waitingOnRetry = true;
 347     }
 348 }
 349
 350 const char *
 351 BaseCache::CacheEvent::description()
 352 {
 353     return "timing event\n";
 354 }
 355
 356 Port*
 357 BaseCache::getPort(const std::string &if_name, int idx)
 358 {
 359     if (if_name == "")
 360     {
 361         if(cpuSidePort == NULL)
 362             cpuSidePort = new CachePort(name() + "-cpu_side_port", this, true);
 363         return cpuSidePort;
 364     }
 365     else if (if_name == "functional")
 366     {
 367         if(cpuSidePort == NULL)
 368             cpuSidePort = new CachePort(name() + "-cpu_side_port", this, true);
 369         return cpuSidePort;
 370     }
 371     else if (if_name == "cpu_side")
 372     {
 373         if(cpuSidePort == NULL)
 374             cpuSidePort = new CachePort(name() + "-cpu_side_port", this, true);
 375         return cpuSidePort;
 376     }
 377     else if (if_name == "mem_side")
 378     {
 379         if (memSidePort != NULL)
 380             panic("Already have a mem side for this cache\n");
 381         memSidePort = new CachePort(name() + "-mem_side_port", this, false);
 382         return memSidePort;
 383     }
 384     else panic("Port name %s unrecognized\n", if_name);
 385 }
 386
 387 void
 388 BaseCache::init()
 389 {
 390     if (!cpuSidePort || !memSidePort)
 391         panic("Cache not hooked up on both sides\n");
 392     cpuSidePort->sendStatusChange(Port::RangeChange);
 393 }
 394
 395 void
 396 BaseCache::regStats()
 397 {
 398     Request temp_req((Addr) NULL, 4, 0);
 399     Packet::Command temp_cmd = Packet::ReadReq;
 400     Packet temp_pkt(&temp_req, temp_cmd, 0);  //@todo FIx command strings so this isn't neccessary
 401     temp_pkt.allocate(); //Temp allocate, all need data
 402
 403     using namespace Stats;
 404
 405     // Hit statistics
 406     for (int access_idx = 0; access_idx < NUM_MEM_CMDS; ++access_idx) {
 407         Packet::Command cmd = (Packet::Command)access_idx;
 408         const string &cstr = temp_pkt.cmdIdxToString(cmd);
 409
 410         hits[access_idx]
 411             .init(maxThreadsPerCPU)
 412             .name(name() + "." + cstr + "_hits")
 413             .desc("number of " + cstr + " hits")
 414             .flags(total | nozero | nonan)
 415             ;
 416     }
 417
 418     demandHits
 419         .name(name() + ".demand_hits")
 420         .desc("number of demand (read+write) hits")
 421         .flags(total)
 422         ;
 423     demandHits = hits[Packet::ReadReq] + hits[Packet::WriteReq];
 424
 425     overallHits
 426         .name(name() + ".overall_hits")
 427         .desc("number of overall hits")
 428         .flags(total)
 429         ;
 430     overallHits = demandHits + hits[Packet::SoftPFReq] + hits[Packet::HardPFReq]
 431         + hits[Packet::Writeback];
 432
 433     // Miss statistics
 434     for (int access_idx = 0; access_idx < NUM_MEM_CMDS; ++access_idx) {
 435         Packet::Command cmd = (Packet::Command)access_idx;
 436         const string &cstr = temp_pkt.cmdIdxToString(cmd);
 437
 438         misses[access_idx]
 439             .init(maxThreadsPerCPU)
 440             .name(name() + "." + cstr + "_misses")
 441             .desc("number of " + cstr + " misses")
 442             .flags(total | nozero | nonan)
 443             ;
 444     }
 445
 446     demandMisses
 447         .name(name() + ".demand_misses")
 448         .desc("number of demand (read+write) misses")
 449         .flags(total)
 450         ;
 451     demandMisses = misses[Packet::ReadReq] + misses[Packet::WriteReq];
 452
 453     overallMisses
 454         .name(name() + ".overall_misses")
 455         .desc("number of overall misses")
 456         .flags(total)
 457         ;
 458     overallMisses = demandMisses + misses[Packet::SoftPFReq] +
 459         misses[Packet::HardPFReq] + misses[Packet::Writeback];
 460
 461     // Miss latency statistics
 462     for (int access_idx = 0; access_idx < NUM_MEM_CMDS; ++access_idx) {
 463         Packet::Command cmd = (Packet::Command)access_idx;
 464         const string &cstr = temp_pkt.cmdIdxToString(cmd);
 465
 466         missLatency[access_idx]
 467             .init(maxThreadsPerCPU)
 468             .name(name() + "." + cstr + "_miss_latency")
 469             .desc("number of " + cstr + " miss cycles")
 470             .flags(total | nozero | nonan)
 471             ;
 472     }
 473
 474     demandMissLatency
 475         .name(name() + ".demand_miss_latency")
 476         .desc("number of demand (read+write) miss cycles")
 477         .flags(total)
 478         ;
 479     demandMissLatency = missLatency[Packet::ReadReq] + missLatency[Packet::WriteReq];
 480
 481     overallMissLatency
 482         .name(name() + ".overall_miss_latency")
 483         .desc("number of overall miss cycles")
 484         .flags(total)
 485         ;
 486     overallMissLatency = demandMissLatency + missLatency[Packet::SoftPFReq] +
 487         missLatency[Packet::HardPFReq];
 488
 489     // access formulas
 490     for (int access_idx = 0; access_idx < NUM_MEM_CMDS; ++access_idx) {
 491         Packet::Command cmd = (Packet::Command)access_idx;
 492         const string &cstr = temp_pkt.cmdIdxToString(cmd);
 493
 494         accesses[access_idx]
 495             .name(name() + "." + cstr + "_accesses")
 496             .desc("number of " + cstr + " accesses(hits+misses)")
 497             .flags(total | nozero | nonan)
 498             ;
 499
 500         accesses[access_idx] = hits[access_idx] + misses[access_idx];
 501     }
 502
 503     demandAccesses
 504         .name(name() + ".demand_accesses")
 505         .desc("number of demand (read+write) accesses")
 506         .flags(total)
 507         ;
 508     demandAccesses = demandHits + demandMisses;
 509
 510     overallAccesses
 511         .name(name() + ".overall_accesses")
 512         .desc("number of overall (read+write) accesses")
 513         .flags(total)
 514         ;
 515     overallAccesses = overallHits + overallMisses;
 516
 517     // miss rate formulas
 518     for (int access_idx = 0; access_idx < NUM_MEM_CMDS; ++access_idx) {
 519         Packet::Command cmd = (Packet::Command)access_idx;
 520         const string &cstr = temp_pkt.cmdIdxToString(cmd);
 521
 522         missRate[access_idx]
 523             .name(name() + "." + cstr + "_miss_rate")
 524             .desc("miss rate for " + cstr + " accesses")
 525             .flags(total | nozero | nonan)
 526             ;
 527
 528         missRate[access_idx] = misses[access_idx] / accesses[access_idx];
 529     }
 530
 531     demandMissRate
 532         .name(name() + ".demand_miss_rate")
 533         .desc("miss rate for demand accesses")
 534         .flags(total)
 535         ;
 536     demandMissRate = demandMisses / demandAccesses;
 537
 538     overallMissRate
 539         .name(name() + ".overall_miss_rate")
 540         .desc("miss rate for overall accesses")
 541         .flags(total)
 542         ;
 543     overallMissRate = overallMisses / overallAccesses;
 544
 545     // miss latency formulas
 546     for (int access_idx = 0; access_idx < NUM_MEM_CMDS; ++access_idx) {
 547         Packet::Command cmd = (Packet::Command)access_idx;
 548         const string &cstr = temp_pkt.cmdIdxToString(cmd);
 549
 550         avgMissLatency[access_idx]
 551             .name(name() + "." + cstr + "_avg_miss_latency")
 552             .desc("average " + cstr + " miss latency")
 553             .flags(total | nozero | nonan)
 554             ;
 555
 556         avgMissLatency[access_idx] =
 557             missLatency[access_idx] / misses[access_idx];
 558     }
 559
 560     demandAvgMissLatency
 561         .name(name() + ".demand_avg_miss_latency")
 562         .desc("average overall miss latency")
 563         .flags(total)
 564         ;
 565     demandAvgMissLatency = demandMissLatency / demandMisses;
 566
 567     overallAvgMissLatency
 568         .name(name() + ".overall_avg_miss_latency")
 569         .desc("average overall miss latency")
 570         .flags(total)
 571         ;
 572     overallAvgMissLatency = overallMissLatency / overallMisses;
 573
 574     blocked_cycles.init(NUM_BLOCKED_CAUSES);
 575     blocked_cycles
 576         .name(name() + ".blocked_cycles")
 577         .desc("number of cycles access was blocked")
 578         .subname(Blocked_NoMSHRs, "no_mshrs")
 579         .subname(Blocked_NoTargets, "no_targets")
 580         ;
 581
 582
 583     blocked_causes.init(NUM_BLOCKED_CAUSES);
 584     blocked_causes
 585         .name(name() + ".blocked")
 586         .desc("number of cycles access was blocked")
 587         .subname(Blocked_NoMSHRs, "no_mshrs")
 588         .subname(Blocked_NoTargets, "no_targets")
 589         ;
 590
 591     avg_blocked
 592         .name(name() + ".avg_blocked_cycles")
 593         .desc("average number of cycles each access was blocked")
 594         .subname(Blocked_NoMSHRs, "no_mshrs")
 595         .subname(Blocked_NoTargets, "no_targets")
 596         ;
 597
 598     avg_blocked = blocked_cycles / blocked_causes;
 599
 600     fastWrites
 601         .name(name() + ".fast_writes")
 602         .desc("number of fast writes performed")
 603         ;
 604
 605     cacheCopies
 606         .name(name() + ".cache_copies")
 607         .desc("number of cache copies performed")
 608         ;
 609
 610 }