2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Authors: Erik Hallnor
33 * Definition of BaseCache functions.
36 #include "cpu/base.hh"
38 #include "mem/cache/base_cache.hh"
39 #include "mem/cache/miss/mshr.hh"
43 BaseCache::CachePort::CachePort(const std::string
&_name
, BaseCache
*_cache
,
45 : Port(_name
, _cache
), cache(_cache
), isCpuSide(_isCpuSide
)
48 waitingOnRetry
= false;
49 //Start ports at null if more than one is created we should panic
55 BaseCache::CachePort::recvStatusChange(Port::Status status
)
57 cache
->recvStatusChange(status
, isCpuSide
);
61 BaseCache::CachePort::getDeviceAddressRanges(AddrRangeList
&resp
,
64 cache
->getAddressRanges(resp
, snoop
, isCpuSide
);
68 BaseCache::CachePort::deviceBlockSize()
70 return cache
->getBlockSize();
74 BaseCache::CachePort::recvTiming(PacketPtr pkt
)
77 && !pkt
->req
->isUncacheable()
78 && pkt
->isInvalidate()
79 && !pkt
->isRead() && !pkt
->isWrite()) {
80 //Upgrade or Invalidate
81 //Look into what happens if two slave caches on bus
82 DPRINTF(Cache
, "%s %x ?\n", pkt
->cmdString(), pkt
->getAddr());
84 assert(!(pkt
->flags
& SATISFIED
));
85 pkt
->flags
|= SATISFIED
;
86 //Invalidates/Upgrades need no response if they get the bus
90 if (pkt
->isRequest() && blocked
)
92 DPRINTF(Cache
,"Scheduling a retry while blocked\n");
96 return cache
->doTimingAccess(pkt
, this, isCpuSide
);
100 BaseCache::CachePort::recvAtomic(PacketPtr pkt
)
102 return cache
->doAtomicAccess(pkt
, isCpuSide
);
106 BaseCache::CachePort::recvFunctional(PacketPtr pkt
)
108 //Check storage here first
109 list
<PacketPtr
>::iterator i
= drainList
.begin();
110 list
<PacketPtr
>::iterator end
= drainList
.end();
111 for (; i
!= end
; ++i
) {
112 PacketPtr target
= *i
;
113 // If the target contains data, and it overlaps the
114 // probed request, need to update data
115 if (target
->intersect(pkt
)) {
116 fixPacket(pkt
, target
);
119 cache
->doFunctionalAccess(pkt
, isCpuSide
);
123 BaseCache::CachePort::recvRetry()
126 assert(waitingOnRetry
);
127 if (!drainList
.empty()) {
128 DPRINTF(CachePort
, "%s attempting to send a retry for response\n", name());
129 //We have some responses to drain first
130 if (sendTiming(drainList
.front())) {
131 DPRINTF(CachePort
, "%s sucessful in sending a retry for response\n", name());
132 drainList
.pop_front();
133 if (!drainList
.empty() ||
134 !isCpuSide
&& cache
->doMasterRequest() ||
135 isCpuSide
&& cache
->doSlaveRequest()) {
137 DPRINTF(CachePort
, "%s has more responses/requests\n", name());
138 BaseCache::CacheEvent
* reqCpu
= new BaseCache::CacheEvent(this);
139 reqCpu
->schedule(curTick
+ 1);
141 waitingOnRetry
= false;
146 DPRINTF(CachePort
, "%s attempting to send a retry for MSHR\n", name());
147 if (!cache
->doMasterRequest()) {
148 //This can happen if I am the owner of a block and see an upgrade
149 //while the block was in my WB Buffers. I just remove the
150 //wb and de-assert the masterRequest
151 waitingOnRetry
= false;
154 pkt
= cache
->getPacket();
155 MSHR
* mshr
= (MSHR
*) pkt
->senderState
;
156 //Copy the packet, it may be modified/destroyed elsewhere
157 PacketPtr copyPkt
= new Packet(*pkt
);
158 copyPkt
->dataStatic
<uint8_t>(pkt
->getPtr
<uint8_t>());
161 bool success
= sendTiming(pkt
);
162 DPRINTF(Cache
, "Address %x was %s in sending the timing request\n",
163 pkt
->getAddr(), success
? "succesful" : "unsuccesful");
165 waitingOnRetry
= !success
;
166 if (waitingOnRetry
) {
167 DPRINTF(CachePort
, "%s now waiting on a retry\n", name());
170 cache
->sendResult(pkt
, mshr
, success
);
172 if (success
&& cache
->doMasterRequest())
174 DPRINTF(CachePort
, "%s has more requests\n", name());
175 //Still more to issue, rerequest in 1 cycle
176 BaseCache::CacheEvent
* reqCpu
= new BaseCache::CacheEvent(this);
177 reqCpu
->schedule(curTick
+ 1);
182 assert(cache
->doSlaveRequest());
183 //pkt = cache->getCoherencePacket();
184 //We save the packet, no reordering on CSHRS
185 pkt
= cache
->getCoherencePacket();
186 MSHR
* cshr
= (MSHR
*)pkt
->senderState
;
187 bool success
= sendTiming(pkt
);
188 cache
->sendCoherenceResult(pkt
, cshr
, success
);
189 waitingOnRetry
= !success
;
190 if (success
&& cache
->doSlaveRequest())
192 DPRINTF(CachePort
, "%s has more requests\n", name());
193 //Still more to issue, rerequest in 1 cycle
194 BaseCache::CacheEvent
* reqCpu
= new BaseCache::CacheEvent(this);
195 reqCpu
->schedule(curTick
+ 1);
198 if (waitingOnRetry
) DPRINTF(CachePort
, "%s STILL Waiting on retry\n", name());
199 else DPRINTF(CachePort
, "%s no longer waiting on retry\n", name());
203 BaseCache::CachePort::setBlocked()
206 DPRINTF(Cache
, "Cache Blocking\n");
208 //Clear the retry flag
209 mustSendRetry
= false;
213 BaseCache::CachePort::clearBlocked()
216 DPRINTF(Cache
, "Cache Unblocking\n");
220 DPRINTF(Cache
, "Cache Sending Retry\n");
221 mustSendRetry
= false;
226 BaseCache::CacheEvent::CacheEvent(CachePort
*_cachePort
)
227 : Event(&mainEventQueue
, CPU_Tick_Pri
), cachePort(_cachePort
)
229 this->setFlags(AutoDelete
);
233 BaseCache::CacheEvent::CacheEvent(CachePort
*_cachePort
, PacketPtr _pkt
)
234 : Event(&mainEventQueue
, CPU_Tick_Pri
), cachePort(_cachePort
), pkt(_pkt
)
236 this->setFlags(AutoDelete
);
240 BaseCache::CacheEvent::process()
244 if (cachePort
->waitingOnRetry
) return;
245 //We have some responses to drain first
246 if (!cachePort
->drainList
.empty()) {
247 DPRINTF(CachePort
, "%s trying to drain a response\n", cachePort
->name());
248 if (cachePort
->sendTiming(cachePort
->drainList
.front())) {
249 DPRINTF(CachePort
, "%s drains a response succesfully\n", cachePort
->name());
250 cachePort
->drainList
.pop_front();
251 if (!cachePort
->drainList
.empty() ||
252 !cachePort
->isCpuSide
&& cachePort
->cache
->doMasterRequest() ||
253 cachePort
->isCpuSide
&& cachePort
->cache
->doSlaveRequest()) {
255 DPRINTF(CachePort
, "%s still has outstanding bus reqs\n", cachePort
->name());
256 this->schedule(curTick
+ 1);
260 cachePort
->waitingOnRetry
= true;
261 DPRINTF(CachePort
, "%s now waiting on a retry\n", cachePort
->name());
264 else if (!cachePort
->isCpuSide
)
266 DPRINTF(CachePort
, "%s trying to send a MSHR request\n", cachePort
->name());
267 if (!cachePort
->cache
->doMasterRequest()) {
268 //This can happen if I am the owner of a block and see an upgrade
269 //while the block was in my WB Buffers. I just remove the
270 //wb and de-assert the masterRequest
274 pkt
= cachePort
->cache
->getPacket();
275 MSHR
* mshr
= (MSHR
*) pkt
->senderState
;
276 //Copy the packet, it may be modified/destroyed elsewhere
277 PacketPtr copyPkt
= new Packet(*pkt
);
278 copyPkt
->dataStatic
<uint8_t>(pkt
->getPtr
<uint8_t>());
281 bool success
= cachePort
->sendTiming(pkt
);
282 DPRINTF(Cache
, "Address %x was %s in sending the timing request\n",
283 pkt
->getAddr(), success
? "succesful" : "unsuccesful");
285 cachePort
->waitingOnRetry
= !success
;
286 if (cachePort
->waitingOnRetry
) {
287 DPRINTF(CachePort
, "%s now waiting on a retry\n", cachePort
->name());
290 cachePort
->cache
->sendResult(pkt
, mshr
, success
);
291 if (success
&& cachePort
->cache
->doMasterRequest())
293 DPRINTF(CachePort
, "%s still more MSHR requests to send\n",
295 //Still more to issue, rerequest in 1 cycle
297 this->schedule(curTick
+1);
303 assert(cachePort
->cache
->doSlaveRequest());
304 pkt
= cachePort
->cache
->getCoherencePacket();
305 MSHR
* cshr
= (MSHR
*) pkt
->senderState
;
306 bool success
= cachePort
->sendTiming(pkt
);
307 cachePort
->cache
->sendCoherenceResult(pkt
, cshr
, success
);
308 cachePort
->waitingOnRetry
= !success
;
309 if (cachePort
->waitingOnRetry
)
310 DPRINTF(CachePort
, "%s now waiting on a retry\n", cachePort
->name());
311 if (success
&& cachePort
->cache
->doSlaveRequest())
313 DPRINTF(CachePort
, "%s still more CSHR requests to send\n",
315 //Still more to issue, rerequest in 1 cycle
317 this->schedule(curTick
+1);
323 //Know the packet to send
324 if (pkt
->flags
& NACKED_LINE
)
325 pkt
->result
= Packet::Nacked
;
327 pkt
->result
= Packet::Success
;
328 pkt
->makeTimingResponse();
329 DPRINTF(CachePort
, "%s attempting to send a response\n", cachePort
->name());
330 if (!cachePort
->drainList
.empty() || cachePort
->waitingOnRetry
) {
331 //Already have a list, just append
332 cachePort
->drainList
.push_back(pkt
);
333 DPRINTF(CachePort
, "%s appending response onto drain list\n", cachePort
->name());
335 else if (!cachePort
->sendTiming(pkt
)) {
336 //It failed, save it to list of drain events
337 DPRINTF(CachePort
, "%s now waiting for a retry\n", cachePort
->name());
338 cachePort
->drainList
.push_back(pkt
);
339 cachePort
->waitingOnRetry
= true;
344 BaseCache::CacheEvent::description()
346 return "timing event\n";
350 BaseCache::getPort(const std::string
&if_name
, int idx
)
354 if(cpuSidePort
== NULL
)
355 cpuSidePort
= new CachePort(name() + "-cpu_side_port", this, true);
358 else if (if_name
== "functional")
360 if(cpuSidePort
== NULL
)
361 cpuSidePort
= new CachePort(name() + "-cpu_side_port", this, true);
364 else if (if_name
== "cpu_side")
366 if(cpuSidePort
== NULL
)
367 cpuSidePort
= new CachePort(name() + "-cpu_side_port", this, true);
370 else if (if_name
== "mem_side")
372 if (memSidePort
!= NULL
)
373 panic("Already have a mem side for this cache\n");
374 memSidePort
= new CachePort(name() + "-mem_side_port", this, false);
377 else panic("Port name %s unrecognized\n", if_name
);
383 if (!cpuSidePort
|| !memSidePort
)
384 panic("Cache not hooked up on both sides\n");
385 cpuSidePort
->sendStatusChange(Port::RangeChange
);
389 BaseCache::regStats()
391 Request
temp_req((Addr
) NULL
, 4, 0);
392 Packet::Command temp_cmd
= Packet::ReadReq
;
393 Packet
temp_pkt(&temp_req
, temp_cmd
, 0); //@todo FIx command strings so this isn't neccessary
394 temp_pkt
.allocate(); //Temp allocate, all need data
396 using namespace Stats
;
399 for (int access_idx
= 0; access_idx
< NUM_MEM_CMDS
; ++access_idx
) {
400 Packet::Command cmd
= (Packet::Command
)access_idx
;
401 const string
&cstr
= temp_pkt
.cmdIdxToString(cmd
);
404 .init(maxThreadsPerCPU
)
405 .name(name() + "." + cstr
+ "_hits")
406 .desc("number of " + cstr
+ " hits")
407 .flags(total
| nozero
| nonan
)
412 .name(name() + ".demand_hits")
413 .desc("number of demand (read+write) hits")
416 demandHits
= hits
[Packet::ReadReq
] + hits
[Packet::WriteReq
];
419 .name(name() + ".overall_hits")
420 .desc("number of overall hits")
423 overallHits
= demandHits
+ hits
[Packet::SoftPFReq
] + hits
[Packet::HardPFReq
]
424 + hits
[Packet::Writeback
];
427 for (int access_idx
= 0; access_idx
< NUM_MEM_CMDS
; ++access_idx
) {
428 Packet::Command cmd
= (Packet::Command
)access_idx
;
429 const string
&cstr
= temp_pkt
.cmdIdxToString(cmd
);
432 .init(maxThreadsPerCPU
)
433 .name(name() + "." + cstr
+ "_misses")
434 .desc("number of " + cstr
+ " misses")
435 .flags(total
| nozero
| nonan
)
440 .name(name() + ".demand_misses")
441 .desc("number of demand (read+write) misses")
444 demandMisses
= misses
[Packet::ReadReq
] + misses
[Packet::WriteReq
];
447 .name(name() + ".overall_misses")
448 .desc("number of overall misses")
451 overallMisses
= demandMisses
+ misses
[Packet::SoftPFReq
] +
452 misses
[Packet::HardPFReq
] + misses
[Packet::Writeback
];
454 // Miss latency statistics
455 for (int access_idx
= 0; access_idx
< NUM_MEM_CMDS
; ++access_idx
) {
456 Packet::Command cmd
= (Packet::Command
)access_idx
;
457 const string
&cstr
= temp_pkt
.cmdIdxToString(cmd
);
459 missLatency
[access_idx
]
460 .init(maxThreadsPerCPU
)
461 .name(name() + "." + cstr
+ "_miss_latency")
462 .desc("number of " + cstr
+ " miss cycles")
463 .flags(total
| nozero
| nonan
)
468 .name(name() + ".demand_miss_latency")
469 .desc("number of demand (read+write) miss cycles")
472 demandMissLatency
= missLatency
[Packet::ReadReq
] + missLatency
[Packet::WriteReq
];
475 .name(name() + ".overall_miss_latency")
476 .desc("number of overall miss cycles")
479 overallMissLatency
= demandMissLatency
+ missLatency
[Packet::SoftPFReq
] +
480 missLatency
[Packet::HardPFReq
];
483 for (int access_idx
= 0; access_idx
< NUM_MEM_CMDS
; ++access_idx
) {
484 Packet::Command cmd
= (Packet::Command
)access_idx
;
485 const string
&cstr
= temp_pkt
.cmdIdxToString(cmd
);
488 .name(name() + "." + cstr
+ "_accesses")
489 .desc("number of " + cstr
+ " accesses(hits+misses)")
490 .flags(total
| nozero
| nonan
)
493 accesses
[access_idx
] = hits
[access_idx
] + misses
[access_idx
];
497 .name(name() + ".demand_accesses")
498 .desc("number of demand (read+write) accesses")
501 demandAccesses
= demandHits
+ demandMisses
;
504 .name(name() + ".overall_accesses")
505 .desc("number of overall (read+write) accesses")
508 overallAccesses
= overallHits
+ overallMisses
;
510 // miss rate formulas
511 for (int access_idx
= 0; access_idx
< NUM_MEM_CMDS
; ++access_idx
) {
512 Packet::Command cmd
= (Packet::Command
)access_idx
;
513 const string
&cstr
= temp_pkt
.cmdIdxToString(cmd
);
516 .name(name() + "." + cstr
+ "_miss_rate")
517 .desc("miss rate for " + cstr
+ " accesses")
518 .flags(total
| nozero
| nonan
)
521 missRate
[access_idx
] = misses
[access_idx
] / accesses
[access_idx
];
525 .name(name() + ".demand_miss_rate")
526 .desc("miss rate for demand accesses")
529 demandMissRate
= demandMisses
/ demandAccesses
;
532 .name(name() + ".overall_miss_rate")
533 .desc("miss rate for overall accesses")
536 overallMissRate
= overallMisses
/ overallAccesses
;
538 // miss latency formulas
539 for (int access_idx
= 0; access_idx
< NUM_MEM_CMDS
; ++access_idx
) {
540 Packet::Command cmd
= (Packet::Command
)access_idx
;
541 const string
&cstr
= temp_pkt
.cmdIdxToString(cmd
);
543 avgMissLatency
[access_idx
]
544 .name(name() + "." + cstr
+ "_avg_miss_latency")
545 .desc("average " + cstr
+ " miss latency")
546 .flags(total
| nozero
| nonan
)
549 avgMissLatency
[access_idx
] =
550 missLatency
[access_idx
] / misses
[access_idx
];
554 .name(name() + ".demand_avg_miss_latency")
555 .desc("average overall miss latency")
558 demandAvgMissLatency
= demandMissLatency
/ demandMisses
;
560 overallAvgMissLatency
561 .name(name() + ".overall_avg_miss_latency")
562 .desc("average overall miss latency")
565 overallAvgMissLatency
= overallMissLatency
/ overallMisses
;
567 blocked_cycles
.init(NUM_BLOCKED_CAUSES
);
569 .name(name() + ".blocked_cycles")
570 .desc("number of cycles access was blocked")
571 .subname(Blocked_NoMSHRs
, "no_mshrs")
572 .subname(Blocked_NoTargets
, "no_targets")
576 blocked_causes
.init(NUM_BLOCKED_CAUSES
);
578 .name(name() + ".blocked")
579 .desc("number of cycles access was blocked")
580 .subname(Blocked_NoMSHRs
, "no_mshrs")
581 .subname(Blocked_NoTargets
, "no_targets")
585 .name(name() + ".avg_blocked_cycles")
586 .desc("average number of cycles each access was blocked")
587 .subname(Blocked_NoMSHRs
, "no_mshrs")
588 .subname(Blocked_NoTargets
, "no_targets")
591 avg_blocked
= blocked_cycles
/ blocked_causes
;
594 .name(name() + ".fast_writes")
595 .desc("number of fast writes performed")
599 .name(name() + ".cache_copies")
600 .desc("number of cache copies performed")