src/mem/cache/base_cache.cc

   1 /*
   2  * Copyright (c) 2003-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Erik Hallnor
  29  */
  30
  31 /**
  32  * @file
  33  * Definition of BaseCache functions.
  34  */
  35
  36 #include "cpu/base.hh"
  37 #include "cpu/smt.hh"
  38 #include "mem/cache/base_cache.hh"
  39 #include "mem/cache/miss/mshr.hh"
  40
  41 using namespace std;
  42
  43 BaseCache::CachePort::CachePort(const std::string &_name, BaseCache *_cache,
  44                                 bool _isCpuSide)
  45     : Port(_name, _cache), cache(_cache), isCpuSide(_isCpuSide)
  46 {
  47     blocked = false;
  48     waitingOnRetry = false;
  49     //Start ports at null if more than one is created we should panic
  50     //cpuSidePort = NULL;
  51     //memSidePort = NULL;
  52 }
  53
  54 void
  55 BaseCache::CachePort::recvStatusChange(Port::Status status)
  56 {
  57     cache->recvStatusChange(status, isCpuSide);
  58 }
  59
  60 void
  61 BaseCache::CachePort::getDeviceAddressRanges(AddrRangeList &resp,
  62                                        AddrRangeList &snoop)
  63 {
  64     cache->getAddressRanges(resp, snoop, isCpuSide);
  65 }
  66
  67 int
  68 BaseCache::CachePort::deviceBlockSize()
  69 {
  70     return cache->getBlockSize();
  71 }
  72
  73 bool
  74 BaseCache::CachePort::recvTiming(PacketPtr pkt)
  75 {
  76     if (isCpuSide
  77         && !pkt->req->isUncacheable()
  78         && pkt->isInvalidate()
  79         && !pkt->isRead() && !pkt->isWrite()) {
  80         //Upgrade or Invalidate
  81         //Look into what happens if two slave caches on bus
  82         DPRINTF(Cache, "%s %x ?\n", pkt->cmdString(), pkt->getAddr());
  83
  84         assert(!(pkt->flags & SATISFIED));
  85         pkt->flags |= SATISFIED;
  86         //Invalidates/Upgrades need no response if they get the bus
  87         return true;
  88     }
  89
  90     if (pkt->isRequest() && blocked)
  91     {
  92         DPRINTF(Cache,"Scheduling a retry while blocked\n");
  93         mustSendRetry = true;
  94         return false;
  95     }
  96     return cache->doTimingAccess(pkt, this, isCpuSide);
  97 }
  98
  99 Tick
 100 BaseCache::CachePort::recvAtomic(PacketPtr pkt)
 101 {
 102     return cache->doAtomicAccess(pkt, isCpuSide);
 103 }
 104
 105 bool
 106 BaseCache::CachePort::checkFunctional(PacketPtr pkt)
 107 {
 108     //Check storage here first
 109     list<PacketPtr>::iterator i = drainList.begin();
 110     list<PacketPtr>::iterator iend = drainList.end();
 111     bool notDone = true;
 112     while (i != iend && notDone) {
 113         PacketPtr target = *i;
 114         // If the target contains data, and it overlaps the
 115         // probed request, need to update data
 116         if (target->intersect(pkt)) {
 117             DPRINTF(Cache, "Functional %s access to blk_addr %x intersects a drain\n",
 118                     pkt->cmdString(), pkt->getAddr() & ~(cache->getBlockSize() - 1));
 119             notDone = fixPacket(pkt, target);
 120         }
 121         i++;
 122     }
 123     //Also check the response not yet ready to be on the list
 124     std::list<std::pair<Tick,PacketPtr> >::iterator j = transmitList.begin();
 125     std::list<std::pair<Tick,PacketPtr> >::iterator jend = transmitList.end();
 126
 127     while (j != jend && notDone) {
 128         PacketPtr target = j->second;
 129         // If the target contains data, and it overlaps the
 130         // probed request, need to update data
 131         if (target->intersect(pkt)) {
 132             DPRINTF(Cache, "Functional %s access to blk_addr %x intersects a response\n",
 133                     pkt->cmdString(), pkt->getAddr() & ~(cache->getBlockSize() - 1));
 134             notDone = fixDelayedResponsePacket(pkt, target);
 135         }
 136         j++;
 137     }
 138     return notDone;
 139 }
 140
 141 void
 142 BaseCache::CachePort::recvFunctional(PacketPtr pkt)
 143 {
 144     bool notDone = checkFunctional(pkt);
 145     if (notDone)
 146         cache->doFunctionalAccess(pkt, isCpuSide);
 147 }
 148
 149 void
 150 BaseCache::CachePort::checkAndSendFunctional(PacketPtr pkt)
 151 {
 152     bool notDone = checkFunctional(pkt);
 153     if (notDone)
 154         sendFunctional(pkt);
 155 }
 156
 157 void
 158 BaseCache::CachePort::recvRetry()
 159 {
 160     PacketPtr pkt;
 161     assert(waitingOnRetry);
 162     if (!drainList.empty()) {
 163         DPRINTF(CachePort, "%s attempting to send a retry for response\n", name());
 164         //We have some responses to drain first
 165         if (sendTiming(drainList.front())) {
 166             DPRINTF(CachePort, "%s sucessful in sending a retry for response\n", name());
 167             drainList.pop_front();
 168             if (!drainList.empty() ||
 169                 !isCpuSide && cache->doMasterRequest() ||
 170                 isCpuSide && cache->doSlaveRequest()) {
 171
 172                 DPRINTF(CachePort, "%s has more responses/requests\n", name());
 173                 BaseCache::CacheEvent * reqCpu = new BaseCache::CacheEvent(this, false);
 174                 reqCpu->schedule(curTick + 1);
 175             }
 176             waitingOnRetry = false;
 177         }
 178         // Check if we're done draining once this list is empty
 179         if (drainList.empty())
 180             cache->checkDrain();
 181     }
 182     else if (!isCpuSide)
 183     {
 184         DPRINTF(CachePort, "%s attempting to send a retry for MSHR\n", name());
 185         if (!cache->doMasterRequest()) {
 186             //This can happen if I am the owner of a block and see an upgrade
 187             //while the block was in my WB Buffers.  I just remove the
 188             //wb and de-assert the masterRequest
 189             waitingOnRetry = false;
 190             return;
 191         }
 192         pkt = cache->getPacket();
 193         MSHR* mshr = (MSHR*) pkt->senderState;
 194         //Copy the packet, it may be modified/destroyed elsewhere
 195         PacketPtr copyPkt = new Packet(*pkt);
 196         copyPkt->dataStatic<uint8_t>(pkt->getPtr<uint8_t>());
 197         mshr->pkt = copyPkt;
 198
 199         bool success = sendTiming(pkt);
 200         DPRINTF(Cache, "Address %x was %s in sending the timing request\n",
 201                 pkt->getAddr(), success ? "succesful" : "unsuccesful");
 202
 203         waitingOnRetry = !success;
 204         if (waitingOnRetry) {
 205             DPRINTF(CachePort, "%s now waiting on a retry\n", name());
 206         }
 207
 208         cache->sendResult(pkt, mshr, success);
 209
 210         if (success && cache->doMasterRequest())
 211         {
 212             DPRINTF(CachePort, "%s has more requests\n", name());
 213             //Still more to issue, rerequest in 1 cycle
 214             BaseCache::CacheEvent * reqCpu = new BaseCache::CacheEvent(this, false);
 215             reqCpu->schedule(curTick + 1);
 216         }
 217     }
 218     else
 219     {
 220         assert(cache->doSlaveRequest());
 221         //pkt = cache->getCoherencePacket();
 222         //We save the packet, no reordering on CSHRS
 223         pkt = cache->getCoherencePacket();
 224         MSHR* cshr = (MSHR*)pkt->senderState;
 225         bool success = sendTiming(pkt);
 226         cache->sendCoherenceResult(pkt, cshr, success);
 227         waitingOnRetry = !success;
 228         if (success && cache->doSlaveRequest())
 229         {
 230             DPRINTF(CachePort, "%s has more requests\n", name());
 231             //Still more to issue, rerequest in 1 cycle
 232             BaseCache::CacheEvent * reqCpu = new BaseCache::CacheEvent(this, false);
 233             reqCpu->schedule(curTick + 1);
 234         }
 235     }
 236     if (waitingOnRetry) DPRINTF(CachePort, "%s STILL Waiting on retry\n", name());
 237     else DPRINTF(CachePort, "%s no longer waiting on retry\n", name());
 238     return;
 239 }
 240 void
 241 BaseCache::CachePort::setBlocked()
 242 {
 243     assert(!blocked);
 244     DPRINTF(Cache, "Cache Blocking\n");
 245     blocked = true;
 246     //Clear the retry flag
 247     mustSendRetry = false;
 248 }
 249
 250 void
 251 BaseCache::CachePort::clearBlocked()
 252 {
 253     assert(blocked);
 254     DPRINTF(Cache, "Cache Unblocking\n");
 255     blocked = false;
 256     if (mustSendRetry)
 257     {
 258         DPRINTF(Cache, "Cache Sending Retry\n");
 259         mustSendRetry = false;
 260         sendRetry();
 261     }
 262 }
 263
 264 BaseCache::CacheEvent::CacheEvent(CachePort *_cachePort, bool _newResponse)
 265     : Event(&mainEventQueue, CPU_Tick_Pri), cachePort(_cachePort),
 266       newResponse(_newResponse)
 267 {
 268     if (!newResponse)
 269         this->setFlags(AutoDelete);
 270     pkt = NULL;
 271 }
 272
 273 void
 274 BaseCache::CacheEvent::process()
 275 {
 276     if (!newResponse)
 277     {
 278         if (cachePort->waitingOnRetry) return;
 279        //We have some responses to drain first
 280         if (!cachePort->drainList.empty()) {
 281             DPRINTF(CachePort, "%s trying to drain a response\n", cachePort->name());
 282             if (cachePort->sendTiming(cachePort->drainList.front())) {
 283                 DPRINTF(CachePort, "%s drains a response succesfully\n", cachePort->name());
 284                 cachePort->drainList.pop_front();
 285                 if (!cachePort->drainList.empty() ||
 286                     !cachePort->isCpuSide && cachePort->cache->doMasterRequest() ||
 287                     cachePort->isCpuSide && cachePort->cache->doSlaveRequest()) {
 288
 289                     DPRINTF(CachePort, "%s still has outstanding bus reqs\n", cachePort->name());
 290                     this->schedule(curTick + 1);
 291                 }
 292             }
 293             else {
 294                 cachePort->waitingOnRetry = true;
 295                 DPRINTF(CachePort, "%s now waiting on a retry\n", cachePort->name());
 296             }
 297         }
 298         else if (!cachePort->isCpuSide)
 299         {            //MSHR
 300             DPRINTF(CachePort, "%s trying to send a MSHR request\n", cachePort->name());
 301             if (!cachePort->cache->doMasterRequest()) {
 302                 //This can happen if I am the owner of a block and see an upgrade
 303                 //while the block was in my WB Buffers.  I just remove the
 304                 //wb and de-assert the masterRequest
 305                 return;
 306             }
 307
 308             pkt = cachePort->cache->getPacket();
 309             MSHR* mshr = (MSHR*) pkt->senderState;
 310             //Copy the packet, it may be modified/destroyed elsewhere
 311             PacketPtr copyPkt = new Packet(*pkt);
 312             copyPkt->dataStatic<uint8_t>(pkt->getPtr<uint8_t>());
 313             mshr->pkt = copyPkt;
 314
 315             bool success = cachePort->sendTiming(pkt);
 316             DPRINTF(Cache, "Address %x was %s in sending the timing request\n",
 317                     pkt->getAddr(), success ? "succesful" : "unsuccesful");
 318
 319             cachePort->waitingOnRetry = !success;
 320             if (cachePort->waitingOnRetry) {
 321                 DPRINTF(CachePort, "%s now waiting on a retry\n", cachePort->name());
 322             }
 323
 324             cachePort->cache->sendResult(pkt, mshr, success);
 325             if (success && cachePort->cache->doMasterRequest())
 326             {
 327                 DPRINTF(CachePort, "%s still more MSHR requests to send\n",
 328                         cachePort->name());
 329                 //Still more to issue, rerequest in 1 cycle
 330                 pkt = NULL;
 331                 this->schedule(curTick+1);
 332             }
 333         }
 334         else
 335         {
 336             //CSHR
 337             assert(cachePort->cache->doSlaveRequest());
 338             pkt = cachePort->cache->getCoherencePacket();
 339             MSHR* cshr = (MSHR*) pkt->senderState;
 340             bool success = cachePort->sendTiming(pkt);
 341             cachePort->cache->sendCoherenceResult(pkt, cshr, success);
 342             cachePort->waitingOnRetry = !success;
 343             if (cachePort->waitingOnRetry)
 344                 DPRINTF(CachePort, "%s now waiting on a retry\n", cachePort->name());
 345             if (success && cachePort->cache->doSlaveRequest())
 346             {
 347                 DPRINTF(CachePort, "%s still more CSHR requests to send\n",
 348                         cachePort->name());
 349                 //Still more to issue, rerequest in 1 cycle
 350                 pkt = NULL;
 351                 this->schedule(curTick+1);
 352             }
 353         }
 354         return;
 355     }
 356     //Else it's a response
 357     assert(cachePort->transmitList.size());
 358     assert(cachePort->transmitList.front().first <= curTick);
 359     pkt = cachePort->transmitList.front().second;
 360     cachePort->transmitList.pop_front();
 361     if (!cachePort->transmitList.empty()) {
 362         Tick time = cachePort->transmitList.front().first;
 363         schedule(time <= curTick ? curTick+1 : time);
 364     }
 365
 366     if (pkt->flags & NACKED_LINE)
 367         pkt->result = Packet::Nacked;
 368     else
 369         pkt->result = Packet::Success;
 370     pkt->makeTimingResponse();
 371     DPRINTF(CachePort, "%s attempting to send a response\n", cachePort->name());
 372     if (!cachePort->drainList.empty() || cachePort->waitingOnRetry) {
 373         //Already have a list, just append
 374         cachePort->drainList.push_back(pkt);
 375         DPRINTF(CachePort, "%s appending response onto drain list\n", cachePort->name());
 376     }
 377     else if (!cachePort->sendTiming(pkt)) {
 378         //It failed, save it to list of drain events
 379         DPRINTF(CachePort, "%s now waiting for a retry\n", cachePort->name());
 380         cachePort->drainList.push_back(pkt);
 381         cachePort->waitingOnRetry = true;
 382     }
 383
 384     // Check if we're done draining once this list is empty
 385     if (cachePort->drainList.empty() && cachePort->transmitList.empty())
 386         cachePort->cache->checkDrain();
 387 }
 388
 389 const char *
 390 BaseCache::CacheEvent::description()
 391 {
 392     return "timing event\n";
 393 }
 394
 395 Port*
 396 BaseCache::getPort(const std::string &if_name, int idx)
 397 {
 398     if (if_name == "")
 399     {
 400         if(cpuSidePort == NULL) {
 401             cpuSidePort = new CachePort(name() + "-cpu_side_port", this, true);
 402             sendEvent = new CacheEvent(cpuSidePort, true);
 403         }
 404         return cpuSidePort;
 405     }
 406     else if (if_name == "functional")
 407     {
 408         return new CachePort(name() + "-cpu_side_port", this, true);
 409     }
 410     else if (if_name == "cpu_side")
 411     {
 412         if(cpuSidePort == NULL) {
 413             cpuSidePort = new CachePort(name() + "-cpu_side_port", this, true);
 414             sendEvent = new CacheEvent(cpuSidePort, true);
 415         }
 416         return cpuSidePort;
 417     }
 418     else if (if_name == "mem_side")
 419     {
 420         if (memSidePort != NULL)
 421             panic("Already have a mem side for this cache\n");
 422         memSidePort = new CachePort(name() + "-mem_side_port", this, false);
 423         memSendEvent = new CacheEvent(memSidePort, true);
 424         return memSidePort;
 425     }
 426     else panic("Port name %s unrecognized\n", if_name);
 427 }
 428
 429 void
 430 BaseCache::init()
 431 {
 432     if (!cpuSidePort || !memSidePort)
 433         panic("Cache not hooked up on both sides\n");
 434     cpuSidePort->sendStatusChange(Port::RangeChange);
 435 }
 436
 437 void
 438 BaseCache::regStats()
 439 {
 440     Request temp_req((Addr) NULL, 4, 0);
 441     Packet::Command temp_cmd = Packet::ReadReq;
 442     Packet temp_pkt(&temp_req, temp_cmd, 0);  //@todo FIx command strings so this isn't neccessary
 443     temp_pkt.allocate(); //Temp allocate, all need data
 444
 445     using namespace Stats;
 446
 447     // Hit statistics
 448     for (int access_idx = 0; access_idx < NUM_MEM_CMDS; ++access_idx) {
 449         Packet::Command cmd = (Packet::Command)access_idx;
 450         const string &cstr = temp_pkt.cmdIdxToString(cmd);
 451
 452         hits[access_idx]
 453             .init(maxThreadsPerCPU)
 454             .name(name() + "." + cstr + "_hits")
 455             .desc("number of " + cstr + " hits")
 456             .flags(total | nozero | nonan)
 457             ;
 458     }
 459
 460     demandHits
 461         .name(name() + ".demand_hits")
 462         .desc("number of demand (read+write) hits")
 463         .flags(total)
 464         ;
 465     demandHits = hits[Packet::ReadReq] + hits[Packet::WriteReq];
 466
 467     overallHits
 468         .name(name() + ".overall_hits")
 469         .desc("number of overall hits")
 470         .flags(total)
 471         ;
 472     overallHits = demandHits + hits[Packet::SoftPFReq] + hits[Packet::HardPFReq]
 473         + hits[Packet::Writeback];
 474
 475     // Miss statistics
 476     for (int access_idx = 0; access_idx < NUM_MEM_CMDS; ++access_idx) {
 477         Packet::Command cmd = (Packet::Command)access_idx;
 478         const string &cstr = temp_pkt.cmdIdxToString(cmd);
 479
 480         misses[access_idx]
 481             .init(maxThreadsPerCPU)
 482             .name(name() + "." + cstr + "_misses")
 483             .desc("number of " + cstr + " misses")
 484             .flags(total | nozero | nonan)
 485             ;
 486     }
 487
 488     demandMisses
 489         .name(name() + ".demand_misses")
 490         .desc("number of demand (read+write) misses")
 491         .flags(total)
 492         ;
 493     demandMisses = misses[Packet::ReadReq] + misses[Packet::WriteReq];
 494
 495     overallMisses
 496         .name(name() + ".overall_misses")
 497         .desc("number of overall misses")
 498         .flags(total)
 499         ;
 500     overallMisses = demandMisses + misses[Packet::SoftPFReq] +
 501         misses[Packet::HardPFReq] + misses[Packet::Writeback];
 502
 503     // Miss latency statistics
 504     for (int access_idx = 0; access_idx < NUM_MEM_CMDS; ++access_idx) {
 505         Packet::Command cmd = (Packet::Command)access_idx;
 506         const string &cstr = temp_pkt.cmdIdxToString(cmd);
 507
 508         missLatency[access_idx]
 509             .init(maxThreadsPerCPU)
 510             .name(name() + "." + cstr + "_miss_latency")
 511             .desc("number of " + cstr + " miss cycles")
 512             .flags(total | nozero | nonan)
 513             ;
 514     }
 515
 516     demandMissLatency
 517         .name(name() + ".demand_miss_latency")
 518         .desc("number of demand (read+write) miss cycles")
 519         .flags(total)
 520         ;
 521     demandMissLatency = missLatency[Packet::ReadReq] + missLatency[Packet::WriteReq];
 522
 523     overallMissLatency
 524         .name(name() + ".overall_miss_latency")
 525         .desc("number of overall miss cycles")
 526         .flags(total)
 527         ;
 528     overallMissLatency = demandMissLatency + missLatency[Packet::SoftPFReq] +
 529         missLatency[Packet::HardPFReq];
 530
 531     // access formulas
 532     for (int access_idx = 0; access_idx < NUM_MEM_CMDS; ++access_idx) {
 533         Packet::Command cmd = (Packet::Command)access_idx;
 534         const string &cstr = temp_pkt.cmdIdxToString(cmd);
 535
 536         accesses[access_idx]
 537             .name(name() + "." + cstr + "_accesses")
 538             .desc("number of " + cstr + " accesses(hits+misses)")
 539             .flags(total | nozero | nonan)
 540             ;
 541
 542         accesses[access_idx] = hits[access_idx] + misses[access_idx];
 543     }
 544
 545     demandAccesses
 546         .name(name() + ".demand_accesses")
 547         .desc("number of demand (read+write) accesses")
 548         .flags(total)
 549         ;
 550     demandAccesses = demandHits + demandMisses;
 551
 552     overallAccesses
 553         .name(name() + ".overall_accesses")
 554         .desc("number of overall (read+write) accesses")
 555         .flags(total)
 556         ;
 557     overallAccesses = overallHits + overallMisses;
 558
 559     // miss rate formulas
 560     for (int access_idx = 0; access_idx < NUM_MEM_CMDS; ++access_idx) {
 561         Packet::Command cmd = (Packet::Command)access_idx;
 562         const string &cstr = temp_pkt.cmdIdxToString(cmd);
 563
 564         missRate[access_idx]
 565             .name(name() + "." + cstr + "_miss_rate")
 566             .desc("miss rate for " + cstr + " accesses")
 567             .flags(total | nozero | nonan)
 568             ;
 569
 570         missRate[access_idx] = misses[access_idx] / accesses[access_idx];
 571     }
 572
 573     demandMissRate
 574         .name(name() + ".demand_miss_rate")
 575         .desc("miss rate for demand accesses")
 576         .flags(total)
 577         ;
 578     demandMissRate = demandMisses / demandAccesses;
 579
 580     overallMissRate
 581         .name(name() + ".overall_miss_rate")
 582         .desc("miss rate for overall accesses")
 583         .flags(total)
 584         ;
 585     overallMissRate = overallMisses / overallAccesses;
 586
 587     // miss latency formulas
 588     for (int access_idx = 0; access_idx < NUM_MEM_CMDS; ++access_idx) {
 589         Packet::Command cmd = (Packet::Command)access_idx;
 590         const string &cstr = temp_pkt.cmdIdxToString(cmd);
 591
 592         avgMissLatency[access_idx]
 593             .name(name() + "." + cstr + "_avg_miss_latency")
 594             .desc("average " + cstr + " miss latency")
 595             .flags(total | nozero | nonan)
 596             ;
 597
 598         avgMissLatency[access_idx] =
 599             missLatency[access_idx] / misses[access_idx];
 600     }
 601
 602     demandAvgMissLatency
 603         .name(name() + ".demand_avg_miss_latency")
 604         .desc("average overall miss latency")
 605         .flags(total)
 606         ;
 607     demandAvgMissLatency = demandMissLatency / demandMisses;
 608
 609     overallAvgMissLatency
 610         .name(name() + ".overall_avg_miss_latency")
 611         .desc("average overall miss latency")
 612         .flags(total)
 613         ;
 614     overallAvgMissLatency = overallMissLatency / overallMisses;
 615
 616     blocked_cycles.init(NUM_BLOCKED_CAUSES);
 617     blocked_cycles
 618         .name(name() + ".blocked_cycles")
 619         .desc("number of cycles access was blocked")
 620         .subname(Blocked_NoMSHRs, "no_mshrs")
 621         .subname(Blocked_NoTargets, "no_targets")
 622         ;
 623
 624
 625     blocked_causes.init(NUM_BLOCKED_CAUSES);
 626     blocked_causes
 627         .name(name() + ".blocked")
 628         .desc("number of cycles access was blocked")
 629         .subname(Blocked_NoMSHRs, "no_mshrs")
 630         .subname(Blocked_NoTargets, "no_targets")
 631         ;
 632
 633     avg_blocked
 634         .name(name() + ".avg_blocked_cycles")
 635         .desc("average number of cycles each access was blocked")
 636         .subname(Blocked_NoMSHRs, "no_mshrs")
 637         .subname(Blocked_NoTargets, "no_targets")
 638         ;
 639
 640     avg_blocked = blocked_cycles / blocked_causes;
 641
 642     fastWrites
 643         .name(name() + ".fast_writes")
 644         .desc("number of fast writes performed")
 645         ;
 646
 647     cacheCopies
 648         .name(name() + ".cache_copies")
 649         .desc("number of cache copies performed")
 650         ;
 651
 652 }
 653
 654 unsigned int
 655 BaseCache::drain(Event *de)
 656 {
 657     // Set status
 658     if (!canDrain()) {
 659         drainEvent = de;
 660
 661         changeState(SimObject::Draining);
 662         return 1;
 663     }
 664
 665     changeState(SimObject::Drained);
 666     return 0;
 667 }