2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Authors: Erik Hallnor
33 * Definition of BaseCache functions.
36 #include "cpu/base.hh"
38 #include "mem/cache/base_cache.hh"
39 #include "mem/cache/miss/mshr.hh"
43 BaseCache::CachePort::CachePort(const std::string
&_name
, BaseCache
*_cache
,
45 : Port(_name
), cache(_cache
), isCpuSide(_isCpuSide
)
48 waitingOnRetry
= false;
49 //Start ports at null if more than one is created we should panic
55 BaseCache::CachePort::recvStatusChange(Port::Status status
)
57 cache
->recvStatusChange(status
, isCpuSide
);
61 BaseCache::CachePort::getDeviceAddressRanges(AddrRangeList
&resp
,
64 cache
->getAddressRanges(resp
, snoop
, isCpuSide
);
68 BaseCache::CachePort::deviceBlockSize()
70 return cache
->getBlockSize();
74 BaseCache::CachePort::recvTiming(PacketPtr pkt
)
77 && !pkt
->req
->isUncacheable()
78 && pkt
->isInvalidate()
79 && !pkt
->isRead() && !pkt
->isWrite()) {
80 //Upgrade or Invalidate
81 //Look into what happens if two slave caches on bus
82 DPRINTF(Cache
, "%s %x ? blk_addr: %x\n", pkt
->cmdString(),
83 pkt
->getAddr() & (((ULL(1))<<48)-1),
84 pkt
->getAddr() & ~((Addr
)cache
->blkSize
- 1));
86 assert(!(pkt
->flags
& SATISFIED
));
87 pkt
->flags
|= SATISFIED
;
88 //Invalidates/Upgrades need no response if they get the bus
92 if (pkt
->isRequest() && blocked
)
94 DPRINTF(Cache
,"Scheduling a retry while blocked\n");
98 return cache
->doTimingAccess(pkt
, this, isCpuSide
);
102 BaseCache::CachePort::recvAtomic(PacketPtr pkt
)
104 return cache
->doAtomicAccess(pkt
, isCpuSide
);
108 BaseCache::CachePort::recvFunctional(PacketPtr pkt
)
110 //Check storage here first
111 list
<PacketPtr
>::iterator i
= drainList
.begin();
112 list
<PacketPtr
>::iterator end
= drainList
.end();
113 for (; i
!= end
; ++i
) {
114 PacketPtr target
= *i
;
115 // If the target contains data, and it overlaps the
116 // probed request, need to update data
117 if (target
->intersect(pkt
)) {
118 fixPacket(pkt
, target
);
121 cache
->doFunctionalAccess(pkt
, isCpuSide
);
125 BaseCache::CachePort::recvRetry()
128 assert(waitingOnRetry
);
129 if (!drainList
.empty()) {
130 DPRINTF(CachePort
, "%s attempting to send a retry for response\n", name());
131 //We have some responses to drain first
132 if (sendTiming(drainList
.front())) {
133 DPRINTF(CachePort
, "%s sucessful in sending a retry for response\n", name());
134 drainList
.pop_front();
135 if (!drainList
.empty() ||
136 !isCpuSide
&& cache
->doMasterRequest() ||
137 isCpuSide
&& cache
->doSlaveRequest()) {
139 DPRINTF(CachePort
, "%s has more responses/requests\n", name());
140 BaseCache::CacheEvent
* reqCpu
= new BaseCache::CacheEvent(this);
141 reqCpu
->schedule(curTick
+ 1);
143 waitingOnRetry
= false;
148 DPRINTF(CachePort
, "%s attempting to send a retry for MSHR\n", name());
149 if (!cache
->doMasterRequest()) {
150 //This can happen if I am the owner of a block and see an upgrade
151 //while the block was in my WB Buffers. I just remove the
152 //wb and de-assert the masterRequest
153 waitingOnRetry
= false;
156 pkt
= cache
->getPacket();
157 MSHR
* mshr
= (MSHR
*) pkt
->senderState
;
158 //Copy the packet, it may be modified/destroyed elsewhere
159 PacketPtr copyPkt
= new Packet(*pkt
);
160 copyPkt
->dataStatic
<uint8_t>(pkt
->getPtr
<uint8_t>());
163 bool success
= sendTiming(pkt
);
164 DPRINTF(Cache
, "Address %x was %s in sending the timing request\n",
165 pkt
->getAddr(), success
? "succesful" : "unsuccesful");
167 waitingOnRetry
= !success
;
168 if (waitingOnRetry
) {
169 DPRINTF(CachePort
, "%s now waiting on a retry\n", name());
172 cache
->sendResult(pkt
, mshr
, success
);
174 if (success
&& cache
->doMasterRequest())
176 DPRINTF(CachePort
, "%s has more requests\n", name());
177 //Still more to issue, rerequest in 1 cycle
178 BaseCache::CacheEvent
* reqCpu
= new BaseCache::CacheEvent(this);
179 reqCpu
->schedule(curTick
+ 1);
184 assert(cache
->doSlaveRequest());
185 //pkt = cache->getCoherencePacket();
186 //We save the packet, no reordering on CSHRS
187 pkt
= cache
->getCoherencePacket();
188 MSHR
* cshr
= (MSHR
*)pkt
->senderState
;
189 bool success
= sendTiming(pkt
);
190 cache
->sendCoherenceResult(pkt
, cshr
, success
);
191 waitingOnRetry
= !success
;
192 if (success
&& cache
->doSlaveRequest())
194 DPRINTF(CachePort
, "%s has more requests\n", name());
195 //Still more to issue, rerequest in 1 cycle
196 BaseCache::CacheEvent
* reqCpu
= new BaseCache::CacheEvent(this);
197 reqCpu
->schedule(curTick
+ 1);
200 if (waitingOnRetry
) DPRINTF(CachePort
, "%s STILL Waiting on retry\n", name());
201 else DPRINTF(CachePort
, "%s no longer waiting on retry\n", name());
205 BaseCache::CachePort::setBlocked()
208 DPRINTF(Cache
, "Cache Blocking\n");
210 //Clear the retry flag
211 mustSendRetry
= false;
215 BaseCache::CachePort::clearBlocked()
218 DPRINTF(Cache
, "Cache Unblocking\n");
222 DPRINTF(Cache
, "Cache Sending Retry\n");
223 mustSendRetry
= false;
228 BaseCache::CacheEvent::CacheEvent(CachePort
*_cachePort
)
229 : Event(&mainEventQueue
, CPU_Tick_Pri
), cachePort(_cachePort
)
231 this->setFlags(AutoDelete
);
235 BaseCache::CacheEvent::CacheEvent(CachePort
*_cachePort
, PacketPtr _pkt
)
236 : Event(&mainEventQueue
, CPU_Tick_Pri
), cachePort(_cachePort
), pkt(_pkt
)
238 this->setFlags(AutoDelete
);
242 BaseCache::CacheEvent::process()
246 if (cachePort
->waitingOnRetry
) return;
247 //We have some responses to drain first
248 if (!cachePort
->drainList
.empty()) {
249 DPRINTF(CachePort
, "%s trying to drain a response\n", cachePort
->name());
250 if (cachePort
->sendTiming(cachePort
->drainList
.front())) {
251 DPRINTF(CachePort
, "%s drains a response succesfully\n", cachePort
->name());
252 cachePort
->drainList
.pop_front();
253 if (!cachePort
->drainList
.empty() ||
254 !cachePort
->isCpuSide
&& cachePort
->cache
->doMasterRequest() ||
255 cachePort
->isCpuSide
&& cachePort
->cache
->doSlaveRequest()) {
257 DPRINTF(CachePort
, "%s still has outstanding bus reqs\n", cachePort
->name());
258 this->schedule(curTick
+ 1);
262 cachePort
->waitingOnRetry
= true;
263 DPRINTF(CachePort
, "%s now waiting on a retry\n", cachePort
->name());
266 else if (!cachePort
->isCpuSide
)
268 DPRINTF(CachePort
, "%s trying to send a MSHR request\n", cachePort
->name());
269 if (!cachePort
->cache
->doMasterRequest()) {
270 //This can happen if I am the owner of a block and see an upgrade
271 //while the block was in my WB Buffers. I just remove the
272 //wb and de-assert the masterRequest
276 pkt
= cachePort
->cache
->getPacket();
277 MSHR
* mshr
= (MSHR
*) pkt
->senderState
;
278 //Copy the packet, it may be modified/destroyed elsewhere
279 PacketPtr copyPkt
= new Packet(*pkt
);
280 copyPkt
->dataStatic
<uint8_t>(pkt
->getPtr
<uint8_t>());
283 bool success
= cachePort
->sendTiming(pkt
);
284 DPRINTF(Cache
, "Address %x was %s in sending the timing request\n",
285 pkt
->getAddr(), success
? "succesful" : "unsuccesful");
287 cachePort
->waitingOnRetry
= !success
;
288 if (cachePort
->waitingOnRetry
) {
289 DPRINTF(CachePort
, "%s now waiting on a retry\n", cachePort
->name());
292 cachePort
->cache
->sendResult(pkt
, mshr
, success
);
293 if (success
&& cachePort
->cache
->doMasterRequest())
295 DPRINTF(CachePort
, "%s still more MSHR requests to send\n",
297 //Still more to issue, rerequest in 1 cycle
299 this->schedule(curTick
+1);
305 assert(cachePort
->cache
->doSlaveRequest());
306 pkt
= cachePort
->cache
->getCoherencePacket();
307 MSHR
* cshr
= (MSHR
*) pkt
->senderState
;
308 bool success
= cachePort
->sendTiming(pkt
);
309 cachePort
->cache
->sendCoherenceResult(pkt
, cshr
, success
);
310 cachePort
->waitingOnRetry
= !success
;
311 if (cachePort
->waitingOnRetry
)
312 DPRINTF(CachePort
, "%s now waiting on a retry\n", cachePort
->name());
313 if (success
&& cachePort
->cache
->doSlaveRequest())
315 DPRINTF(CachePort
, "%s still more CSHR requests to send\n",
317 //Still more to issue, rerequest in 1 cycle
319 this->schedule(curTick
+1);
325 //Know the packet to send
326 if (pkt
->flags
& NACKED_LINE
)
327 pkt
->result
= Packet::Nacked
;
329 pkt
->result
= Packet::Success
;
330 pkt
->makeTimingResponse();
331 DPRINTF(CachePort
, "%s attempting to send a response\n", cachePort
->name());
332 if (!cachePort
->drainList
.empty() || cachePort
->waitingOnRetry
) {
333 //Already have a list, just append
334 cachePort
->drainList
.push_back(pkt
);
335 DPRINTF(CachePort
, "%s appending response onto drain list\n", cachePort
->name());
337 else if (!cachePort
->sendTiming(pkt
)) {
338 //It failed, save it to list of drain events
339 DPRINTF(CachePort
, "%s now waiting for a retry\n", cachePort
->name());
340 cachePort
->drainList
.push_back(pkt
);
341 cachePort
->waitingOnRetry
= true;
346 BaseCache::CacheEvent::description()
348 return "timing event\n";
352 BaseCache::getPort(const std::string
&if_name
, int idx
)
356 if(cpuSidePort
== NULL
)
357 cpuSidePort
= new CachePort(name() + "-cpu_side_port", this, true);
360 else if (if_name
== "functional")
362 if(cpuSidePort
== NULL
)
363 cpuSidePort
= new CachePort(name() + "-cpu_side_port", this, true);
366 else if (if_name
== "cpu_side")
368 if(cpuSidePort
== NULL
)
369 cpuSidePort
= new CachePort(name() + "-cpu_side_port", this, true);
372 else if (if_name
== "mem_side")
374 if (memSidePort
!= NULL
)
375 panic("Already have a mem side for this cache\n");
376 memSidePort
= new CachePort(name() + "-mem_side_port", this, false);
379 else panic("Port name %s unrecognized\n", if_name
);
385 if (!cpuSidePort
|| !memSidePort
)
386 panic("Cache not hooked up on both sides\n");
387 cpuSidePort
->sendStatusChange(Port::RangeChange
);
391 BaseCache::regStats()
393 Request
temp_req((Addr
) NULL
, 4, 0);
394 Packet::Command temp_cmd
= Packet::ReadReq
;
395 Packet
temp_pkt(&temp_req
, temp_cmd
, 0); //@todo FIx command strings so this isn't neccessary
396 temp_pkt
.allocate(); //Temp allocate, all need data
398 using namespace Stats
;
401 for (int access_idx
= 0; access_idx
< NUM_MEM_CMDS
; ++access_idx
) {
402 Packet::Command cmd
= (Packet::Command
)access_idx
;
403 const string
&cstr
= temp_pkt
.cmdIdxToString(cmd
);
406 .init(maxThreadsPerCPU
)
407 .name(name() + "." + cstr
+ "_hits")
408 .desc("number of " + cstr
+ " hits")
409 .flags(total
| nozero
| nonan
)
414 .name(name() + ".demand_hits")
415 .desc("number of demand (read+write) hits")
418 demandHits
= hits
[Packet::ReadReq
] + hits
[Packet::WriteReq
];
421 .name(name() + ".overall_hits")
422 .desc("number of overall hits")
425 overallHits
= demandHits
+ hits
[Packet::SoftPFReq
] + hits
[Packet::HardPFReq
]
426 + hits
[Packet::Writeback
];
429 for (int access_idx
= 0; access_idx
< NUM_MEM_CMDS
; ++access_idx
) {
430 Packet::Command cmd
= (Packet::Command
)access_idx
;
431 const string
&cstr
= temp_pkt
.cmdIdxToString(cmd
);
434 .init(maxThreadsPerCPU
)
435 .name(name() + "." + cstr
+ "_misses")
436 .desc("number of " + cstr
+ " misses")
437 .flags(total
| nozero
| nonan
)
442 .name(name() + ".demand_misses")
443 .desc("number of demand (read+write) misses")
446 demandMisses
= misses
[Packet::ReadReq
] + misses
[Packet::WriteReq
];
449 .name(name() + ".overall_misses")
450 .desc("number of overall misses")
453 overallMisses
= demandMisses
+ misses
[Packet::SoftPFReq
] +
454 misses
[Packet::HardPFReq
] + misses
[Packet::Writeback
];
456 // Miss latency statistics
457 for (int access_idx
= 0; access_idx
< NUM_MEM_CMDS
; ++access_idx
) {
458 Packet::Command cmd
= (Packet::Command
)access_idx
;
459 const string
&cstr
= temp_pkt
.cmdIdxToString(cmd
);
461 missLatency
[access_idx
]
462 .init(maxThreadsPerCPU
)
463 .name(name() + "." + cstr
+ "_miss_latency")
464 .desc("number of " + cstr
+ " miss cycles")
465 .flags(total
| nozero
| nonan
)
470 .name(name() + ".demand_miss_latency")
471 .desc("number of demand (read+write) miss cycles")
474 demandMissLatency
= missLatency
[Packet::ReadReq
] + missLatency
[Packet::WriteReq
];
477 .name(name() + ".overall_miss_latency")
478 .desc("number of overall miss cycles")
481 overallMissLatency
= demandMissLatency
+ missLatency
[Packet::SoftPFReq
] +
482 missLatency
[Packet::HardPFReq
];
485 for (int access_idx
= 0; access_idx
< NUM_MEM_CMDS
; ++access_idx
) {
486 Packet::Command cmd
= (Packet::Command
)access_idx
;
487 const string
&cstr
= temp_pkt
.cmdIdxToString(cmd
);
490 .name(name() + "." + cstr
+ "_accesses")
491 .desc("number of " + cstr
+ " accesses(hits+misses)")
492 .flags(total
| nozero
| nonan
)
495 accesses
[access_idx
] = hits
[access_idx
] + misses
[access_idx
];
499 .name(name() + ".demand_accesses")
500 .desc("number of demand (read+write) accesses")
503 demandAccesses
= demandHits
+ demandMisses
;
506 .name(name() + ".overall_accesses")
507 .desc("number of overall (read+write) accesses")
510 overallAccesses
= overallHits
+ overallMisses
;
512 // miss rate formulas
513 for (int access_idx
= 0; access_idx
< NUM_MEM_CMDS
; ++access_idx
) {
514 Packet::Command cmd
= (Packet::Command
)access_idx
;
515 const string
&cstr
= temp_pkt
.cmdIdxToString(cmd
);
518 .name(name() + "." + cstr
+ "_miss_rate")
519 .desc("miss rate for " + cstr
+ " accesses")
520 .flags(total
| nozero
| nonan
)
523 missRate
[access_idx
] = misses
[access_idx
] / accesses
[access_idx
];
527 .name(name() + ".demand_miss_rate")
528 .desc("miss rate for demand accesses")
531 demandMissRate
= demandMisses
/ demandAccesses
;
534 .name(name() + ".overall_miss_rate")
535 .desc("miss rate for overall accesses")
538 overallMissRate
= overallMisses
/ overallAccesses
;
540 // miss latency formulas
541 for (int access_idx
= 0; access_idx
< NUM_MEM_CMDS
; ++access_idx
) {
542 Packet::Command cmd
= (Packet::Command
)access_idx
;
543 const string
&cstr
= temp_pkt
.cmdIdxToString(cmd
);
545 avgMissLatency
[access_idx
]
546 .name(name() + "." + cstr
+ "_avg_miss_latency")
547 .desc("average " + cstr
+ " miss latency")
548 .flags(total
| nozero
| nonan
)
551 avgMissLatency
[access_idx
] =
552 missLatency
[access_idx
] / misses
[access_idx
];
556 .name(name() + ".demand_avg_miss_latency")
557 .desc("average overall miss latency")
560 demandAvgMissLatency
= demandMissLatency
/ demandMisses
;
562 overallAvgMissLatency
563 .name(name() + ".overall_avg_miss_latency")
564 .desc("average overall miss latency")
567 overallAvgMissLatency
= overallMissLatency
/ overallMisses
;
569 blocked_cycles
.init(NUM_BLOCKED_CAUSES
);
571 .name(name() + ".blocked_cycles")
572 .desc("number of cycles access was blocked")
573 .subname(Blocked_NoMSHRs
, "no_mshrs")
574 .subname(Blocked_NoTargets
, "no_targets")
578 blocked_causes
.init(NUM_BLOCKED_CAUSES
);
580 .name(name() + ".blocked")
581 .desc("number of cycles access was blocked")
582 .subname(Blocked_NoMSHRs
, "no_mshrs")
583 .subname(Blocked_NoTargets
, "no_targets")
587 .name(name() + ".avg_blocked_cycles")
588 .desc("average number of cycles each access was blocked")
589 .subname(Blocked_NoMSHRs
, "no_mshrs")
590 .subname(Blocked_NoTargets
, "no_targets")
593 avg_blocked
= blocked_cycles
/ blocked_causes
;
596 .name(name() + ".fast_writes")
597 .desc("number of fast writes performed")
601 .name(name() + ".cache_copies")
602 .desc("number of cache copies performed")