2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Authors: Erik Hallnor
33 * Definition of BaseCache functions.
36 #include "cpu/base.hh"
38 #include "mem/cache/base_cache.hh"
39 #include "mem/cache/miss/mshr.hh"
43 BaseCache::CachePort::CachePort(const std::string
&_name
, BaseCache
*_cache
,
45 : Port(_name
, _cache
), cache(_cache
), isCpuSide(_isCpuSide
)
48 waitingOnRetry
= false;
49 //Start ports at null if more than one is created we should panic
55 BaseCache::CachePort::recvStatusChange(Port::Status status
)
57 cache
->recvStatusChange(status
, isCpuSide
);
61 BaseCache::CachePort::getDeviceAddressRanges(AddrRangeList
&resp
,
64 cache
->getAddressRanges(resp
, snoop
, isCpuSide
);
68 BaseCache::CachePort::deviceBlockSize()
70 return cache
->getBlockSize();
74 BaseCache::CachePort::recvTiming(PacketPtr pkt
)
77 && !pkt
->req
->isUncacheable()
78 && pkt
->isInvalidate()
79 && !pkt
->isRead() && !pkt
->isWrite()) {
80 //Upgrade or Invalidate
81 //Look into what happens if two slave caches on bus
82 DPRINTF(Cache
, "%s %x ?\n", pkt
->cmdString(), pkt
->getAddr());
84 assert(!(pkt
->flags
& SATISFIED
));
85 pkt
->flags
|= SATISFIED
;
86 //Invalidates/Upgrades need no response if they get the bus
90 if (pkt
->isRequest() && blocked
)
92 DPRINTF(Cache
,"Scheduling a retry while blocked\n");
96 return cache
->doTimingAccess(pkt
, this, isCpuSide
);
100 BaseCache::CachePort::recvAtomic(PacketPtr pkt
)
102 return cache
->doAtomicAccess(pkt
, isCpuSide
);
106 BaseCache::CachePort::recvFunctional(PacketPtr pkt
)
108 //Check storage here first
109 list
<PacketPtr
>::iterator i
= drainList
.begin();
110 list
<PacketPtr
>::iterator end
= drainList
.end();
111 for (; i
!= end
; ++i
) {
112 PacketPtr target
= *i
;
113 // If the target contains data, and it overlaps the
114 // probed request, need to update data
115 if (target
->intersect(pkt
)) {
116 fixPacket(pkt
, target
);
119 cache
->doFunctionalAccess(pkt
, isCpuSide
);
123 BaseCache::CachePort::recvRetry()
126 assert(waitingOnRetry
);
127 if (!drainList
.empty()) {
128 DPRINTF(CachePort
, "%s attempting to send a retry for response\n", name());
129 //We have some responses to drain first
130 if (sendTiming(drainList
.front())) {
131 DPRINTF(CachePort
, "%s sucessful in sending a retry for response\n", name());
132 drainList
.pop_front();
133 if (!drainList
.empty() ||
134 !isCpuSide
&& cache
->doMasterRequest() ||
135 isCpuSide
&& cache
->doSlaveRequest()) {
137 DPRINTF(CachePort
, "%s has more responses/requests\n", name());
138 BaseCache::CacheEvent
* reqCpu
= new BaseCache::CacheEvent(this);
139 reqCpu
->schedule(curTick
+ 1);
141 waitingOnRetry
= false;
143 // Check if we're done draining once this list is empty
144 if (drainList
.empty())
149 DPRINTF(CachePort
, "%s attempting to send a retry for MSHR\n", name());
150 if (!cache
->doMasterRequest()) {
151 //This can happen if I am the owner of a block and see an upgrade
152 //while the block was in my WB Buffers. I just remove the
153 //wb and de-assert the masterRequest
154 waitingOnRetry
= false;
157 pkt
= cache
->getPacket();
158 MSHR
* mshr
= (MSHR
*) pkt
->senderState
;
159 //Copy the packet, it may be modified/destroyed elsewhere
160 PacketPtr copyPkt
= new Packet(*pkt
);
161 copyPkt
->dataStatic
<uint8_t>(pkt
->getPtr
<uint8_t>());
164 bool success
= sendTiming(pkt
);
165 DPRINTF(Cache
, "Address %x was %s in sending the timing request\n",
166 pkt
->getAddr(), success
? "succesful" : "unsuccesful");
168 waitingOnRetry
= !success
;
169 if (waitingOnRetry
) {
170 DPRINTF(CachePort
, "%s now waiting on a retry\n", name());
173 cache
->sendResult(pkt
, mshr
, success
);
175 if (success
&& cache
->doMasterRequest())
177 DPRINTF(CachePort
, "%s has more requests\n", name());
178 //Still more to issue, rerequest in 1 cycle
179 BaseCache::CacheEvent
* reqCpu
= new BaseCache::CacheEvent(this);
180 reqCpu
->schedule(curTick
+ 1);
185 assert(cache
->doSlaveRequest());
186 //pkt = cache->getCoherencePacket();
187 //We save the packet, no reordering on CSHRS
188 pkt
= cache
->getCoherencePacket();
189 MSHR
* cshr
= (MSHR
*)pkt
->senderState
;
190 bool success
= sendTiming(pkt
);
191 cache
->sendCoherenceResult(pkt
, cshr
, success
);
192 waitingOnRetry
= !success
;
193 if (success
&& cache
->doSlaveRequest())
195 DPRINTF(CachePort
, "%s has more requests\n", name());
196 //Still more to issue, rerequest in 1 cycle
197 BaseCache::CacheEvent
* reqCpu
= new BaseCache::CacheEvent(this);
198 reqCpu
->schedule(curTick
+ 1);
201 if (waitingOnRetry
) DPRINTF(CachePort
, "%s STILL Waiting on retry\n", name());
202 else DPRINTF(CachePort
, "%s no longer waiting on retry\n", name());
206 BaseCache::CachePort::setBlocked()
209 DPRINTF(Cache
, "Cache Blocking\n");
211 //Clear the retry flag
212 mustSendRetry
= false;
216 BaseCache::CachePort::clearBlocked()
219 DPRINTF(Cache
, "Cache Unblocking\n");
223 DPRINTF(Cache
, "Cache Sending Retry\n");
224 mustSendRetry
= false;
229 BaseCache::CacheEvent::CacheEvent(CachePort
*_cachePort
)
230 : Event(&mainEventQueue
, CPU_Tick_Pri
), cachePort(_cachePort
)
232 this->setFlags(AutoDelete
);
236 BaseCache::CacheEvent::CacheEvent(CachePort
*_cachePort
, PacketPtr _pkt
)
237 : Event(&mainEventQueue
, CPU_Tick_Pri
), cachePort(_cachePort
), pkt(_pkt
)
239 this->setFlags(AutoDelete
);
243 BaseCache::CacheEvent::process()
247 if (cachePort
->waitingOnRetry
) return;
248 //We have some responses to drain first
249 if (!cachePort
->drainList
.empty()) {
250 DPRINTF(CachePort
, "%s trying to drain a response\n", cachePort
->name());
251 if (cachePort
->sendTiming(cachePort
->drainList
.front())) {
252 DPRINTF(CachePort
, "%s drains a response succesfully\n", cachePort
->name());
253 cachePort
->drainList
.pop_front();
254 if (!cachePort
->drainList
.empty() ||
255 !cachePort
->isCpuSide
&& cachePort
->cache
->doMasterRequest() ||
256 cachePort
->isCpuSide
&& cachePort
->cache
->doSlaveRequest()) {
258 DPRINTF(CachePort
, "%s still has outstanding bus reqs\n", cachePort
->name());
259 this->schedule(curTick
+ 1);
263 cachePort
->waitingOnRetry
= true;
264 DPRINTF(CachePort
, "%s now waiting on a retry\n", cachePort
->name());
267 else if (!cachePort
->isCpuSide
)
269 DPRINTF(CachePort
, "%s trying to send a MSHR request\n", cachePort
->name());
270 if (!cachePort
->cache
->doMasterRequest()) {
271 //This can happen if I am the owner of a block and see an upgrade
272 //while the block was in my WB Buffers. I just remove the
273 //wb and de-assert the masterRequest
277 pkt
= cachePort
->cache
->getPacket();
278 MSHR
* mshr
= (MSHR
*) pkt
->senderState
;
279 //Copy the packet, it may be modified/destroyed elsewhere
280 PacketPtr copyPkt
= new Packet(*pkt
);
281 copyPkt
->dataStatic
<uint8_t>(pkt
->getPtr
<uint8_t>());
284 bool success
= cachePort
->sendTiming(pkt
);
285 DPRINTF(Cache
, "Address %x was %s in sending the timing request\n",
286 pkt
->getAddr(), success
? "succesful" : "unsuccesful");
288 cachePort
->waitingOnRetry
= !success
;
289 if (cachePort
->waitingOnRetry
) {
290 DPRINTF(CachePort
, "%s now waiting on a retry\n", cachePort
->name());
293 cachePort
->cache
->sendResult(pkt
, mshr
, success
);
294 if (success
&& cachePort
->cache
->doMasterRequest())
296 DPRINTF(CachePort
, "%s still more MSHR requests to send\n",
298 //Still more to issue, rerequest in 1 cycle
300 this->schedule(curTick
+1);
306 assert(cachePort
->cache
->doSlaveRequest());
307 pkt
= cachePort
->cache
->getCoherencePacket();
308 MSHR
* cshr
= (MSHR
*) pkt
->senderState
;
309 bool success
= cachePort
->sendTiming(pkt
);
310 cachePort
->cache
->sendCoherenceResult(pkt
, cshr
, success
);
311 cachePort
->waitingOnRetry
= !success
;
312 if (cachePort
->waitingOnRetry
)
313 DPRINTF(CachePort
, "%s now waiting on a retry\n", cachePort
->name());
314 if (success
&& cachePort
->cache
->doSlaveRequest())
316 DPRINTF(CachePort
, "%s still more CSHR requests to send\n",
318 //Still more to issue, rerequest in 1 cycle
320 this->schedule(curTick
+1);
326 //Know the packet to send
327 if (pkt
->flags
& NACKED_LINE
)
328 pkt
->result
= Packet::Nacked
;
330 pkt
->result
= Packet::Success
;
331 pkt
->makeTimingResponse();
332 DPRINTF(CachePort
, "%s attempting to send a response\n", cachePort
->name());
333 if (!cachePort
->drainList
.empty() || cachePort
->waitingOnRetry
) {
334 //Already have a list, just append
335 cachePort
->drainList
.push_back(pkt
);
336 DPRINTF(CachePort
, "%s appending response onto drain list\n", cachePort
->name());
338 else if (!cachePort
->sendTiming(pkt
)) {
339 //It failed, save it to list of drain events
340 DPRINTF(CachePort
, "%s now waiting for a retry\n", cachePort
->name());
341 cachePort
->drainList
.push_back(pkt
);
342 cachePort
->waitingOnRetry
= true;
345 // Check if we're done draining once this list is empty
346 if (cachePort
->drainList
.empty())
347 cachePort
->cache
->checkDrain();
351 BaseCache::CacheEvent::description()
353 return "timing event\n";
357 BaseCache::getPort(const std::string
&if_name
, int idx
)
361 if(cpuSidePort
== NULL
)
362 cpuSidePort
= new CachePort(name() + "-cpu_side_port", this, true);
365 else if (if_name
== "functional")
367 return new CachePort(name() + "-cpu_side_port", this, true);
369 else if (if_name
== "cpu_side")
371 if(cpuSidePort
== NULL
)
372 cpuSidePort
= new CachePort(name() + "-cpu_side_port", this, true);
375 else if (if_name
== "mem_side")
377 if (memSidePort
!= NULL
)
378 panic("Already have a mem side for this cache\n");
379 memSidePort
= new CachePort(name() + "-mem_side_port", this, false);
382 else panic("Port name %s unrecognized\n", if_name
);
388 if (!cpuSidePort
|| !memSidePort
)
389 panic("Cache not hooked up on both sides\n");
390 cpuSidePort
->sendStatusChange(Port::RangeChange
);
394 BaseCache::regStats()
396 Request
temp_req((Addr
) NULL
, 4, 0);
397 Packet::Command temp_cmd
= Packet::ReadReq
;
398 Packet
temp_pkt(&temp_req
, temp_cmd
, 0); //@todo FIx command strings so this isn't neccessary
399 temp_pkt
.allocate(); //Temp allocate, all need data
401 using namespace Stats
;
404 for (int access_idx
= 0; access_idx
< NUM_MEM_CMDS
; ++access_idx
) {
405 Packet::Command cmd
= (Packet::Command
)access_idx
;
406 const string
&cstr
= temp_pkt
.cmdIdxToString(cmd
);
409 .init(maxThreadsPerCPU
)
410 .name(name() + "." + cstr
+ "_hits")
411 .desc("number of " + cstr
+ " hits")
412 .flags(total
| nozero
| nonan
)
417 .name(name() + ".demand_hits")
418 .desc("number of demand (read+write) hits")
421 demandHits
= hits
[Packet::ReadReq
] + hits
[Packet::WriteReq
];
424 .name(name() + ".overall_hits")
425 .desc("number of overall hits")
428 overallHits
= demandHits
+ hits
[Packet::SoftPFReq
] + hits
[Packet::HardPFReq
]
429 + hits
[Packet::Writeback
];
432 for (int access_idx
= 0; access_idx
< NUM_MEM_CMDS
; ++access_idx
) {
433 Packet::Command cmd
= (Packet::Command
)access_idx
;
434 const string
&cstr
= temp_pkt
.cmdIdxToString(cmd
);
437 .init(maxThreadsPerCPU
)
438 .name(name() + "." + cstr
+ "_misses")
439 .desc("number of " + cstr
+ " misses")
440 .flags(total
| nozero
| nonan
)
445 .name(name() + ".demand_misses")
446 .desc("number of demand (read+write) misses")
449 demandMisses
= misses
[Packet::ReadReq
] + misses
[Packet::WriteReq
];
452 .name(name() + ".overall_misses")
453 .desc("number of overall misses")
456 overallMisses
= demandMisses
+ misses
[Packet::SoftPFReq
] +
457 misses
[Packet::HardPFReq
] + misses
[Packet::Writeback
];
459 // Miss latency statistics
460 for (int access_idx
= 0; access_idx
< NUM_MEM_CMDS
; ++access_idx
) {
461 Packet::Command cmd
= (Packet::Command
)access_idx
;
462 const string
&cstr
= temp_pkt
.cmdIdxToString(cmd
);
464 missLatency
[access_idx
]
465 .init(maxThreadsPerCPU
)
466 .name(name() + "." + cstr
+ "_miss_latency")
467 .desc("number of " + cstr
+ " miss cycles")
468 .flags(total
| nozero
| nonan
)
473 .name(name() + ".demand_miss_latency")
474 .desc("number of demand (read+write) miss cycles")
477 demandMissLatency
= missLatency
[Packet::ReadReq
] + missLatency
[Packet::WriteReq
];
480 .name(name() + ".overall_miss_latency")
481 .desc("number of overall miss cycles")
484 overallMissLatency
= demandMissLatency
+ missLatency
[Packet::SoftPFReq
] +
485 missLatency
[Packet::HardPFReq
];
488 for (int access_idx
= 0; access_idx
< NUM_MEM_CMDS
; ++access_idx
) {
489 Packet::Command cmd
= (Packet::Command
)access_idx
;
490 const string
&cstr
= temp_pkt
.cmdIdxToString(cmd
);
493 .name(name() + "." + cstr
+ "_accesses")
494 .desc("number of " + cstr
+ " accesses(hits+misses)")
495 .flags(total
| nozero
| nonan
)
498 accesses
[access_idx
] = hits
[access_idx
] + misses
[access_idx
];
502 .name(name() + ".demand_accesses")
503 .desc("number of demand (read+write) accesses")
506 demandAccesses
= demandHits
+ demandMisses
;
509 .name(name() + ".overall_accesses")
510 .desc("number of overall (read+write) accesses")
513 overallAccesses
= overallHits
+ overallMisses
;
515 // miss rate formulas
516 for (int access_idx
= 0; access_idx
< NUM_MEM_CMDS
; ++access_idx
) {
517 Packet::Command cmd
= (Packet::Command
)access_idx
;
518 const string
&cstr
= temp_pkt
.cmdIdxToString(cmd
);
521 .name(name() + "." + cstr
+ "_miss_rate")
522 .desc("miss rate for " + cstr
+ " accesses")
523 .flags(total
| nozero
| nonan
)
526 missRate
[access_idx
] = misses
[access_idx
] / accesses
[access_idx
];
530 .name(name() + ".demand_miss_rate")
531 .desc("miss rate for demand accesses")
534 demandMissRate
= demandMisses
/ demandAccesses
;
537 .name(name() + ".overall_miss_rate")
538 .desc("miss rate for overall accesses")
541 overallMissRate
= overallMisses
/ overallAccesses
;
543 // miss latency formulas
544 for (int access_idx
= 0; access_idx
< NUM_MEM_CMDS
; ++access_idx
) {
545 Packet::Command cmd
= (Packet::Command
)access_idx
;
546 const string
&cstr
= temp_pkt
.cmdIdxToString(cmd
);
548 avgMissLatency
[access_idx
]
549 .name(name() + "." + cstr
+ "_avg_miss_latency")
550 .desc("average " + cstr
+ " miss latency")
551 .flags(total
| nozero
| nonan
)
554 avgMissLatency
[access_idx
] =
555 missLatency
[access_idx
] / misses
[access_idx
];
559 .name(name() + ".demand_avg_miss_latency")
560 .desc("average overall miss latency")
563 demandAvgMissLatency
= demandMissLatency
/ demandMisses
;
565 overallAvgMissLatency
566 .name(name() + ".overall_avg_miss_latency")
567 .desc("average overall miss latency")
570 overallAvgMissLatency
= overallMissLatency
/ overallMisses
;
572 blocked_cycles
.init(NUM_BLOCKED_CAUSES
);
574 .name(name() + ".blocked_cycles")
575 .desc("number of cycles access was blocked")
576 .subname(Blocked_NoMSHRs
, "no_mshrs")
577 .subname(Blocked_NoTargets
, "no_targets")
581 blocked_causes
.init(NUM_BLOCKED_CAUSES
);
583 .name(name() + ".blocked")
584 .desc("number of cycles access was blocked")
585 .subname(Blocked_NoMSHRs
, "no_mshrs")
586 .subname(Blocked_NoTargets
, "no_targets")
590 .name(name() + ".avg_blocked_cycles")
591 .desc("average number of cycles each access was blocked")
592 .subname(Blocked_NoMSHRs
, "no_mshrs")
593 .subname(Blocked_NoTargets
, "no_targets")
596 avg_blocked
= blocked_cycles
/ blocked_causes
;
599 .name(name() + ".fast_writes")
600 .desc("number of fast writes performed")
604 .name(name() + ".cache_copies")
605 .desc("number of cache copies performed")
611 BaseCache::drain(Event
*de
)
617 changeState(SimObject::Draining
);
621 changeState(SimObject::Drained
);