src/mem/cache/base_cache.cc

   1 /*
   2  * Copyright (c) 2003-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Erik Hallnor
  29  */
  30
  31 /**
  32  * @file
  33  * Definition of BaseCache functions.
  34  */
  35
  36 #include "cpu/base.hh"
  37 #include "cpu/smt.hh"
  38 #include "mem/cache/base_cache.hh"
  39 #include "mem/cache/miss/mshr.hh"
  40
  41 using namespace std;
  42
  43 BaseCache::CachePort::CachePort(const std::string &_name, BaseCache *_cache,
  44                                 bool _isCpuSide)
  45     : Port(_name, _cache), cache(_cache), isCpuSide(_isCpuSide)
  46 {
  47     blocked = false;
  48     waitingOnRetry = false;
  49     //Start ports at null if more than one is created we should panic
  50     //cpuSidePort = NULL;
  51     //memSidePort = NULL;
  52 }
  53
  54 void
  55 BaseCache::CachePort::recvStatusChange(Port::Status status)
  56 {
  57     cache->recvStatusChange(status, isCpuSide);
  58 }
  59
  60 void
  61 BaseCache::CachePort::getDeviceAddressRanges(AddrRangeList &resp,
  62                                        AddrRangeList &snoop)
  63 {
  64     cache->getAddressRanges(resp, snoop, isCpuSide);
  65 }
  66
  67 int
  68 BaseCache::CachePort::deviceBlockSize()
  69 {
  70     return cache->getBlockSize();
  71 }
  72
  73 bool
  74 BaseCache::CachePort::recvTiming(PacketPtr pkt)
  75 {
  76     if (isCpuSide
  77         && !pkt->req->isUncacheable()
  78         && pkt->isInvalidate()
  79         && !pkt->isRead() && !pkt->isWrite()) {
  80         //Upgrade or Invalidate
  81         //Look into what happens if two slave caches on bus
  82         DPRINTF(Cache, "%s %x ?\n", pkt->cmdString(), pkt->getAddr());
  83
  84         assert(!(pkt->flags & SATISFIED));
  85         pkt->flags |= SATISFIED;
  86         //Invalidates/Upgrades need no response if they get the bus
  87         return true;
  88     }
  89
  90     if (pkt->isRequest() && blocked)
  91     {
  92         DPRINTF(Cache,"Scheduling a retry while blocked\n");
  93         mustSendRetry = true;
  94         return false;
  95     }
  96     return cache->doTimingAccess(pkt, this, isCpuSide);
  97 }
  98
  99 Tick
 100 BaseCache::CachePort::recvAtomic(PacketPtr pkt)
 101 {
 102     return cache->doAtomicAccess(pkt, isCpuSide);
 103 }
 104
 105 bool
 106 BaseCache::CachePort::checkFunctional(PacketPtr pkt)
 107 {
 108     //Check storage here first
 109     list<PacketPtr>::iterator i = drainList.begin();
 110     list<PacketPtr>::iterator iend = drainList.end();
 111     bool notDone = true;
 112     while (i != iend && notDone) {
 113         PacketPtr target = *i;
 114         // If the target contains data, and it overlaps the
 115         // probed request, need to update data
 116         if (target->intersect(pkt)) {
 117             notDone = fixPacket(pkt, target);
 118         }
 119         i++;
 120     }
 121     //Also check the response not yet ready to be on the list
 122     std::list<std::pair<Tick,PacketPtr> >::iterator j = transmitList.begin();
 123     std::list<std::pair<Tick,PacketPtr> >::iterator jend = transmitList.end();
 124
 125     while (j != jend && notDone) {
 126         PacketPtr target = j->second;
 127         // If the target contains data, and it overlaps the
 128         // probed request, need to update data
 129         if (target->intersect(pkt))
 130             notDone = fixPacket(pkt, target);
 131         j++;
 132     }
 133     return notDone;
 134 }
 135
 136 void
 137 BaseCache::CachePort::recvFunctional(PacketPtr pkt)
 138 {
 139     bool notDone = checkFunctional(pkt);
 140     if (notDone)
 141         cache->doFunctionalAccess(pkt, isCpuSide);
 142 }
 143
 144 void
 145 BaseCache::CachePort::checkAndSendFunctional(PacketPtr pkt)
 146 {
 147     bool notDone = checkFunctional(pkt);
 148     if (notDone)
 149         sendFunctional(pkt);
 150 }
 151
 152 void
 153 BaseCache::CachePort::recvRetry()
 154 {
 155     PacketPtr pkt;
 156     assert(waitingOnRetry);
 157     if (!drainList.empty()) {
 158         DPRINTF(CachePort, "%s attempting to send a retry for response\n", name());
 159         //We have some responses to drain first
 160         if (sendTiming(drainList.front())) {
 161             DPRINTF(CachePort, "%s sucessful in sending a retry for response\n", name());
 162             drainList.pop_front();
 163             if (!drainList.empty() ||
 164                 !isCpuSide && cache->doMasterRequest() ||
 165                 isCpuSide && cache->doSlaveRequest()) {
 166
 167                 DPRINTF(CachePort, "%s has more responses/requests\n", name());
 168                 BaseCache::CacheEvent * reqCpu = new BaseCache::CacheEvent(this, false);
 169                 reqCpu->schedule(curTick + 1);
 170             }
 171             waitingOnRetry = false;
 172         }
 173         // Check if we're done draining once this list is empty
 174         if (drainList.empty())
 175             cache->checkDrain();
 176     }
 177     else if (!isCpuSide)
 178     {
 179         DPRINTF(CachePort, "%s attempting to send a retry for MSHR\n", name());
 180         if (!cache->doMasterRequest()) {
 181             //This can happen if I am the owner of a block and see an upgrade
 182             //while the block was in my WB Buffers.  I just remove the
 183             //wb and de-assert the masterRequest
 184             waitingOnRetry = false;
 185             return;
 186         }
 187         pkt = cache->getPacket();
 188         MSHR* mshr = (MSHR*) pkt->senderState;
 189         //Copy the packet, it may be modified/destroyed elsewhere
 190         PacketPtr copyPkt = new Packet(*pkt);
 191         copyPkt->dataStatic<uint8_t>(pkt->getPtr<uint8_t>());
 192         mshr->pkt = copyPkt;
 193
 194         bool success = sendTiming(pkt);
 195         DPRINTF(Cache, "Address %x was %s in sending the timing request\n",
 196                 pkt->getAddr(), success ? "succesful" : "unsuccesful");
 197
 198         waitingOnRetry = !success;
 199         if (waitingOnRetry) {
 200             DPRINTF(CachePort, "%s now waiting on a retry\n", name());
 201         }
 202
 203         cache->sendResult(pkt, mshr, success);
 204
 205         if (success && cache->doMasterRequest())
 206         {
 207             DPRINTF(CachePort, "%s has more requests\n", name());
 208             //Still more to issue, rerequest in 1 cycle
 209             BaseCache::CacheEvent * reqCpu = new BaseCache::CacheEvent(this, false);
 210             reqCpu->schedule(curTick + 1);
 211         }
 212     }
 213     else
 214     {
 215         assert(cache->doSlaveRequest());
 216         //pkt = cache->getCoherencePacket();
 217         //We save the packet, no reordering on CSHRS
 218         pkt = cache->getCoherencePacket();
 219         MSHR* cshr = (MSHR*)pkt->senderState;
 220         bool success = sendTiming(pkt);
 221         cache->sendCoherenceResult(pkt, cshr, success);
 222         waitingOnRetry = !success;
 223         if (success && cache->doSlaveRequest())
 224         {
 225             DPRINTF(CachePort, "%s has more requests\n", name());
 226             //Still more to issue, rerequest in 1 cycle
 227             BaseCache::CacheEvent * reqCpu = new BaseCache::CacheEvent(this, false);
 228             reqCpu->schedule(curTick + 1);
 229         }
 230     }
 231     if (waitingOnRetry) DPRINTF(CachePort, "%s STILL Waiting on retry\n", name());
 232     else DPRINTF(CachePort, "%s no longer waiting on retry\n", name());
 233     return;
 234 }
 235 void
 236 BaseCache::CachePort::setBlocked()
 237 {
 238     assert(!blocked);
 239     DPRINTF(Cache, "Cache Blocking\n");
 240     blocked = true;
 241     //Clear the retry flag
 242     mustSendRetry = false;
 243 }
 244
 245 void
 246 BaseCache::CachePort::clearBlocked()
 247 {
 248     assert(blocked);
 249     DPRINTF(Cache, "Cache Unblocking\n");
 250     blocked = false;
 251     if (mustSendRetry)
 252     {
 253         DPRINTF(Cache, "Cache Sending Retry\n");
 254         mustSendRetry = false;
 255         sendRetry();
 256     }
 257 }
 258
 259 BaseCache::CacheEvent::CacheEvent(CachePort *_cachePort, bool _newResponse)
 260     : Event(&mainEventQueue, CPU_Tick_Pri), cachePort(_cachePort),
 261       newResponse(_newResponse)
 262 {
 263     if (!newResponse)
 264         this->setFlags(AutoDelete);
 265     pkt = NULL;
 266 }
 267
 268 void
 269 BaseCache::CacheEvent::process()
 270 {
 271     if (!newResponse)
 272     {
 273         if (cachePort->waitingOnRetry) return;
 274        //We have some responses to drain first
 275         if (!cachePort->drainList.empty()) {
 276             DPRINTF(CachePort, "%s trying to drain a response\n", cachePort->name());
 277             if (cachePort->sendTiming(cachePort->drainList.front())) {
 278                 DPRINTF(CachePort, "%s drains a response succesfully\n", cachePort->name());
 279                 cachePort->drainList.pop_front();
 280                 if (!cachePort->drainList.empty() ||
 281                     !cachePort->isCpuSide && cachePort->cache->doMasterRequest() ||
 282                     cachePort->isCpuSide && cachePort->cache->doSlaveRequest()) {
 283
 284                     DPRINTF(CachePort, "%s still has outstanding bus reqs\n", cachePort->name());
 285                     this->schedule(curTick + 1);
 286                 }
 287             }
 288             else {
 289                 cachePort->waitingOnRetry = true;
 290                 DPRINTF(CachePort, "%s now waiting on a retry\n", cachePort->name());
 291             }
 292         }
 293         else if (!cachePort->isCpuSide)
 294         {            //MSHR
 295             DPRINTF(CachePort, "%s trying to send a MSHR request\n", cachePort->name());
 296             if (!cachePort->cache->doMasterRequest()) {
 297                 //This can happen if I am the owner of a block and see an upgrade
 298                 //while the block was in my WB Buffers.  I just remove the
 299                 //wb and de-assert the masterRequest
 300                 return;
 301             }
 302
 303             pkt = cachePort->cache->getPacket();
 304             MSHR* mshr = (MSHR*) pkt->senderState;
 305             //Copy the packet, it may be modified/destroyed elsewhere
 306             PacketPtr copyPkt = new Packet(*pkt);
 307             copyPkt->dataStatic<uint8_t>(pkt->getPtr<uint8_t>());
 308             mshr->pkt = copyPkt;
 309
 310             bool success = cachePort->sendTiming(pkt);
 311             DPRINTF(Cache, "Address %x was %s in sending the timing request\n",
 312                     pkt->getAddr(), success ? "succesful" : "unsuccesful");
 313
 314             cachePort->waitingOnRetry = !success;
 315             if (cachePort->waitingOnRetry) {
 316                 DPRINTF(CachePort, "%s now waiting on a retry\n", cachePort->name());
 317             }
 318
 319             cachePort->cache->sendResult(pkt, mshr, success);
 320             if (success && cachePort->cache->doMasterRequest())
 321             {
 322                 DPRINTF(CachePort, "%s still more MSHR requests to send\n",
 323                         cachePort->name());
 324                 //Still more to issue, rerequest in 1 cycle
 325                 pkt = NULL;
 326                 this->schedule(curTick+1);
 327             }
 328         }
 329         else
 330         {
 331             //CSHR
 332             assert(cachePort->cache->doSlaveRequest());
 333             pkt = cachePort->cache->getCoherencePacket();
 334             MSHR* cshr = (MSHR*) pkt->senderState;
 335             bool success = cachePort->sendTiming(pkt);
 336             cachePort->cache->sendCoherenceResult(pkt, cshr, success);
 337             cachePort->waitingOnRetry = !success;
 338             if (cachePort->waitingOnRetry)
 339                 DPRINTF(CachePort, "%s now waiting on a retry\n", cachePort->name());
 340             if (success && cachePort->cache->doSlaveRequest())
 341             {
 342                 DPRINTF(CachePort, "%s still more CSHR requests to send\n",
 343                         cachePort->name());
 344                 //Still more to issue, rerequest in 1 cycle
 345                 pkt = NULL;
 346                 this->schedule(curTick+1);
 347             }
 348         }
 349         return;
 350     }
 351     //Else it's a response Response
 352     assert(cachePort->transmitList.size());
 353     assert(cachePort->transmitList.front().first <= curTick);
 354     pkt = cachePort->transmitList.front().second;
 355     cachePort->transmitList.pop_front();
 356     if (!cachePort->transmitList.empty()) {
 357         Tick time = cachePort->transmitList.front().first;
 358         schedule(time <= curTick ? curTick+1 : time);
 359     }
 360
 361     if (pkt->flags & NACKED_LINE)
 362         pkt->result = Packet::Nacked;
 363     else
 364         pkt->result = Packet::Success;
 365     pkt->makeTimingResponse();
 366     DPRINTF(CachePort, "%s attempting to send a response\n", cachePort->name());
 367     if (!cachePort->drainList.empty() || cachePort->waitingOnRetry) {
 368         //Already have a list, just append
 369         cachePort->drainList.push_back(pkt);
 370         DPRINTF(CachePort, "%s appending response onto drain list\n", cachePort->name());
 371     }
 372     else if (!cachePort->sendTiming(pkt)) {
 373         //It failed, save it to list of drain events
 374         DPRINTF(CachePort, "%s now waiting for a retry\n", cachePort->name());
 375         cachePort->drainList.push_back(pkt);
 376         cachePort->waitingOnRetry = true;
 377     }
 378
 379     // Check if we're done draining once this list is empty
 380     if (cachePort->drainList.empty() && cachePort->transmitList.empty())
 381         cachePort->cache->checkDrain();
 382 }
 383
 384 const char *
 385 BaseCache::CacheEvent::description()
 386 {
 387     return "timing event\n";
 388 }
 389
 390 Port*
 391 BaseCache::getPort(const std::string &if_name, int idx)
 392 {
 393     if (if_name == "")
 394     {
 395         if(cpuSidePort == NULL) {
 396             cpuSidePort = new CachePort(name() + "-cpu_side_port", this, true);
 397             sendEvent = new CacheEvent(cpuSidePort, true);
 398         }
 399         return cpuSidePort;
 400     }
 401     else if (if_name == "functional")
 402     {
 403         return new CachePort(name() + "-cpu_side_port", this, true);
 404     }
 405     else if (if_name == "cpu_side")
 406     {
 407         if(cpuSidePort == NULL) {
 408             cpuSidePort = new CachePort(name() + "-cpu_side_port", this, true);
 409             sendEvent = new CacheEvent(cpuSidePort, true);
 410         }
 411         return cpuSidePort;
 412     }
 413     else if (if_name == "mem_side")
 414     {
 415         if (memSidePort != NULL)
 416             panic("Already have a mem side for this cache\n");
 417         memSidePort = new CachePort(name() + "-mem_side_port", this, false);
 418         memSendEvent = new CacheEvent(memSidePort, true);
 419         return memSidePort;
 420     }
 421     else panic("Port name %s unrecognized\n", if_name);
 422 }
 423
 424 void
 425 BaseCache::init()
 426 {
 427     if (!cpuSidePort || !memSidePort)
 428         panic("Cache not hooked up on both sides\n");
 429     cpuSidePort->sendStatusChange(Port::RangeChange);
 430 }
 431
 432 void
 433 BaseCache::regStats()
 434 {
 435     Request temp_req((Addr) NULL, 4, 0);
 436     Packet::Command temp_cmd = Packet::ReadReq;
 437     Packet temp_pkt(&temp_req, temp_cmd, 0);  //@todo FIx command strings so this isn't neccessary
 438     temp_pkt.allocate(); //Temp allocate, all need data
 439
 440     using namespace Stats;
 441
 442     // Hit statistics
 443     for (int access_idx = 0; access_idx < NUM_MEM_CMDS; ++access_idx) {
 444         Packet::Command cmd = (Packet::Command)access_idx;
 445         const string &cstr = temp_pkt.cmdIdxToString(cmd);
 446
 447         hits[access_idx]
 448             .init(maxThreadsPerCPU)
 449             .name(name() + "." + cstr + "_hits")
 450             .desc("number of " + cstr + " hits")
 451             .flags(total | nozero | nonan)
 452             ;
 453     }
 454
 455     demandHits
 456         .name(name() + ".demand_hits")
 457         .desc("number of demand (read+write) hits")
 458         .flags(total)
 459         ;
 460     demandHits = hits[Packet::ReadReq] + hits[Packet::WriteReq];
 461
 462     overallHits
 463         .name(name() + ".overall_hits")
 464         .desc("number of overall hits")
 465         .flags(total)
 466         ;
 467     overallHits = demandHits + hits[Packet::SoftPFReq] + hits[Packet::HardPFReq]
 468         + hits[Packet::Writeback];
 469
 470     // Miss statistics
 471     for (int access_idx = 0; access_idx < NUM_MEM_CMDS; ++access_idx) {
 472         Packet::Command cmd = (Packet::Command)access_idx;
 473         const string &cstr = temp_pkt.cmdIdxToString(cmd);
 474
 475         misses[access_idx]
 476             .init(maxThreadsPerCPU)
 477             .name(name() + "." + cstr + "_misses")
 478             .desc("number of " + cstr + " misses")
 479             .flags(total | nozero | nonan)
 480             ;
 481     }
 482
 483     demandMisses
 484         .name(name() + ".demand_misses")
 485         .desc("number of demand (read+write) misses")
 486         .flags(total)
 487         ;
 488     demandMisses = misses[Packet::ReadReq] + misses[Packet::WriteReq];
 489
 490     overallMisses
 491         .name(name() + ".overall_misses")
 492         .desc("number of overall misses")
 493         .flags(total)
 494         ;
 495     overallMisses = demandMisses + misses[Packet::SoftPFReq] +
 496         misses[Packet::HardPFReq] + misses[Packet::Writeback];
 497
 498     // Miss latency statistics
 499     for (int access_idx = 0; access_idx < NUM_MEM_CMDS; ++access_idx) {
 500         Packet::Command cmd = (Packet::Command)access_idx;
 501         const string &cstr = temp_pkt.cmdIdxToString(cmd);
 502
 503         missLatency[access_idx]
 504             .init(maxThreadsPerCPU)
 505             .name(name() + "." + cstr + "_miss_latency")
 506             .desc("number of " + cstr + " miss cycles")
 507             .flags(total | nozero | nonan)
 508             ;
 509     }
 510
 511     demandMissLatency
 512         .name(name() + ".demand_miss_latency")
 513         .desc("number of demand (read+write) miss cycles")
 514         .flags(total)
 515         ;
 516     demandMissLatency = missLatency[Packet::ReadReq] + missLatency[Packet::WriteReq];
 517
 518     overallMissLatency
 519         .name(name() + ".overall_miss_latency")
 520         .desc("number of overall miss cycles")
 521         .flags(total)
 522         ;
 523     overallMissLatency = demandMissLatency + missLatency[Packet::SoftPFReq] +
 524         missLatency[Packet::HardPFReq];
 525
 526     // access formulas
 527     for (int access_idx = 0; access_idx < NUM_MEM_CMDS; ++access_idx) {
 528         Packet::Command cmd = (Packet::Command)access_idx;
 529         const string &cstr = temp_pkt.cmdIdxToString(cmd);
 530
 531         accesses[access_idx]
 532             .name(name() + "." + cstr + "_accesses")
 533             .desc("number of " + cstr + " accesses(hits+misses)")
 534             .flags(total | nozero | nonan)
 535             ;
 536
 537         accesses[access_idx] = hits[access_idx] + misses[access_idx];
 538     }
 539
 540     demandAccesses
 541         .name(name() + ".demand_accesses")
 542         .desc("number of demand (read+write) accesses")
 543         .flags(total)
 544         ;
 545     demandAccesses = demandHits + demandMisses;
 546
 547     overallAccesses
 548         .name(name() + ".overall_accesses")
 549         .desc("number of overall (read+write) accesses")
 550         .flags(total)
 551         ;
 552     overallAccesses = overallHits + overallMisses;
 553
 554     // miss rate formulas
 555     for (int access_idx = 0; access_idx < NUM_MEM_CMDS; ++access_idx) {
 556         Packet::Command cmd = (Packet::Command)access_idx;
 557         const string &cstr = temp_pkt.cmdIdxToString(cmd);
 558
 559         missRate[access_idx]
 560             .name(name() + "." + cstr + "_miss_rate")
 561             .desc("miss rate for " + cstr + " accesses")
 562             .flags(total | nozero | nonan)
 563             ;
 564
 565         missRate[access_idx] = misses[access_idx] / accesses[access_idx];
 566     }
 567
 568     demandMissRate
 569         .name(name() + ".demand_miss_rate")
 570         .desc("miss rate for demand accesses")
 571         .flags(total)
 572         ;
 573     demandMissRate = demandMisses / demandAccesses;
 574
 575     overallMissRate
 576         .name(name() + ".overall_miss_rate")
 577         .desc("miss rate for overall accesses")
 578         .flags(total)
 579         ;
 580     overallMissRate = overallMisses / overallAccesses;
 581
 582     // miss latency formulas
 583     for (int access_idx = 0; access_idx < NUM_MEM_CMDS; ++access_idx) {
 584         Packet::Command cmd = (Packet::Command)access_idx;
 585         const string &cstr = temp_pkt.cmdIdxToString(cmd);
 586
 587         avgMissLatency[access_idx]
 588             .name(name() + "." + cstr + "_avg_miss_latency")
 589             .desc("average " + cstr + " miss latency")
 590             .flags(total | nozero | nonan)
 591             ;
 592
 593         avgMissLatency[access_idx] =
 594             missLatency[access_idx] / misses[access_idx];
 595     }
 596
 597     demandAvgMissLatency
 598         .name(name() + ".demand_avg_miss_latency")
 599         .desc("average overall miss latency")
 600         .flags(total)
 601         ;
 602     demandAvgMissLatency = demandMissLatency / demandMisses;
 603
 604     overallAvgMissLatency
 605         .name(name() + ".overall_avg_miss_latency")
 606         .desc("average overall miss latency")
 607         .flags(total)
 608         ;
 609     overallAvgMissLatency = overallMissLatency / overallMisses;
 610
 611     blocked_cycles.init(NUM_BLOCKED_CAUSES);
 612     blocked_cycles
 613         .name(name() + ".blocked_cycles")
 614         .desc("number of cycles access was blocked")
 615         .subname(Blocked_NoMSHRs, "no_mshrs")
 616         .subname(Blocked_NoTargets, "no_targets")
 617         ;
 618
 619
 620     blocked_causes.init(NUM_BLOCKED_CAUSES);
 621     blocked_causes
 622         .name(name() + ".blocked")
 623         .desc("number of cycles access was blocked")
 624         .subname(Blocked_NoMSHRs, "no_mshrs")
 625         .subname(Blocked_NoTargets, "no_targets")
 626         ;
 627
 628     avg_blocked
 629         .name(name() + ".avg_blocked_cycles")
 630         .desc("average number of cycles each access was blocked")
 631         .subname(Blocked_NoMSHRs, "no_mshrs")
 632         .subname(Blocked_NoTargets, "no_targets")
 633         ;
 634
 635     avg_blocked = blocked_cycles / blocked_causes;
 636
 637     fastWrites
 638         .name(name() + ".fast_writes")
 639         .desc("number of fast writes performed")
 640         ;
 641
 642     cacheCopies
 643         .name(name() + ".cache_copies")
 644         .desc("number of cache copies performed")
 645         ;
 646
 647 }
 648
 649 unsigned int
 650 BaseCache::drain(Event *de)
 651 {
 652     // Set status
 653     if (!canDrain()) {
 654         drainEvent = de;
 655
 656         changeState(SimObject::Draining);
 657         return 1;
 658     }
 659
 660     changeState(SimObject::Drained);
 661     return 0;
 662 }