src/mem/cache/base_cache.cc

   1 /*
   2  * Copyright (c) 2003-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Erik Hallnor
  29  */
  30
  31 /**
  32  * @file
  33  * Definition of BaseCache functions.
  34  */
  35
  36 #include "cpu/base.hh"
  37 #include "cpu/smt.hh"
  38 #include "mem/cache/base_cache.hh"
  39 #include "mem/cache/miss/mshr.hh"
  40
  41 using namespace std;
  42
  43 BaseCache::CachePort::CachePort(const std::string &_name, BaseCache *_cache,
  44                                 bool _isCpuSide)
  45     : Port(_name), cache(_cache), isCpuSide(_isCpuSide)
  46 {
  47     blocked = false;
  48     waitingOnRetry = false;
  49     //Start ports at null if more than one is created we should panic
  50     //cpuSidePort = NULL;
  51     //memSidePort = NULL;
  52 }
  53
  54 void
  55 BaseCache::CachePort::recvStatusChange(Port::Status status)
  56 {
  57     cache->recvStatusChange(status, isCpuSide);
  58 }
  59
  60 void
  61 BaseCache::CachePort::getDeviceAddressRanges(AddrRangeList &resp,
  62                                        AddrRangeList &snoop)
  63 {
  64     cache->getAddressRanges(resp, snoop, isCpuSide);
  65 }
  66
  67 int
  68 BaseCache::CachePort::deviceBlockSize()
  69 {
  70     return cache->getBlockSize();
  71 }
  72
  73 bool
  74 BaseCache::CachePort::recvTiming(PacketPtr pkt)
  75 {
  76     if (isCpuSide
  77         && !pkt->req->isUncacheable()
  78         && pkt->isInvalidate()
  79         && !pkt->isRead() && !pkt->isWrite()) {
  80         //Upgrade or Invalidate
  81         //Look into what happens if two slave caches on bus
  82         DPRINTF(Cache, "%s %x ? blk_addr: %x\n", pkt->cmdString(),
  83                 pkt->getAddr() & (((ULL(1))<<48)-1),
  84                 pkt->getAddr() & ~((Addr)cache->blkSize - 1));
  85
  86         assert(!(pkt->flags & SATISFIED));
  87         pkt->flags |= SATISFIED;
  88         //Invalidates/Upgrades need no response if they get the bus
  89         return true;
  90     }
  91
  92     if (pkt->isRequest() && blocked)
  93     {
  94         DPRINTF(Cache,"Scheduling a retry while blocked\n");
  95         mustSendRetry = true;
  96         return false;
  97     }
  98     return cache->doTimingAccess(pkt, this, isCpuSide);
  99 }
 100
 101 Tick
 102 BaseCache::CachePort::recvAtomic(PacketPtr pkt)
 103 {
 104     return cache->doAtomicAccess(pkt, isCpuSide);
 105 }
 106
 107 void
 108 BaseCache::CachePort::recvFunctional(PacketPtr pkt)
 109 {
 110     //Check storage here first
 111     list<PacketPtr>::iterator i = drainList.begin();
 112     list<PacketPtr>::iterator end = drainList.end();
 113     for (; i != end; ++i) {
 114         PacketPtr target = *i;
 115         // If the target contains data, and it overlaps the
 116         // probed request, need to update data
 117         if (target->intersect(pkt)) {
 118             fixPacket(pkt, target);
 119         }
 120     }
 121     cache->doFunctionalAccess(pkt, isCpuSide);
 122 }
 123
 124 void
 125 BaseCache::CachePort::recvRetry()
 126 {
 127     PacketPtr pkt;
 128     assert(waitingOnRetry);
 129     if (!drainList.empty()) {
 130         DPRINTF(CachePort, "%s attempting to send a retry for response\n", name());
 131         //We have some responses to drain first
 132         if (sendTiming(drainList.front())) {
 133             DPRINTF(CachePort, "%s sucessful in sending a retry for response\n", name());
 134             drainList.pop_front();
 135             if (!drainList.empty() ||
 136                 !isCpuSide && cache->doMasterRequest() ||
 137                 isCpuSide && cache->doSlaveRequest()) {
 138
 139                 DPRINTF(CachePort, "%s has more responses/requests\n", name());
 140                 BaseCache::CacheEvent * reqCpu = new BaseCache::CacheEvent(this);
 141                 reqCpu->schedule(curTick + 1);
 142             }
 143             waitingOnRetry = false;
 144         }
 145     }
 146     else if (!isCpuSide)
 147     {
 148         DPRINTF(CachePort, "%s attempting to send a retry for MSHR\n", name());
 149         if (!cache->doMasterRequest()) {
 150             //This can happen if I am the owner of a block and see an upgrade
 151             //while the block was in my WB Buffers.  I just remove the
 152             //wb and de-assert the masterRequest
 153             waitingOnRetry = false;
 154             return;
 155         }
 156         pkt = cache->getPacket();
 157         MSHR* mshr = (MSHR*) pkt->senderState;
 158         //Copy the packet, it may be modified/destroyed elsewhere
 159         PacketPtr copyPkt = new Packet(*pkt);
 160         copyPkt->dataStatic<uint8_t>(pkt->getPtr<uint8_t>());
 161         mshr->pkt = copyPkt;
 162
 163         bool success = sendTiming(pkt);
 164         DPRINTF(Cache, "Address %x was %s in sending the timing request\n",
 165                 pkt->getAddr(), success ? "succesful" : "unsuccesful");
 166
 167         waitingOnRetry = !success;
 168         if (waitingOnRetry) {
 169             DPRINTF(CachePort, "%s now waiting on a retry\n", name());
 170         }
 171
 172         cache->sendResult(pkt, mshr, success);
 173
 174         if (success && cache->doMasterRequest())
 175         {
 176             DPRINTF(CachePort, "%s has more requests\n", name());
 177             //Still more to issue, rerequest in 1 cycle
 178             BaseCache::CacheEvent * reqCpu = new BaseCache::CacheEvent(this);
 179             reqCpu->schedule(curTick + 1);
 180         }
 181     }
 182     else
 183     {
 184         assert(cache->doSlaveRequest());
 185         //pkt = cache->getCoherencePacket();
 186         //We save the packet, no reordering on CSHRS
 187         pkt = cache->getCoherencePacket();
 188         MSHR* cshr = (MSHR*)pkt->senderState;
 189         bool success = sendTiming(pkt);
 190         cache->sendCoherenceResult(pkt, cshr, success);
 191         waitingOnRetry = !success;
 192         if (success && cache->doSlaveRequest())
 193         {
 194             DPRINTF(CachePort, "%s has more requests\n", name());
 195             //Still more to issue, rerequest in 1 cycle
 196             BaseCache::CacheEvent * reqCpu = new BaseCache::CacheEvent(this);
 197             reqCpu->schedule(curTick + 1);
 198         }
 199     }
 200     if (waitingOnRetry) DPRINTF(CachePort, "%s STILL Waiting on retry\n", name());
 201     else DPRINTF(CachePort, "%s no longer waiting on retry\n", name());
 202     return;
 203 }
 204 void
 205 BaseCache::CachePort::setBlocked()
 206 {
 207     assert(!blocked);
 208     DPRINTF(Cache, "Cache Blocking\n");
 209     blocked = true;
 210     //Clear the retry flag
 211     mustSendRetry = false;
 212 }
 213
 214 void
 215 BaseCache::CachePort::clearBlocked()
 216 {
 217     assert(blocked);
 218     DPRINTF(Cache, "Cache Unblocking\n");
 219     blocked = false;
 220     if (mustSendRetry)
 221     {
 222         DPRINTF(Cache, "Cache Sending Retry\n");
 223         mustSendRetry = false;
 224         sendRetry();
 225     }
 226 }
 227
 228 BaseCache::CacheEvent::CacheEvent(CachePort *_cachePort)
 229     : Event(&mainEventQueue, CPU_Tick_Pri), cachePort(_cachePort)
 230 {
 231     this->setFlags(AutoDelete);
 232     pkt = NULL;
 233 }
 234
 235 BaseCache::CacheEvent::CacheEvent(CachePort *_cachePort, PacketPtr _pkt)
 236     : Event(&mainEventQueue, CPU_Tick_Pri), cachePort(_cachePort), pkt(_pkt)
 237 {
 238     this->setFlags(AutoDelete);
 239 }
 240
 241 void
 242 BaseCache::CacheEvent::process()
 243 {
 244     if (!pkt)
 245     {
 246         if (cachePort->waitingOnRetry) return;
 247        //We have some responses to drain first
 248         if (!cachePort->drainList.empty()) {
 249             DPRINTF(CachePort, "%s trying to drain a response\n", cachePort->name());
 250             if (cachePort->sendTiming(cachePort->drainList.front())) {
 251                 DPRINTF(CachePort, "%s drains a response succesfully\n", cachePort->name());
 252                 cachePort->drainList.pop_front();
 253                 if (!cachePort->drainList.empty() ||
 254                     !cachePort->isCpuSide && cachePort->cache->doMasterRequest() ||
 255                     cachePort->isCpuSide && cachePort->cache->doSlaveRequest()) {
 256
 257                     DPRINTF(CachePort, "%s still has outstanding bus reqs\n", cachePort->name());
 258                     this->schedule(curTick + 1);
 259                 }
 260             }
 261             else {
 262                 cachePort->waitingOnRetry = true;
 263                 DPRINTF(CachePort, "%s now waiting on a retry\n", cachePort->name());
 264             }
 265         }
 266         else if (!cachePort->isCpuSide)
 267         {            //MSHR
 268             DPRINTF(CachePort, "%s trying to send a MSHR request\n", cachePort->name());
 269             if (!cachePort->cache->doMasterRequest()) {
 270                 //This can happen if I am the owner of a block and see an upgrade
 271                 //while the block was in my WB Buffers.  I just remove the
 272                 //wb and de-assert the masterRequest
 273                 return;
 274             }
 275
 276             pkt = cachePort->cache->getPacket();
 277             MSHR* mshr = (MSHR*) pkt->senderState;
 278             //Copy the packet, it may be modified/destroyed elsewhere
 279             PacketPtr copyPkt = new Packet(*pkt);
 280             copyPkt->dataStatic<uint8_t>(pkt->getPtr<uint8_t>());
 281             mshr->pkt = copyPkt;
 282
 283             bool success = cachePort->sendTiming(pkt);
 284             DPRINTF(Cache, "Address %x was %s in sending the timing request\n",
 285                     pkt->getAddr(), success ? "succesful" : "unsuccesful");
 286
 287             cachePort->waitingOnRetry = !success;
 288             if (cachePort->waitingOnRetry) {
 289                 DPRINTF(CachePort, "%s now waiting on a retry\n", cachePort->name());
 290             }
 291
 292             cachePort->cache->sendResult(pkt, mshr, success);
 293             if (success && cachePort->cache->doMasterRequest())
 294             {
 295                 DPRINTF(CachePort, "%s still more MSHR requests to send\n",
 296                         cachePort->name());
 297                 //Still more to issue, rerequest in 1 cycle
 298                 pkt = NULL;
 299                 this->schedule(curTick+1);
 300             }
 301         }
 302         else
 303         {
 304             //CSHR
 305             assert(cachePort->cache->doSlaveRequest());
 306             pkt = cachePort->cache->getCoherencePacket();
 307             MSHR* cshr = (MSHR*) pkt->senderState;
 308             bool success = cachePort->sendTiming(pkt);
 309             cachePort->cache->sendCoherenceResult(pkt, cshr, success);
 310             cachePort->waitingOnRetry = !success;
 311             if (cachePort->waitingOnRetry)
 312                 DPRINTF(CachePort, "%s now waiting on a retry\n", cachePort->name());
 313             if (success && cachePort->cache->doSlaveRequest())
 314             {
 315                 DPRINTF(CachePort, "%s still more CSHR requests to send\n",
 316                         cachePort->name());
 317                 //Still more to issue, rerequest in 1 cycle
 318                 pkt = NULL;
 319                 this->schedule(curTick+1);
 320             }
 321         }
 322         return;
 323     }
 324     //Response
 325     //Know the packet to send
 326     if (pkt->flags & NACKED_LINE)
 327         pkt->result = Packet::Nacked;
 328     else
 329         pkt->result = Packet::Success;
 330     pkt->makeTimingResponse();
 331     DPRINTF(CachePort, "%s attempting to send a response\n", cachePort->name());
 332     if (!cachePort->drainList.empty() || cachePort->waitingOnRetry) {
 333         //Already have a list, just append
 334         cachePort->drainList.push_back(pkt);
 335         DPRINTF(CachePort, "%s appending response onto drain list\n", cachePort->name());
 336     }
 337     else if (!cachePort->sendTiming(pkt)) {
 338         //It failed, save it to list of drain events
 339         DPRINTF(CachePort, "%s now waiting for a retry\n", cachePort->name());
 340         cachePort->drainList.push_back(pkt);
 341         cachePort->waitingOnRetry = true;
 342     }
 343 }
 344
 345 const char *
 346 BaseCache::CacheEvent::description()
 347 {
 348     return "timing event\n";
 349 }
 350
 351 Port*
 352 BaseCache::getPort(const std::string &if_name, int idx)
 353 {
 354     if (if_name == "")
 355     {
 356         if(cpuSidePort == NULL)
 357             cpuSidePort = new CachePort(name() + "-cpu_side_port", this, true);
 358         return cpuSidePort;
 359     }
 360     else if (if_name == "functional")
 361     {
 362         if(cpuSidePort == NULL)
 363             cpuSidePort = new CachePort(name() + "-cpu_side_port", this, true);
 364         return cpuSidePort;
 365     }
 366     else if (if_name == "cpu_side")
 367     {
 368         if(cpuSidePort == NULL)
 369             cpuSidePort = new CachePort(name() + "-cpu_side_port", this, true);
 370         return cpuSidePort;
 371     }
 372     else if (if_name == "mem_side")
 373     {
 374         if (memSidePort != NULL)
 375             panic("Already have a mem side for this cache\n");
 376         memSidePort = new CachePort(name() + "-mem_side_port", this, false);
 377         return memSidePort;
 378     }
 379     else panic("Port name %s unrecognized\n", if_name);
 380 }
 381
 382 void
 383 BaseCache::init()
 384 {
 385     if (!cpuSidePort || !memSidePort)
 386         panic("Cache not hooked up on both sides\n");
 387     cpuSidePort->sendStatusChange(Port::RangeChange);
 388 }
 389
 390 void
 391 BaseCache::regStats()
 392 {
 393     Request temp_req((Addr) NULL, 4, 0);
 394     Packet::Command temp_cmd = Packet::ReadReq;
 395     Packet temp_pkt(&temp_req, temp_cmd, 0);  //@todo FIx command strings so this isn't neccessary
 396     temp_pkt.allocate(); //Temp allocate, all need data
 397
 398     using namespace Stats;
 399
 400     // Hit statistics
 401     for (int access_idx = 0; access_idx < NUM_MEM_CMDS; ++access_idx) {
 402         Packet::Command cmd = (Packet::Command)access_idx;
 403         const string &cstr = temp_pkt.cmdIdxToString(cmd);
 404
 405         hits[access_idx]
 406             .init(maxThreadsPerCPU)
 407             .name(name() + "." + cstr + "_hits")
 408             .desc("number of " + cstr + " hits")
 409             .flags(total | nozero | nonan)
 410             ;
 411     }
 412
 413     demandHits
 414         .name(name() + ".demand_hits")
 415         .desc("number of demand (read+write) hits")
 416         .flags(total)
 417         ;
 418     demandHits = hits[Packet::ReadReq] + hits[Packet::WriteReq];
 419
 420     overallHits
 421         .name(name() + ".overall_hits")
 422         .desc("number of overall hits")
 423         .flags(total)
 424         ;
 425     overallHits = demandHits + hits[Packet::SoftPFReq] + hits[Packet::HardPFReq]
 426         + hits[Packet::Writeback];
 427
 428     // Miss statistics
 429     for (int access_idx = 0; access_idx < NUM_MEM_CMDS; ++access_idx) {
 430         Packet::Command cmd = (Packet::Command)access_idx;
 431         const string &cstr = temp_pkt.cmdIdxToString(cmd);
 432
 433         misses[access_idx]
 434             .init(maxThreadsPerCPU)
 435             .name(name() + "." + cstr + "_misses")
 436             .desc("number of " + cstr + " misses")
 437             .flags(total | nozero | nonan)
 438             ;
 439     }
 440
 441     demandMisses
 442         .name(name() + ".demand_misses")
 443         .desc("number of demand (read+write) misses")
 444         .flags(total)
 445         ;
 446     demandMisses = misses[Packet::ReadReq] + misses[Packet::WriteReq];
 447
 448     overallMisses
 449         .name(name() + ".overall_misses")
 450         .desc("number of overall misses")
 451         .flags(total)
 452         ;
 453     overallMisses = demandMisses + misses[Packet::SoftPFReq] +
 454         misses[Packet::HardPFReq] + misses[Packet::Writeback];
 455
 456     // Miss latency statistics
 457     for (int access_idx = 0; access_idx < NUM_MEM_CMDS; ++access_idx) {
 458         Packet::Command cmd = (Packet::Command)access_idx;
 459         const string &cstr = temp_pkt.cmdIdxToString(cmd);
 460
 461         missLatency[access_idx]
 462             .init(maxThreadsPerCPU)
 463             .name(name() + "." + cstr + "_miss_latency")
 464             .desc("number of " + cstr + " miss cycles")
 465             .flags(total | nozero | nonan)
 466             ;
 467     }
 468
 469     demandMissLatency
 470         .name(name() + ".demand_miss_latency")
 471         .desc("number of demand (read+write) miss cycles")
 472         .flags(total)
 473         ;
 474     demandMissLatency = missLatency[Packet::ReadReq] + missLatency[Packet::WriteReq];
 475
 476     overallMissLatency
 477         .name(name() + ".overall_miss_latency")
 478         .desc("number of overall miss cycles")
 479         .flags(total)
 480         ;
 481     overallMissLatency = demandMissLatency + missLatency[Packet::SoftPFReq] +
 482         missLatency[Packet::HardPFReq];
 483
 484     // access formulas
 485     for (int access_idx = 0; access_idx < NUM_MEM_CMDS; ++access_idx) {
 486         Packet::Command cmd = (Packet::Command)access_idx;
 487         const string &cstr = temp_pkt.cmdIdxToString(cmd);
 488
 489         accesses[access_idx]
 490             .name(name() + "." + cstr + "_accesses")
 491             .desc("number of " + cstr + " accesses(hits+misses)")
 492             .flags(total | nozero | nonan)
 493             ;
 494
 495         accesses[access_idx] = hits[access_idx] + misses[access_idx];
 496     }
 497
 498     demandAccesses
 499         .name(name() + ".demand_accesses")
 500         .desc("number of demand (read+write) accesses")
 501         .flags(total)
 502         ;
 503     demandAccesses = demandHits + demandMisses;
 504
 505     overallAccesses
 506         .name(name() + ".overall_accesses")
 507         .desc("number of overall (read+write) accesses")
 508         .flags(total)
 509         ;
 510     overallAccesses = overallHits + overallMisses;
 511
 512     // miss rate formulas
 513     for (int access_idx = 0; access_idx < NUM_MEM_CMDS; ++access_idx) {
 514         Packet::Command cmd = (Packet::Command)access_idx;
 515         const string &cstr = temp_pkt.cmdIdxToString(cmd);
 516
 517         missRate[access_idx]
 518             .name(name() + "." + cstr + "_miss_rate")
 519             .desc("miss rate for " + cstr + " accesses")
 520             .flags(total | nozero | nonan)
 521             ;
 522
 523         missRate[access_idx] = misses[access_idx] / accesses[access_idx];
 524     }
 525
 526     demandMissRate
 527         .name(name() + ".demand_miss_rate")
 528         .desc("miss rate for demand accesses")
 529         .flags(total)
 530         ;
 531     demandMissRate = demandMisses / demandAccesses;
 532
 533     overallMissRate
 534         .name(name() + ".overall_miss_rate")
 535         .desc("miss rate for overall accesses")
 536         .flags(total)
 537         ;
 538     overallMissRate = overallMisses / overallAccesses;
 539
 540     // miss latency formulas
 541     for (int access_idx = 0; access_idx < NUM_MEM_CMDS; ++access_idx) {
 542         Packet::Command cmd = (Packet::Command)access_idx;
 543         const string &cstr = temp_pkt.cmdIdxToString(cmd);
 544
 545         avgMissLatency[access_idx]
 546             .name(name() + "." + cstr + "_avg_miss_latency")
 547             .desc("average " + cstr + " miss latency")
 548             .flags(total | nozero | nonan)
 549             ;
 550
 551         avgMissLatency[access_idx] =
 552             missLatency[access_idx] / misses[access_idx];
 553     }
 554
 555     demandAvgMissLatency
 556         .name(name() + ".demand_avg_miss_latency")
 557         .desc("average overall miss latency")
 558         .flags(total)
 559         ;
 560     demandAvgMissLatency = demandMissLatency / demandMisses;
 561
 562     overallAvgMissLatency
 563         .name(name() + ".overall_avg_miss_latency")
 564         .desc("average overall miss latency")
 565         .flags(total)
 566         ;
 567     overallAvgMissLatency = overallMissLatency / overallMisses;
 568
 569     blocked_cycles.init(NUM_BLOCKED_CAUSES);
 570     blocked_cycles
 571         .name(name() + ".blocked_cycles")
 572         .desc("number of cycles access was blocked")
 573         .subname(Blocked_NoMSHRs, "no_mshrs")
 574         .subname(Blocked_NoTargets, "no_targets")
 575         ;
 576
 577
 578     blocked_causes.init(NUM_BLOCKED_CAUSES);
 579     blocked_causes
 580         .name(name() + ".blocked")
 581         .desc("number of cycles access was blocked")
 582         .subname(Blocked_NoMSHRs, "no_mshrs")
 583         .subname(Blocked_NoTargets, "no_targets")
 584         ;
 585
 586     avg_blocked
 587         .name(name() + ".avg_blocked_cycles")
 588         .desc("average number of cycles each access was blocked")
 589         .subname(Blocked_NoMSHRs, "no_mshrs")
 590         .subname(Blocked_NoTargets, "no_targets")
 591         ;
 592
 593     avg_blocked = blocked_cycles / blocked_causes;
 594
 595     fastWrites
 596         .name(name() + ".fast_writes")
 597         .desc("number of fast writes performed")
 598         ;
 599
 600     cacheCopies
 601         .name(name() + ".cache_copies")
 602         .desc("number of cache copies performed")
 603         ;
 604
 605 }