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28 * Authors: Erik Hallnor
33 * Declares a basic cache interface BaseCache.
36 #ifndef __BASE_CACHE_HH__
37 #define __BASE_CACHE_HH__
44 #include "base/misc.hh"
45 #include "base/statistics.hh"
46 #include "base/trace.hh"
47 #include "mem/mem_object.hh"
48 #include "mem/packet.hh"
49 #include "mem/port.hh"
50 #include "mem/request.hh"
51 #include "sim/eventq.hh"
54 * Reasons for Caches to be Blocked.
66 * Reasons for cache to request a bus.
76 * A basic cache interface. Implements some common functions for speed.
78 class BaseCache : public MemObject
80 class CachePort : public Port
85 CachePort(const std::string &_name, BaseCache *_cache, bool _isCpuSide);
88 virtual bool recvTiming(Packet *pkt);
90 virtual Tick recvAtomic(Packet *pkt);
92 virtual void recvFunctional(Packet *pkt);
94 virtual void recvStatusChange(Status status);
96 virtual void getDeviceAddressRanges(AddrRangeList &resp,
97 AddrRangeList &snoop);
99 virtual int deviceBlockSize();
101 virtual void recvRetry();
115 struct CacheEvent : public Event
117 CachePort *cachePort;
120 CacheEvent(CachePort *_cachePort);
121 CacheEvent(CachePort *_cachePort, Packet *_pkt);
123 const char *description();
127 CachePort *cpuSidePort;
128 CachePort *memSidePort;
130 bool snoopRangesSent;
133 virtual Port *getPort(const std::string &if_name, int idx = -1);
136 //To be defined in cache_impl.hh not in base class
137 virtual bool doTimingAccess(Packet *pkt, CachePort *cachePort, bool isCpuSide)
139 fatal("No implementation");
142 virtual Tick doAtomicAccess(Packet *pkt, bool isCpuSide)
144 fatal("No implementation");
147 virtual void doFunctionalAccess(Packet *pkt, bool isCpuSide)
149 fatal("No implementation");
152 void recvStatusChange(Port::Status status, bool isCpuSide)
154 if (status == Port::RangeChange){
156 cpuSidePort->sendStatusChange(Port::RangeChange);
157 if (topLevelCache && !snoopRangesSent) {
158 snoopRangesSent = true;
159 memSidePort->sendStatusChange(Port::RangeChange);
163 memSidePort->sendStatusChange(Port::RangeChange);
166 else if (status == Port::SnoopSquash) {
172 virtual Packet *getPacket()
174 fatal("No implementation");
177 virtual Packet *getCoherencePacket()
179 fatal("No implementation");
182 virtual void sendResult(Packet* &pkt, bool success)
185 fatal("No implementation");
189 * Bit vector of the blocking reasons for the access path.
195 * Bit vector for the blocking reasons for the snoop path.
198 uint8_t blockedSnoop;
201 * Bit vector for the outstanding requests for the master interface.
203 uint8_t masterRequests;
206 * Bit vector for the outstanding requests for the slave interface.
208 uint8_t slaveRequests;
212 /** True if this cache is connected to the CPU. */
216 /** True if we are now in phase 2 of the snoop process. */
219 /** Stores time the cache blocked for statistics. */
222 /** Block size of this cache */
225 /** The number of misses to trigger an exit event. */
231 * @addtogroup CacheStatistics
235 /** Number of hits per thread for each type of command. @sa Packet::Command */
236 Stats::Vector<> hits[NUM_MEM_CMDS];
237 /** Number of hits for demand accesses. */
238 Stats::Formula demandHits;
239 /** Number of hit for all accesses. */
240 Stats::Formula overallHits;
242 /** Number of misses per thread for each type of command. @sa Packet::Command */
243 Stats::Vector<> misses[NUM_MEM_CMDS];
244 /** Number of misses for demand accesses. */
245 Stats::Formula demandMisses;
246 /** Number of misses for all accesses. */
247 Stats::Formula overallMisses;
250 * Total number of cycles per thread/command spent waiting for a miss.
251 * Used to calculate the average miss latency.
253 Stats::Vector<> missLatency[NUM_MEM_CMDS];
254 /** Total number of cycles spent waiting for demand misses. */
255 Stats::Formula demandMissLatency;
256 /** Total number of cycles spent waiting for all misses. */
257 Stats::Formula overallMissLatency;
259 /** The number of accesses per command and thread. */
260 Stats::Formula accesses[NUM_MEM_CMDS];
261 /** The number of demand accesses. */
262 Stats::Formula demandAccesses;
263 /** The number of overall accesses. */
264 Stats::Formula overallAccesses;
266 /** The miss rate per command and thread. */
267 Stats::Formula missRate[NUM_MEM_CMDS];
268 /** The miss rate of all demand accesses. */
269 Stats::Formula demandMissRate;
270 /** The miss rate for all accesses. */
271 Stats::Formula overallMissRate;
273 /** The average miss latency per command and thread. */
274 Stats::Formula avgMissLatency[NUM_MEM_CMDS];
275 /** The average miss latency for demand misses. */
276 Stats::Formula demandAvgMissLatency;
277 /** The average miss latency for all misses. */
278 Stats::Formula overallAvgMissLatency;
280 /** The total number of cycles blocked for each blocked cause. */
281 Stats::Vector<> blocked_cycles;
282 /** The number of times this cache blocked for each blocked cause. */
283 Stats::Vector<> blocked_causes;
285 /** The average number of cycles blocked for each blocked cause. */
286 Stats::Formula avg_blocked;
288 /** The number of fast writes (WH64) performed. */
289 Stats::Scalar<> fastWrites;
291 /** The number of cache copies performed. */
292 Stats::Scalar<> cacheCopies;
299 * Register stats for this object.
301 virtual void regStats();
308 /** List of address ranges of this cache. */
309 std::vector<Range<Addr> > addrRange;
310 /** The hit latency for this cache. */
312 /** The block size of this cache. */
315 * The maximum number of misses this cache should handle before
316 * ending the simulation.
321 * Construct an instance of this parameter class.
323 Params(std::vector<Range<Addr> > addr_range,
324 int hit_latency, int _blkSize, Counter max_misses)
325 : addrRange(addr_range), hitLatency(hit_latency), blkSize(_blkSize),
326 maxMisses(max_misses)
332 * Create and initialize a basic cache object.
333 * @param name The name of this cache.
334 * @param hier_params Pointer to the HierParams object for this hierarchy
336 * @param params The parameter object for this BaseCache.
338 BaseCache(const std::string &name, Params ¶ms)
339 : MemObject(name), blocked(0), blockedSnoop(0), masterRequests(0),
340 slaveRequests(0), topLevelCache(false), blkSize(params.blkSize),
341 missCount(params.maxMisses)
343 //Start ports at null if more than one is created we should panic
346 snoopRangesSent = false;
352 * Query block size of a cache.
353 * @return The block size
355 int getBlockSize() const
361 * Returns true if this cache is connect to the CPU.
362 * @return True if this is a L1 cache.
366 return topLevelCache;
370 * Returns true if the cache is blocked for accesses.
378 * Returns true if the cache is blocked for snoops.
380 bool isBlockedForSnoop()
382 return blockedSnoop != 0;
386 * Marks the access path of the cache as blocked for the given cause. This
387 * also sets the blocked flag in the slave interface.
388 * @param cause The reason for the cache blocking.
390 void setBlocked(BlockedCause cause)
392 uint8_t flag = 1 << cause;
394 blocked_causes[cause]++;
395 blockedCycle = curTick;
398 DPRINTF(Cache,"Blocking for cause %s\n", cause);
399 cpuSidePort->setBlocked();
403 * Marks the snoop path of the cache as blocked for the given cause. This
404 * also sets the blocked flag in the master interface.
405 * @param cause The reason to block the snoop path.
407 void setBlockedForSnoop(BlockedCause cause)
409 uint8_t flag = 1 << cause;
410 blockedSnoop |= flag;
411 memSidePort->setBlocked();
415 * Marks the cache as unblocked for the given cause. This also clears the
416 * blocked flags in the appropriate interfaces.
417 * @param cause The newly unblocked cause.
418 * @warning Calling this function can cause a blocked request on the bus to
419 * access the cache. The cache must be in a state to handle that request.
421 void clearBlocked(BlockedCause cause)
423 uint8_t flag = 1 << cause;
424 DPRINTF(Cache,"Unblocking for cause %s, causes left=%i\n",
430 blocked_cycles[cause] += curTick - blockedCycle;
431 DPRINTF(Cache,"Unblocking from all causes\n");
432 cpuSidePort->clearBlocked();
435 if (blockedSnoop & flag)
437 blockedSnoop &= ~flag;
438 if (!isBlockedForSnoop()) {
439 memSidePort->clearBlocked();
445 * True if the master bus should be requested.
446 * @return True if there are outstanding requests for the master bus.
448 bool doMasterRequest()
450 return masterRequests != 0;
454 * Request the master bus for the given cause and time.
455 * @param cause The reason for the request.
456 * @param time The time to make the request.
458 void setMasterRequest(RequestCause cause, Tick time)
460 if (!doMasterRequest())
462 BaseCache::CacheEvent * reqCpu = new BaseCache::CacheEvent(memSidePort);
463 reqCpu->schedule(time);
465 uint8_t flag = 1<<cause;
466 masterRequests |= flag;
470 * Clear the master bus request for the given cause.
471 * @param cause The request reason to clear.
473 void clearMasterRequest(RequestCause cause)
475 uint8_t flag = 1<<cause;
476 masterRequests &= ~flag;
480 * Return true if the slave bus should be requested.
481 * @return True if there are outstanding requests for the slave bus.
483 bool doSlaveRequest()
485 return slaveRequests != 0;
489 * Request the slave bus for the given reason and time.
490 * @param cause The reason for the request.
491 * @param time The time to make the request.
493 void setSlaveRequest(RequestCause cause, Tick time)
495 uint8_t flag = 1<<cause;
496 slaveRequests |= flag;
497 assert("Implement\n" && 0);
498 // si->pktuest(time);
502 * Clear the slave bus request for the given reason.
503 * @param cause The request reason to clear.
505 void clearSlaveRequest(RequestCause cause)
507 uint8_t flag = 1<<cause;
508 slaveRequests &= ~flag;
512 * Send a response to the slave interface.
513 * @param pkt The request being responded to.
514 * @param time The time the response is ready.
516 void respond(Packet *pkt, Tick time)
518 pkt->makeTimingResponse();
519 pkt->result = Packet::Success;
520 CacheEvent *reqCpu = new CacheEvent(cpuSidePort, pkt);
521 reqCpu->schedule(time);
525 * Send a reponse to the slave interface and calculate miss latency.
526 * @param pkt The request to respond to.
527 * @param time The time the response is ready.
529 void respondToMiss(Packet *pkt, Tick time)
531 if (!pkt->req->isUncacheable()) {
532 missLatency[pkt->cmdToIndex()][pkt->req->getThreadNum()] += time - pkt->time;
534 CacheEvent *reqCpu = new CacheEvent(cpuSidePort, pkt);
535 reqCpu->schedule(time);
539 * Suppliess the data if cache to cache transfers are enabled.
540 * @param pkt The bus transaction to fulfill.
542 void respondToSnoop(Packet *pkt, Tick time)
544 // assert("Implement\n" && 0);
545 // mi->respond(pkt,curTick + hitLatency);
546 CacheEvent *reqMem = new CacheEvent(memSidePort, pkt);
547 reqMem->schedule(time);
551 * Notification from master interface that a address range changed. Nothing
554 void rangeChange() {}
556 void getAddressRanges(AddrRangeList &resp, AddrRangeList &snoop, bool isCpuSide)
561 memSidePort->getPeerAddressRanges(resp, dummy);
565 //This is where snoops get updated
569 cpuSidePort->getPeerAddressRanges(dummy, snoop);
573 snoop.push_back(RangeSize(0,-1));
581 #endif //__BASE_CACHE_HH__