src/mem/cache/base_cache.hh

   1 /*
   2  * Copyright (c) 2003-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Erik Hallnor
  29  */
  30
  31 /**
  32  * @file
  33  * Declares a basic cache interface BaseCache.
  34  */
  35
  36 #ifndef __BASE_CACHE_HH__
  37 #define __BASE_CACHE_HH__
  38
  39 #include <vector>
  40 #include <string>
  41 #include <list>
  42 #include <inttypes.h>
  43
  44 #include "base/misc.hh"
  45 #include "base/statistics.hh"
  46 #include "base/trace.hh"
  47 #include "mem/mem_object.hh"
  48 #include "mem/packet.hh"
  49 #include "mem/port.hh"
  50 #include "mem/request.hh"
  51 #include "sim/eventq.hh"
  52
  53 /**
  54  * Reasons for Caches to be Blocked.
  55  */
  56 enum BlockedCause{
  57     Blocked_NoMSHRs,
  58     Blocked_NoTargets,
  59     Blocked_NoWBBuffers,
  60     Blocked_Coherence,
  61     NUM_BLOCKED_CAUSES
  62 };
  63
  64 /**
  65  * Reasons for cache to request a bus.
  66  */
  67 enum RequestCause{
  68     Request_MSHR,
  69     Request_WB,
  70     Request_Coherence,
  71     Request_PF
  72 };
  73
  74 class MSHR;
  75 /**
  76  * A basic cache interface. Implements some common functions for speed.
  77  */
  78 class BaseCache : public MemObject
  79 {
  80     class CachePort : public Port
  81     {
  82       public:
  83         BaseCache *cache;
  84
  85         CachePort(const std::string &_name, BaseCache *_cache, bool _isCpuSide);
  86
  87       protected:
  88         virtual bool recvTiming(Packet *pkt);
  89
  90         virtual Tick recvAtomic(Packet *pkt);
  91
  92         virtual void recvFunctional(Packet *pkt);
  93
  94         virtual void recvStatusChange(Status status);
  95
  96         virtual void getDeviceAddressRanges(AddrRangeList &resp,
  97                                             AddrRangeList &snoop);
  98
  99         virtual int deviceBlockSize();
 100
 101         virtual void recvRetry();
 102
 103       public:
 104         void setBlocked();
 105
 106         void clearBlocked();
 107
 108         bool blocked;
 109
 110         bool mustSendRetry;
 111
 112         bool isCpuSide;
 113
 114         bool waitingOnRetry;
 115
 116         std::list<Packet *> drainList;
 117
 118     };
 119
 120     struct CacheEvent : public Event
 121     {
 122         CachePort *cachePort;
 123         Packet *pkt;
 124
 125         CacheEvent(CachePort *_cachePort);
 126         CacheEvent(CachePort *_cachePort, Packet *_pkt);
 127         void process();
 128         const char *description();
 129     };
 130
 131   protected:
 132     CachePort *cpuSidePort;
 133     CachePort *memSidePort;
 134
 135     bool snoopRangesSent;
 136
 137   public:
 138     virtual Port *getPort(const std::string &if_name, int idx = -1);
 139
 140   private:
 141     //To be defined in cache_impl.hh not in base class
 142     virtual bool doTimingAccess(Packet *pkt, CachePort *cachePort, bool isCpuSide)
 143     {
 144         fatal("No implementation");
 145     }
 146
 147     virtual Tick doAtomicAccess(Packet *pkt, bool isCpuSide)
 148     {
 149         fatal("No implementation");
 150     }
 151
 152     virtual void doFunctionalAccess(Packet *pkt, bool isCpuSide)
 153     {
 154         fatal("No implementation");
 155     }
 156
 157     void recvStatusChange(Port::Status status, bool isCpuSide)
 158     {
 159         if (status == Port::RangeChange){
 160             if (!isCpuSide) {
 161                 cpuSidePort->sendStatusChange(Port::RangeChange);
 162                 if (!snoopRangesSent) {
 163                     snoopRangesSent = true;
 164                     memSidePort->sendStatusChange(Port::RangeChange);
 165                 }
 166             }
 167             else {
 168                 memSidePort->sendStatusChange(Port::RangeChange);
 169             }
 170         }
 171     }
 172
 173     virtual Packet *getPacket()
 174     {
 175         fatal("No implementation");
 176     }
 177
 178     virtual Packet *getCoherencePacket()
 179     {
 180         fatal("No implementation");
 181     }
 182
 183     virtual void sendResult(Packet* &pkt, MSHR* mshr, bool success)
 184     {
 185
 186         fatal("No implementation");
 187     }
 188
 189     virtual void sendCoherenceResult(Packet* &pkt, MSHR* mshr, bool success)
 190     {
 191
 192         fatal("No implementation");
 193     }
 194
 195     /**
 196      * Bit vector of the blocking reasons for the access path.
 197      * @sa #BlockedCause
 198      */
 199     uint8_t blocked;
 200
 201     /**
 202      * Bit vector for the blocking reasons for the snoop path.
 203      * @sa #BlockedCause
 204      */
 205     uint8_t blockedSnoop;
 206
 207     /**
 208      * Bit vector for the outstanding requests for the master interface.
 209      */
 210     uint8_t masterRequests;
 211
 212     /**
 213      * Bit vector for the outstanding requests for the slave interface.
 214      */
 215     uint8_t slaveRequests;
 216
 217   protected:
 218
 219     /** Stores time the cache blocked for statistics. */
 220     Tick blockedCycle;
 221
 222     /** Block size of this cache */
 223     const int blkSize;
 224
 225     /** The number of misses to trigger an exit event. */
 226     Counter missCount;
 227
 228   public:
 229     // Statistics
 230     /**
 231      * @addtogroup CacheStatistics
 232      * @{
 233      */
 234
 235     /** Number of hits per thread for each type of command. @sa Packet::Command */
 236     Stats::Vector<> hits[NUM_MEM_CMDS];
 237     /** Number of hits for demand accesses. */
 238     Stats::Formula demandHits;
 239     /** Number of hit for all accesses. */
 240     Stats::Formula overallHits;
 241
 242     /** Number of misses per thread for each type of command. @sa Packet::Command */
 243     Stats::Vector<> misses[NUM_MEM_CMDS];
 244     /** Number of misses for demand accesses. */
 245     Stats::Formula demandMisses;
 246     /** Number of misses for all accesses. */
 247     Stats::Formula overallMisses;
 248
 249     /**
 250      * Total number of cycles per thread/command spent waiting for a miss.
 251      * Used to calculate the average miss latency.
 252      */
 253     Stats::Vector<> missLatency[NUM_MEM_CMDS];
 254     /** Total number of cycles spent waiting for demand misses. */
 255     Stats::Formula demandMissLatency;
 256     /** Total number of cycles spent waiting for all misses. */
 257     Stats::Formula overallMissLatency;
 258
 259     /** The number of accesses per command and thread. */
 260     Stats::Formula accesses[NUM_MEM_CMDS];
 261     /** The number of demand accesses. */
 262     Stats::Formula demandAccesses;
 263     /** The number of overall accesses. */
 264     Stats::Formula overallAccesses;
 265
 266     /** The miss rate per command and thread. */
 267     Stats::Formula missRate[NUM_MEM_CMDS];
 268     /** The miss rate of all demand accesses. */
 269     Stats::Formula demandMissRate;
 270     /** The miss rate for all accesses. */
 271     Stats::Formula overallMissRate;
 272
 273     /** The average miss latency per command and thread. */
 274     Stats::Formula avgMissLatency[NUM_MEM_CMDS];
 275     /** The average miss latency for demand misses. */
 276     Stats::Formula demandAvgMissLatency;
 277     /** The average miss latency for all misses. */
 278     Stats::Formula overallAvgMissLatency;
 279
 280     /** The total number of cycles blocked for each blocked cause. */
 281     Stats::Vector<> blocked_cycles;
 282     /** The number of times this cache blocked for each blocked cause. */
 283     Stats::Vector<> blocked_causes;
 284
 285     /** The average number of cycles blocked for each blocked cause. */
 286     Stats::Formula avg_blocked;
 287
 288     /** The number of fast writes (WH64) performed. */
 289     Stats::Scalar<> fastWrites;
 290
 291     /** The number of cache copies performed. */
 292     Stats::Scalar<> cacheCopies;
 293
 294     /**
 295      * @}
 296      */
 297
 298     /**
 299      * Register stats for this object.
 300      */
 301     virtual void regStats();
 302
 303   public:
 304
 305     class Params
 306     {
 307       public:
 308         /** List of address ranges of this cache. */
 309         std::vector<Range<Addr> > addrRange;
 310         /** The hit latency for this cache. */
 311         int hitLatency;
 312         /** The block size of this cache. */
 313         int blkSize;
 314         /**
 315          * The maximum number of misses this cache should handle before
 316          * ending the simulation.
 317          */
 318         Counter maxMisses;
 319
 320         /**
 321          * Construct an instance of this parameter class.
 322          */
 323         Params(std::vector<Range<Addr> > addr_range,
 324                int hit_latency, int _blkSize, Counter max_misses)
 325             : addrRange(addr_range), hitLatency(hit_latency), blkSize(_blkSize),
 326               maxMisses(max_misses)
 327         {
 328         }
 329     };
 330
 331     /**
 332      * Create and initialize a basic cache object.
 333      * @param name The name of this cache.
 334      * @param hier_params Pointer to the HierParams object for this hierarchy
 335      * of this cache.
 336      * @param params The parameter object for this BaseCache.
 337      */
 338     BaseCache(const std::string &name, Params &params)
 339         : MemObject(name), blocked(0), blockedSnoop(0), masterRequests(0),
 340           slaveRequests(0), blkSize(params.blkSize),
 341           missCount(params.maxMisses)
 342     {
 343         //Start ports at null if more than one is created we should panic
 344         cpuSidePort = NULL;
 345         memSidePort = NULL;
 346         snoopRangesSent = false;
 347     }
 348
 349     virtual void init();
 350
 351     /**
 352      * Query block size of a cache.
 353      * @return  The block size
 354      */
 355     int getBlockSize() const
 356     {
 357         return blkSize;
 358     }
 359
 360     /**
 361      * Returns true if the cache is blocked for accesses.
 362      */
 363     bool isBlocked()
 364     {
 365         return blocked != 0;
 366     }
 367
 368     /**
 369      * Returns true if the cache is blocked for snoops.
 370      */
 371     bool isBlockedForSnoop()
 372     {
 373         return blockedSnoop != 0;
 374     }
 375
 376     /**
 377      * Marks the access path of the cache as blocked for the given cause. This
 378      * also sets the blocked flag in the slave interface.
 379      * @param cause The reason for the cache blocking.
 380      */
 381     void setBlocked(BlockedCause cause)
 382     {
 383         uint8_t flag = 1 << cause;
 384         if (blocked == 0) {
 385             blocked_causes[cause]++;
 386             blockedCycle = curTick;
 387         }
 388         int old_state = blocked;
 389         if (!(blocked & flag)) {
 390             //Wasn't already blocked for this cause
 391             blocked |= flag;
 392             DPRINTF(Cache,"Blocking for cause %s\n", cause);
 393             if (!old_state)
 394                 cpuSidePort->setBlocked();
 395         }
 396     }
 397
 398     /**
 399      * Marks the snoop path of the cache as blocked for the given cause. This
 400      * also sets the blocked flag in the master interface.
 401      * @param cause The reason to block the snoop path.
 402      */
 403     void setBlockedForSnoop(BlockedCause cause)
 404     {
 405         uint8_t flag = 1 << cause;
 406         uint8_t old_state = blockedSnoop;
 407         if (!(blockedSnoop & flag)) {
 408             //Wasn't already blocked for this cause
 409             blockedSnoop |= flag;
 410             if (!old_state)
 411                 memSidePort->setBlocked();
 412         }
 413     }
 414
 415     /**
 416      * Marks the cache as unblocked for the given cause. This also clears the
 417      * blocked flags in the appropriate interfaces.
 418      * @param cause The newly unblocked cause.
 419      * @warning Calling this function can cause a blocked request on the bus to
 420      * access the cache. The cache must be in a state to handle that request.
 421      */
 422     void clearBlocked(BlockedCause cause)
 423     {
 424         uint8_t flag = 1 << cause;
 425         DPRINTF(Cache,"Unblocking for cause %s, causes left=%i\n",
 426                 cause, blocked);
 427         if (blocked & flag)
 428         {
 429             blocked &= ~flag;
 430             if (!isBlocked()) {
 431                 blocked_cycles[cause] += curTick - blockedCycle;
 432                 DPRINTF(Cache,"Unblocking from all causes\n");
 433                 cpuSidePort->clearBlocked();
 434             }
 435         }
 436         if (blockedSnoop & flag)
 437         {
 438             blockedSnoop &= ~flag;
 439             if (!isBlockedForSnoop()) {
 440                 memSidePort->clearBlocked();
 441             }
 442         }
 443     }
 444
 445     /**
 446      * True if the master bus should be requested.
 447      * @return True if there are outstanding requests for the master bus.
 448      */
 449     bool doMasterRequest()
 450     {
 451         return masterRequests != 0;
 452     }
 453
 454     /**
 455      * Request the master bus for the given cause and time.
 456      * @param cause The reason for the request.
 457      * @param time The time to make the request.
 458      */
 459     void setMasterRequest(RequestCause cause, Tick time)
 460     {
 461         if (!doMasterRequest() && !memSidePort->waitingOnRetry)
 462         {
 463             BaseCache::CacheEvent * reqCpu = new BaseCache::CacheEvent(memSidePort);
 464             reqCpu->schedule(time);
 465         }
 466         uint8_t flag = 1<<cause;
 467         masterRequests |= flag;
 468     }
 469
 470     /**
 471      * Clear the master bus request for the given cause.
 472      * @param cause The request reason to clear.
 473      */
 474     void clearMasterRequest(RequestCause cause)
 475     {
 476         uint8_t flag = 1<<cause;
 477         masterRequests &= ~flag;
 478     }
 479
 480     /**
 481      * Return true if the slave bus should be requested.
 482      * @return True if there are outstanding requests for the slave bus.
 483      */
 484     bool doSlaveRequest()
 485     {
 486         return slaveRequests != 0;
 487     }
 488
 489     /**
 490      * Request the slave bus for the given reason and time.
 491      * @param cause The reason for the request.
 492      * @param time The time to make the request.
 493      */
 494     void setSlaveRequest(RequestCause cause, Tick time)
 495     {
 496         if (!doSlaveRequest() && !cpuSidePort->waitingOnRetry)
 497         {
 498             BaseCache::CacheEvent * reqCpu = new BaseCache::CacheEvent(cpuSidePort);
 499             reqCpu->schedule(time);
 500         }
 501         uint8_t flag = 1<<cause;
 502         slaveRequests |= flag;
 503     }
 504
 505     /**
 506      * Clear the slave bus request for the given reason.
 507      * @param cause The request reason to clear.
 508      */
 509     void clearSlaveRequest(RequestCause cause)
 510     {
 511         uint8_t flag = 1<<cause;
 512         slaveRequests &= ~flag;
 513     }
 514
 515     /**
 516      * Send a response to the slave interface.
 517      * @param pkt The request being responded to.
 518      * @param time The time the response is ready.
 519      */
 520     void respond(Packet *pkt, Tick time)
 521     {
 522         if (pkt->needsResponse()) {
 523             CacheEvent *reqCpu = new CacheEvent(cpuSidePort, pkt);
 524             reqCpu->schedule(time);
 525         }
 526         else {
 527             if (pkt->cmd != Packet::UpgradeReq)
 528             {
 529                 delete pkt->req;
 530                 delete pkt;
 531             }
 532         }
 533     }
 534
 535     /**
 536      * Send a reponse to the slave interface and calculate miss latency.
 537      * @param pkt The request to respond to.
 538      * @param time The time the response is ready.
 539      */
 540     void respondToMiss(Packet *pkt, Tick time)
 541     {
 542         if (!pkt->req->isUncacheable()) {
 543             missLatency[pkt->cmdToIndex()][0/*pkt->req->getThreadNum()*/] += time - pkt->time;
 544         }
 545         if (pkt->needsResponse()) {
 546             CacheEvent *reqCpu = new CacheEvent(cpuSidePort, pkt);
 547             reqCpu->schedule(time);
 548         }
 549         else {
 550             if (pkt->cmd != Packet::UpgradeReq)
 551             {
 552                 delete pkt->req;
 553                 delete pkt;
 554             }
 555         }
 556     }
 557
 558     /**
 559      * Suppliess the data if cache to cache transfers are enabled.
 560      * @param pkt The bus transaction to fulfill.
 561      */
 562     void respondToSnoop(Packet *pkt, Tick time)
 563     {
 564         assert (pkt->needsResponse());
 565         CacheEvent *reqMem = new CacheEvent(memSidePort, pkt);
 566         reqMem->schedule(time);
 567     }
 568
 569     /**
 570      * Notification from master interface that a address range changed. Nothing
 571      * to do for a cache.
 572      */
 573     void rangeChange() {}
 574
 575     void getAddressRanges(AddrRangeList &resp, AddrRangeList &snoop, bool isCpuSide)
 576     {
 577         if (isCpuSide)
 578         {
 579             AddrRangeList dummy;
 580             memSidePort->getPeerAddressRanges(resp, dummy);
 581         }
 582         else
 583         {
 584             //This is where snoops get updated
 585             AddrRangeList dummy;
 586             cpuSidePort->getPeerAddressRanges(dummy, snoop);
 587             return;
 588         }
 589     }
 590 };
 591
 592 #endif //__BASE_CACHE_HH__