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28 * Authors: Erik Hallnor
33 * Declares a basic cache interface BaseCache.
36 #ifndef __BASE_CACHE_HH__
37 #define __BASE_CACHE_HH__
44 #include "base/misc.hh"
45 #include "base/statistics.hh"
46 #include "base/trace.hh"
47 #include "mem/mem_object.hh"
48 #include "mem/packet.hh"
49 #include "mem/port.hh"
50 #include "mem/request.hh"
51 #include "sim/eventq.hh"
54 * Reasons for Caches to be Blocked.
66 * Reasons for cache to request a bus.
77 * A basic cache interface. Implements some common functions for speed.
79 class BaseCache : public MemObject
81 class CachePort : public Port
86 CachePort(const std::string &_name, BaseCache *_cache, bool _isCpuSide);
89 virtual bool recvTiming(Packet *pkt);
91 virtual Tick recvAtomic(Packet *pkt);
93 virtual void recvFunctional(Packet *pkt);
95 virtual void recvStatusChange(Status status);
97 virtual void getDeviceAddressRanges(AddrRangeList &resp,
98 AddrRangeList &snoop);
100 virtual int deviceBlockSize();
102 virtual void recvRetry();
115 std::list<Packet *> drainList;
120 struct CacheEvent : public Event
122 CachePort *cachePort;
125 CacheEvent(CachePort *_cachePort);
126 CacheEvent(CachePort *_cachePort, Packet *_pkt);
128 const char *description();
132 CachePort *cpuSidePort;
133 CachePort *memSidePort;
135 bool snoopRangesSent;
138 virtual Port *getPort(const std::string &if_name, int idx = -1);
141 //To be defined in cache_impl.hh not in base class
142 virtual bool doTimingAccess(Packet *pkt, CachePort *cachePort, bool isCpuSide)
144 fatal("No implementation");
147 virtual Tick doAtomicAccess(Packet *pkt, bool isCpuSide)
149 fatal("No implementation");
152 virtual void doFunctionalAccess(Packet *pkt, bool isCpuSide)
154 fatal("No implementation");
157 void recvStatusChange(Port::Status status, bool isCpuSide)
159 if (status == Port::RangeChange){
161 cpuSidePort->sendStatusChange(Port::RangeChange);
162 if (!snoopRangesSent) {
163 snoopRangesSent = true;
164 memSidePort->sendStatusChange(Port::RangeChange);
168 memSidePort->sendStatusChange(Port::RangeChange);
173 virtual Packet *getPacket()
175 fatal("No implementation");
178 virtual Packet *getCoherencePacket()
180 fatal("No implementation");
183 virtual void sendResult(Packet* &pkt, MSHR* mshr, bool success)
186 fatal("No implementation");
190 * Bit vector of the blocking reasons for the access path.
196 * Bit vector for the blocking reasons for the snoop path.
199 uint8_t blockedSnoop;
202 * Bit vector for the outstanding requests for the master interface.
204 uint8_t masterRequests;
207 * Bit vector for the outstanding requests for the slave interface.
209 uint8_t slaveRequests;
213 /** True if this cache is connected to the CPU. */
217 /** Stores time the cache blocked for statistics. */
220 /** Block size of this cache */
223 /** The number of misses to trigger an exit event. */
229 * @addtogroup CacheStatistics
233 /** Number of hits per thread for each type of command. @sa Packet::Command */
234 Stats::Vector<> hits[NUM_MEM_CMDS];
235 /** Number of hits for demand accesses. */
236 Stats::Formula demandHits;
237 /** Number of hit for all accesses. */
238 Stats::Formula overallHits;
240 /** Number of misses per thread for each type of command. @sa Packet::Command */
241 Stats::Vector<> misses[NUM_MEM_CMDS];
242 /** Number of misses for demand accesses. */
243 Stats::Formula demandMisses;
244 /** Number of misses for all accesses. */
245 Stats::Formula overallMisses;
248 * Total number of cycles per thread/command spent waiting for a miss.
249 * Used to calculate the average miss latency.
251 Stats::Vector<> missLatency[NUM_MEM_CMDS];
252 /** Total number of cycles spent waiting for demand misses. */
253 Stats::Formula demandMissLatency;
254 /** Total number of cycles spent waiting for all misses. */
255 Stats::Formula overallMissLatency;
257 /** The number of accesses per command and thread. */
258 Stats::Formula accesses[NUM_MEM_CMDS];
259 /** The number of demand accesses. */
260 Stats::Formula demandAccesses;
261 /** The number of overall accesses. */
262 Stats::Formula overallAccesses;
264 /** The miss rate per command and thread. */
265 Stats::Formula missRate[NUM_MEM_CMDS];
266 /** The miss rate of all demand accesses. */
267 Stats::Formula demandMissRate;
268 /** The miss rate for all accesses. */
269 Stats::Formula overallMissRate;
271 /** The average miss latency per command and thread. */
272 Stats::Formula avgMissLatency[NUM_MEM_CMDS];
273 /** The average miss latency for demand misses. */
274 Stats::Formula demandAvgMissLatency;
275 /** The average miss latency for all misses. */
276 Stats::Formula overallAvgMissLatency;
278 /** The total number of cycles blocked for each blocked cause. */
279 Stats::Vector<> blocked_cycles;
280 /** The number of times this cache blocked for each blocked cause. */
281 Stats::Vector<> blocked_causes;
283 /** The average number of cycles blocked for each blocked cause. */
284 Stats::Formula avg_blocked;
286 /** The number of fast writes (WH64) performed. */
287 Stats::Scalar<> fastWrites;
289 /** The number of cache copies performed. */
290 Stats::Scalar<> cacheCopies;
297 * Register stats for this object.
299 virtual void regStats();
306 /** List of address ranges of this cache. */
307 std::vector<Range<Addr> > addrRange;
308 /** The hit latency for this cache. */
310 /** The block size of this cache. */
313 * The maximum number of misses this cache should handle before
314 * ending the simulation.
319 * Construct an instance of this parameter class.
321 Params(std::vector<Range<Addr> > addr_range,
322 int hit_latency, int _blkSize, Counter max_misses)
323 : addrRange(addr_range), hitLatency(hit_latency), blkSize(_blkSize),
324 maxMisses(max_misses)
330 * Create and initialize a basic cache object.
331 * @param name The name of this cache.
332 * @param hier_params Pointer to the HierParams object for this hierarchy
334 * @param params The parameter object for this BaseCache.
336 BaseCache(const std::string &name, Params ¶ms)
337 : MemObject(name), blocked(0), blockedSnoop(0), masterRequests(0),
338 slaveRequests(0), topLevelCache(false), blkSize(params.blkSize),
339 missCount(params.maxMisses)
341 //Start ports at null if more than one is created we should panic
344 snoopRangesSent = false;
350 * Query block size of a cache.
351 * @return The block size
353 int getBlockSize() const
359 * Returns true if this cache is connect to the CPU.
360 * @return True if this is a L1 cache.
364 return topLevelCache;
368 * Returns true if the cache is blocked for accesses.
376 * Returns true if the cache is blocked for snoops.
378 bool isBlockedForSnoop()
380 return blockedSnoop != 0;
384 * Marks the access path of the cache as blocked for the given cause. This
385 * also sets the blocked flag in the slave interface.
386 * @param cause The reason for the cache blocking.
388 void setBlocked(BlockedCause cause)
390 uint8_t flag = 1 << cause;
392 blocked_causes[cause]++;
393 blockedCycle = curTick;
395 if (!(blocked & flag)) {
396 //Wasn't already blocked for this cause
398 DPRINTF(Cache,"Blocking for cause %s\n", cause);
399 cpuSidePort->setBlocked();
404 * Marks the snoop path of the cache as blocked for the given cause. This
405 * also sets the blocked flag in the master interface.
406 * @param cause The reason to block the snoop path.
408 void setBlockedForSnoop(BlockedCause cause)
410 uint8_t flag = 1 << cause;
411 if (!(blocked & flag)) {
412 //Wasn't already blocked for this cause
413 blockedSnoop |= flag;
414 memSidePort->setBlocked();
419 * Marks the cache as unblocked for the given cause. This also clears the
420 * blocked flags in the appropriate interfaces.
421 * @param cause The newly unblocked cause.
422 * @warning Calling this function can cause a blocked request on the bus to
423 * access the cache. The cache must be in a state to handle that request.
425 void clearBlocked(BlockedCause cause)
427 uint8_t flag = 1 << cause;
428 DPRINTF(Cache,"Unblocking for cause %s, causes left=%i\n",
434 blocked_cycles[cause] += curTick - blockedCycle;
435 DPRINTF(Cache,"Unblocking from all causes\n");
436 cpuSidePort->clearBlocked();
439 if (blockedSnoop & flag)
441 blockedSnoop &= ~flag;
442 if (!isBlockedForSnoop()) {
443 memSidePort->clearBlocked();
449 * True if the master bus should be requested.
450 * @return True if there are outstanding requests for the master bus.
452 bool doMasterRequest()
454 return masterRequests != 0;
458 * Request the master bus for the given cause and time.
459 * @param cause The reason for the request.
460 * @param time The time to make the request.
462 void setMasterRequest(RequestCause cause, Tick time)
464 if (!doMasterRequest())
466 BaseCache::CacheEvent * reqCpu = new BaseCache::CacheEvent(memSidePort);
467 reqCpu->schedule(time);
469 uint8_t flag = 1<<cause;
470 masterRequests |= flag;
474 * Clear the master bus request for the given cause.
475 * @param cause The request reason to clear.
477 void clearMasterRequest(RequestCause cause)
479 uint8_t flag = 1<<cause;
480 masterRequests &= ~flag;
484 * Return true if the slave bus should be requested.
485 * @return True if there are outstanding requests for the slave bus.
487 bool doSlaveRequest()
489 return slaveRequests != 0;
493 * Request the slave bus for the given reason and time.
494 * @param cause The reason for the request.
495 * @param time The time to make the request.
497 void setSlaveRequest(RequestCause cause, Tick time)
499 uint8_t flag = 1<<cause;
500 slaveRequests |= flag;
501 assert("Implement\n" && 0);
502 // si->pktuest(time);
506 * Clear the slave bus request for the given reason.
507 * @param cause The request reason to clear.
509 void clearSlaveRequest(RequestCause cause)
511 uint8_t flag = 1<<cause;
512 slaveRequests &= ~flag;
516 * Send a response to the slave interface.
517 * @param pkt The request being responded to.
518 * @param time The time the response is ready.
520 void respond(Packet *pkt, Tick time)
522 if (pkt->needsResponse()) {
523 CacheEvent *reqCpu = new CacheEvent(cpuSidePort, pkt);
524 reqCpu->schedule(time);
529 * Send a reponse to the slave interface and calculate miss latency.
530 * @param pkt The request to respond to.
531 * @param time The time the response is ready.
533 void respondToMiss(Packet *pkt, Tick time)
535 if (!pkt->req->isUncacheable()) {
536 missLatency[pkt->cmdToIndex()][0/*pkt->req->getThreadNum()*/] += time - pkt->time;
538 if (pkt->needsResponse()) {
539 CacheEvent *reqCpu = new CacheEvent(cpuSidePort, pkt);
540 reqCpu->schedule(time);
545 * Suppliess the data if cache to cache transfers are enabled.
546 * @param pkt The bus transaction to fulfill.
548 void respondToSnoop(Packet *pkt, Tick time)
550 // assert("Implement\n" && 0);
551 // mi->respond(pkt,curTick + hitLatency);
552 assert (pkt->needsResponse());
553 CacheEvent *reqMem = new CacheEvent(memSidePort, pkt);
554 reqMem->schedule(time);
558 * Notification from master interface that a address range changed. Nothing
561 void rangeChange() {}
563 void getAddressRanges(AddrRangeList &resp, AddrRangeList &snoop, bool isCpuSide)
568 memSidePort->getPeerAddressRanges(resp, dummy);
572 //This is where snoops get updated
574 // if (!topLevelCache)
576 cpuSidePort->getPeerAddressRanges(dummy, snoop);
580 // snoop.push_back(RangeSize(0,-1));
588 #endif //__BASE_CACHE_HH__