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28 * Authors: Erik Hallnor
33 * Declares a basic cache interface BaseCache.
36 #ifndef __BASE_CACHE_HH__
37 #define __BASE_CACHE_HH__
44 #include "base/misc.hh"
45 #include "base/statistics.hh"
46 #include "base/trace.hh"
47 #include "mem/mem_object.hh"
48 #include "mem/packet.hh"
49 #include "mem/port.hh"
50 #include "mem/request.hh"
51 #include "sim/eventq.hh"
54 * Reasons for Caches to be Blocked.
66 * Reasons for cache to request a bus.
76 * A basic cache interface. Implements some common functions for speed.
78 class BaseCache : public MemObject
80 class CachePort : public Port
85 CachePort(const std::string &_name, BaseCache *_cache, bool _isCpuSide);
88 virtual bool recvTiming(Packet *pkt);
90 virtual Tick recvAtomic(Packet *pkt);
92 virtual void recvFunctional(Packet *pkt);
94 virtual void recvStatusChange(Status status);
96 virtual void getDeviceAddressRanges(AddrRangeList &resp,
97 AddrRangeList &snoop);
99 virtual int deviceBlockSize();
101 virtual void recvRetry();
114 std::list<Packet *> drainList;
117 struct CacheEvent : public Event
119 CachePort *cachePort;
122 CacheEvent(CachePort *_cachePort);
123 CacheEvent(CachePort *_cachePort, Packet *_pkt);
125 const char *description();
129 CachePort *cpuSidePort;
130 CachePort *memSidePort;
132 bool snoopRangesSent;
135 virtual Port *getPort(const std::string &if_name, int idx = -1);
138 //To be defined in cache_impl.hh not in base class
139 virtual bool doTimingAccess(Packet *pkt, CachePort *cachePort, bool isCpuSide)
141 fatal("No implementation");
144 virtual Tick doAtomicAccess(Packet *pkt, bool isCpuSide)
146 fatal("No implementation");
149 virtual void doFunctionalAccess(Packet *pkt, bool isCpuSide)
151 fatal("No implementation");
154 void recvStatusChange(Port::Status status, bool isCpuSide)
156 if (status == Port::RangeChange){
158 cpuSidePort->sendStatusChange(Port::RangeChange);
159 if (topLevelCache && !snoopRangesSent) {
160 snoopRangesSent = true;
161 memSidePort->sendStatusChange(Port::RangeChange);
165 memSidePort->sendStatusChange(Port::RangeChange);
168 else if (status == Port::SnoopSquash) {
174 virtual Packet *getPacket()
176 fatal("No implementation");
179 virtual Packet *getCoherencePacket()
181 fatal("No implementation");
184 virtual void sendResult(Packet* &pkt, bool success)
187 fatal("No implementation");
191 * Bit vector of the blocking reasons for the access path.
197 * Bit vector for the blocking reasons for the snoop path.
200 uint8_t blockedSnoop;
203 * Bit vector for the outstanding requests for the master interface.
205 uint8_t masterRequests;
208 * Bit vector for the outstanding requests for the slave interface.
210 uint8_t slaveRequests;
214 /** True if this cache is connected to the CPU. */
218 /** True if we are now in phase 2 of the snoop process. */
221 /** Stores time the cache blocked for statistics. */
224 /** Block size of this cache */
227 /** The number of misses to trigger an exit event. */
233 * @addtogroup CacheStatistics
237 /** Number of hits per thread for each type of command. @sa Packet::Command */
238 Stats::Vector<> hits[NUM_MEM_CMDS];
239 /** Number of hits for demand accesses. */
240 Stats::Formula demandHits;
241 /** Number of hit for all accesses. */
242 Stats::Formula overallHits;
244 /** Number of misses per thread for each type of command. @sa Packet::Command */
245 Stats::Vector<> misses[NUM_MEM_CMDS];
246 /** Number of misses for demand accesses. */
247 Stats::Formula demandMisses;
248 /** Number of misses for all accesses. */
249 Stats::Formula overallMisses;
252 * Total number of cycles per thread/command spent waiting for a miss.
253 * Used to calculate the average miss latency.
255 Stats::Vector<> missLatency[NUM_MEM_CMDS];
256 /** Total number of cycles spent waiting for demand misses. */
257 Stats::Formula demandMissLatency;
258 /** Total number of cycles spent waiting for all misses. */
259 Stats::Formula overallMissLatency;
261 /** The number of accesses per command and thread. */
262 Stats::Formula accesses[NUM_MEM_CMDS];
263 /** The number of demand accesses. */
264 Stats::Formula demandAccesses;
265 /** The number of overall accesses. */
266 Stats::Formula overallAccesses;
268 /** The miss rate per command and thread. */
269 Stats::Formula missRate[NUM_MEM_CMDS];
270 /** The miss rate of all demand accesses. */
271 Stats::Formula demandMissRate;
272 /** The miss rate for all accesses. */
273 Stats::Formula overallMissRate;
275 /** The average miss latency per command and thread. */
276 Stats::Formula avgMissLatency[NUM_MEM_CMDS];
277 /** The average miss latency for demand misses. */
278 Stats::Formula demandAvgMissLatency;
279 /** The average miss latency for all misses. */
280 Stats::Formula overallAvgMissLatency;
282 /** The total number of cycles blocked for each blocked cause. */
283 Stats::Vector<> blocked_cycles;
284 /** The number of times this cache blocked for each blocked cause. */
285 Stats::Vector<> blocked_causes;
287 /** The average number of cycles blocked for each blocked cause. */
288 Stats::Formula avg_blocked;
290 /** The number of fast writes (WH64) performed. */
291 Stats::Scalar<> fastWrites;
293 /** The number of cache copies performed. */
294 Stats::Scalar<> cacheCopies;
301 * Register stats for this object.
303 virtual void regStats();
310 /** List of address ranges of this cache. */
311 std::vector<Range<Addr> > addrRange;
312 /** The hit latency for this cache. */
314 /** The block size of this cache. */
317 * The maximum number of misses this cache should handle before
318 * ending the simulation.
323 * Construct an instance of this parameter class.
325 Params(std::vector<Range<Addr> > addr_range,
326 int hit_latency, int _blkSize, Counter max_misses)
327 : addrRange(addr_range), hitLatency(hit_latency), blkSize(_blkSize),
328 maxMisses(max_misses)
334 * Create and initialize a basic cache object.
335 * @param name The name of this cache.
336 * @param hier_params Pointer to the HierParams object for this hierarchy
338 * @param params The parameter object for this BaseCache.
340 BaseCache(const std::string &name, Params ¶ms)
341 : MemObject(name), blocked(0), blockedSnoop(0), masterRequests(0),
342 slaveRequests(0), topLevelCache(false), blkSize(params.blkSize),
343 missCount(params.maxMisses)
345 //Start ports at null if more than one is created we should panic
348 snoopRangesSent = false;
354 * Query block size of a cache.
355 * @return The block size
357 int getBlockSize() const
363 * Returns true if this cache is connect to the CPU.
364 * @return True if this is a L1 cache.
368 return topLevelCache;
372 * Returns true if the cache is blocked for accesses.
380 * Returns true if the cache is blocked for snoops.
382 bool isBlockedForSnoop()
384 return blockedSnoop != 0;
388 * Marks the access path of the cache as blocked for the given cause. This
389 * also sets the blocked flag in the slave interface.
390 * @param cause The reason for the cache blocking.
392 void setBlocked(BlockedCause cause)
394 uint8_t flag = 1 << cause;
396 blocked_causes[cause]++;
397 blockedCycle = curTick;
399 if (!(blocked & flag)) {
400 //Wasn't already blocked for this cause
402 DPRINTF(Cache,"Blocking for cause %s\n", cause);
403 cpuSidePort->setBlocked();
408 * Marks the snoop path of the cache as blocked for the given cause. This
409 * also sets the blocked flag in the master interface.
410 * @param cause The reason to block the snoop path.
412 void setBlockedForSnoop(BlockedCause cause)
414 uint8_t flag = 1 << cause;
415 if (!(blocked & flag)) {
416 //Wasn't already blocked for this cause
417 blockedSnoop |= flag;
418 memSidePort->setBlocked();
423 * Marks the cache as unblocked for the given cause. This also clears the
424 * blocked flags in the appropriate interfaces.
425 * @param cause The newly unblocked cause.
426 * @warning Calling this function can cause a blocked request on the bus to
427 * access the cache. The cache must be in a state to handle that request.
429 void clearBlocked(BlockedCause cause)
431 uint8_t flag = 1 << cause;
432 DPRINTF(Cache,"Unblocking for cause %s, causes left=%i\n",
438 blocked_cycles[cause] += curTick - blockedCycle;
439 DPRINTF(Cache,"Unblocking from all causes\n");
440 cpuSidePort->clearBlocked();
443 if (blockedSnoop & flag)
445 blockedSnoop &= ~flag;
446 if (!isBlockedForSnoop()) {
447 memSidePort->clearBlocked();
453 * True if the master bus should be requested.
454 * @return True if there are outstanding requests for the master bus.
456 bool doMasterRequest()
458 return masterRequests != 0;
462 * Request the master bus for the given cause and time.
463 * @param cause The reason for the request.
464 * @param time The time to make the request.
466 void setMasterRequest(RequestCause cause, Tick time)
468 if (!doMasterRequest())
470 BaseCache::CacheEvent * reqCpu = new BaseCache::CacheEvent(memSidePort);
471 reqCpu->schedule(time);
473 uint8_t flag = 1<<cause;
474 masterRequests |= flag;
478 * Clear the master bus request for the given cause.
479 * @param cause The request reason to clear.
481 void clearMasterRequest(RequestCause cause)
483 uint8_t flag = 1<<cause;
484 masterRequests &= ~flag;
488 * Return true if the slave bus should be requested.
489 * @return True if there are outstanding requests for the slave bus.
491 bool doSlaveRequest()
493 return slaveRequests != 0;
497 * Request the slave bus for the given reason and time.
498 * @param cause The reason for the request.
499 * @param time The time to make the request.
501 void setSlaveRequest(RequestCause cause, Tick time)
503 uint8_t flag = 1<<cause;
504 slaveRequests |= flag;
505 assert("Implement\n" && 0);
506 // si->pktuest(time);
510 * Clear the slave bus request for the given reason.
511 * @param cause The request reason to clear.
513 void clearSlaveRequest(RequestCause cause)
515 uint8_t flag = 1<<cause;
516 slaveRequests &= ~flag;
520 * Send a response to the slave interface.
521 * @param pkt The request being responded to.
522 * @param time The time the response is ready.
524 void respond(Packet *pkt, Tick time)
526 CacheEvent *reqCpu = new CacheEvent(cpuSidePort, pkt);
527 reqCpu->schedule(time);
531 * Send a reponse to the slave interface and calculate miss latency.
532 * @param pkt The request to respond to.
533 * @param time The time the response is ready.
535 void respondToMiss(Packet *pkt, Tick time)
537 if (!pkt->req->isUncacheable()) {
538 missLatency[pkt->cmdToIndex()][0/*pkt->req->getThreadNum()*/] += time - pkt->time;
540 CacheEvent *reqCpu = new CacheEvent(cpuSidePort, pkt);
541 reqCpu->schedule(time);
545 * Suppliess the data if cache to cache transfers are enabled.
546 * @param pkt The bus transaction to fulfill.
548 void respondToSnoop(Packet *pkt, Tick time)
550 // assert("Implement\n" && 0);
551 // mi->respond(pkt,curTick + hitLatency);
552 CacheEvent *reqMem = new CacheEvent(memSidePort, pkt);
553 reqMem->schedule(time);
557 * Notification from master interface that a address range changed. Nothing
560 void rangeChange() {}
562 void getAddressRanges(AddrRangeList &resp, AddrRangeList &snoop, bool isCpuSide)
567 memSidePort->getPeerAddressRanges(resp, dummy);
571 //This is where snoops get updated
575 cpuSidePort->getPeerAddressRanges(dummy, snoop);
579 snoop.push_back(RangeSize(0,-1));
587 #endif //__BASE_CACHE_HH__