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28 * Authors: Erik Hallnor
33 * Declares a basic cache interface BaseCache.
36 #ifndef __BASE_CACHE_HH__
37 #define __BASE_CACHE_HH__
44 #include "base/misc.hh"
45 #include "base/statistics.hh"
46 #include "base/trace.hh"
47 #include "mem/mem_object.hh"
48 #include "mem/packet.hh"
49 #include "mem/port.hh"
50 #include "mem/request.hh"
51 #include "sim/eventq.hh"
54 * Reasons for Caches to be Blocked.
66 * Reasons for cache to request a bus.
76 * A basic cache interface. Implements some common functions for speed.
78 class BaseCache : public MemObject
80 class CachePort : public Port
85 CachePort(const std::string &_name, BaseCache *_cache, bool _isCpuSide);
88 virtual bool recvTiming(Packet *pkt);
90 virtual Tick recvAtomic(Packet *pkt);
92 virtual void recvFunctional(Packet *pkt);
94 virtual void recvStatusChange(Status status);
96 virtual void getDeviceAddressRanges(AddrRangeList &resp,
97 AddrRangeList &snoop);
99 virtual int deviceBlockSize();
111 struct CacheEvent : public Event
113 CachePort *cachePort;
116 CacheEvent(CachePort *_cachePort);
117 CacheEvent(CachePort *_cachePort, Packet *_pkt);
119 const char *description();
123 CachePort *cpuSidePort;
124 CachePort *memSidePort;
127 virtual Port *getPort(const std::string &if_name, int idx = -1);
130 //To be defined in cache_impl.hh not in base class
131 virtual bool doTimingAccess(Packet *pkt, CachePort *cachePort, bool isCpuSide)
133 fatal("No implementation");
136 virtual Tick doAtomicAccess(Packet *pkt, bool isCpuSide)
138 fatal("No implementation");
141 virtual void doFunctionalAccess(Packet *pkt, bool isCpuSide)
143 fatal("No implementation");
146 virtual void recvStatusChange(Port::Status status, bool isCpuSide)
148 fatal("No implementation");
151 virtual Packet *getPacket()
153 fatal("No implementation");
156 virtual Packet *getCoherencePacket()
158 fatal("No implementation");
161 virtual void sendResult(Packet* &pkt, bool success)
164 fatal("No implementation");
168 * Bit vector of the blocking reasons for the access path.
174 * Bit vector for the blocking reasons for the snoop path.
177 uint8_t blockedSnoop;
180 * Bit vector for the outstanding requests for the master interface.
182 uint8_t masterRequests;
185 * Bit vector for the outstanding requests for the slave interface.
187 uint8_t slaveRequests;
191 /** True if this cache is connected to the CPU. */
194 /** Stores time the cache blocked for statistics. */
197 /** Block size of this cache */
200 /** The number of misses to trigger an exit event. */
206 * @addtogroup CacheStatistics
210 /** Number of hits per thread for each type of command. @sa Packet::Command */
211 Stats::Vector<> hits[NUM_MEM_CMDS];
212 /** Number of hits for demand accesses. */
213 Stats::Formula demandHits;
214 /** Number of hit for all accesses. */
215 Stats::Formula overallHits;
217 /** Number of misses per thread for each type of command. @sa Packet::Command */
218 Stats::Vector<> misses[NUM_MEM_CMDS];
219 /** Number of misses for demand accesses. */
220 Stats::Formula demandMisses;
221 /** Number of misses for all accesses. */
222 Stats::Formula overallMisses;
225 * Total number of cycles per thread/command spent waiting for a miss.
226 * Used to calculate the average miss latency.
228 Stats::Vector<> missLatency[NUM_MEM_CMDS];
229 /** Total number of cycles spent waiting for demand misses. */
230 Stats::Formula demandMissLatency;
231 /** Total number of cycles spent waiting for all misses. */
232 Stats::Formula overallMissLatency;
234 /** The number of accesses per command and thread. */
235 Stats::Formula accesses[NUM_MEM_CMDS];
236 /** The number of demand accesses. */
237 Stats::Formula demandAccesses;
238 /** The number of overall accesses. */
239 Stats::Formula overallAccesses;
241 /** The miss rate per command and thread. */
242 Stats::Formula missRate[NUM_MEM_CMDS];
243 /** The miss rate of all demand accesses. */
244 Stats::Formula demandMissRate;
245 /** The miss rate for all accesses. */
246 Stats::Formula overallMissRate;
248 /** The average miss latency per command and thread. */
249 Stats::Formula avgMissLatency[NUM_MEM_CMDS];
250 /** The average miss latency for demand misses. */
251 Stats::Formula demandAvgMissLatency;
252 /** The average miss latency for all misses. */
253 Stats::Formula overallAvgMissLatency;
255 /** The total number of cycles blocked for each blocked cause. */
256 Stats::Vector<> blocked_cycles;
257 /** The number of times this cache blocked for each blocked cause. */
258 Stats::Vector<> blocked_causes;
260 /** The average number of cycles blocked for each blocked cause. */
261 Stats::Formula avg_blocked;
263 /** The number of fast writes (WH64) performed. */
264 Stats::Scalar<> fastWrites;
266 /** The number of cache copies performed. */
267 Stats::Scalar<> cacheCopies;
274 * Register stats for this object.
276 virtual void regStats();
283 /** List of address ranges of this cache. */
284 std::vector<Range<Addr> > addrRange;
285 /** The hit latency for this cache. */
287 /** The block size of this cache. */
290 * The maximum number of misses this cache should handle before
291 * ending the simulation.
296 * Construct an instance of this parameter class.
298 Params(std::vector<Range<Addr> > addr_range,
299 int hit_latency, int _blkSize, Counter max_misses)
300 : addrRange(addr_range), hitLatency(hit_latency), blkSize(_blkSize),
301 maxMisses(max_misses)
307 * Create and initialize a basic cache object.
308 * @param name The name of this cache.
309 * @param hier_params Pointer to the HierParams object for this hierarchy
311 * @param params The parameter object for this BaseCache.
313 BaseCache(const std::string &name, Params ¶ms)
314 : MemObject(name), blocked(0), blockedSnoop(0), masterRequests(0),
315 slaveRequests(0), topLevelCache(false), blkSize(params.blkSize),
316 missCount(params.maxMisses)
318 //Start ports at null if more than one is created we should panic
324 * Query block size of a cache.
325 * @return The block size
327 int getBlockSize() const
333 * Returns true if this cache is connect to the CPU.
334 * @return True if this is a L1 cache.
338 return topLevelCache;
342 * Returns true if the cache is blocked for accesses.
350 * Returns true if the cache is blocked for snoops.
352 bool isBlockedForSnoop()
354 return blockedSnoop != 0;
358 * Marks the access path of the cache as blocked for the given cause. This
359 * also sets the blocked flag in the slave interface.
360 * @param cause The reason for the cache blocking.
362 void setBlocked(BlockedCause cause)
364 uint8_t flag = 1 << cause;
366 blocked_causes[cause]++;
367 blockedCycle = curTick;
370 DPRINTF(Cache,"Blocking for cause %s\n", cause);
371 cpuSidePort->setBlocked();
375 * Marks the snoop path of the cache as blocked for the given cause. This
376 * also sets the blocked flag in the master interface.
377 * @param cause The reason to block the snoop path.
379 void setBlockedForSnoop(BlockedCause cause)
381 uint8_t flag = 1 << cause;
382 blockedSnoop |= flag;
383 memSidePort->setBlocked();
387 * Marks the cache as unblocked for the given cause. This also clears the
388 * blocked flags in the appropriate interfaces.
389 * @param cause The newly unblocked cause.
390 * @warning Calling this function can cause a blocked request on the bus to
391 * access the cache. The cache must be in a state to handle that request.
393 void clearBlocked(BlockedCause cause)
395 uint8_t flag = 1 << cause;
397 blockedSnoop &= ~flag;
398 DPRINTF(Cache,"Unblocking for cause %s, causes left=%i\n",
401 blocked_cycles[cause] += curTick - blockedCycle;
402 DPRINTF(Cache,"Unblocking from all causes\n");
403 cpuSidePort->clearBlocked();
405 if (!isBlockedForSnoop()) {
406 memSidePort->clearBlocked();
411 * True if the master bus should be requested.
412 * @return True if there are outstanding requests for the master bus.
414 bool doMasterRequest()
416 return masterRequests != 0;
420 * Request the master bus for the given cause and time.
421 * @param cause The reason for the request.
422 * @param time The time to make the request.
424 void setMasterRequest(RequestCause cause, Tick time)
426 if (!doMasterRequest())
428 BaseCache::CacheEvent * reqCpu = new BaseCache::CacheEvent(memSidePort);
429 reqCpu->schedule(time);
431 uint8_t flag = 1<<cause;
432 masterRequests |= flag;
436 * Clear the master bus request for the given cause.
437 * @param cause The request reason to clear.
439 void clearMasterRequest(RequestCause cause)
441 uint8_t flag = 1<<cause;
442 masterRequests &= ~flag;
446 * Return true if the slave bus should be requested.
447 * @return True if there are outstanding requests for the slave bus.
449 bool doSlaveRequest()
451 return slaveRequests != 0;
455 * Request the slave bus for the given reason and time.
456 * @param cause The reason for the request.
457 * @param time The time to make the request.
459 void setSlaveRequest(RequestCause cause, Tick time)
461 uint8_t flag = 1<<cause;
462 slaveRequests |= flag;
463 assert("Implement\n" && 0);
464 // si->pktuest(time);
468 * Clear the slave bus request for the given reason.
469 * @param cause The request reason to clear.
471 void clearSlaveRequest(RequestCause cause)
473 uint8_t flag = 1<<cause;
474 slaveRequests &= ~flag;
478 * Send a response to the slave interface.
479 * @param req The request being responded to.
480 * @param time The time the response is ready.
482 void respond(Packet *pkt, Tick time)
484 pkt->makeTimingResponse();
485 pkt->result = Packet::Success;
486 CacheEvent *reqCpu = new CacheEvent(cpuSidePort, pkt);
487 reqCpu->schedule(time);
491 * Send a reponse to the slave interface and calculate miss latency.
492 * @param req The request to respond to.
493 * @param time The time the response is ready.
495 void respondToMiss(Packet *pkt, Tick time)
497 if (!pkt->req->isUncacheable()) {
498 missLatency[pkt->cmdToIndex()][pkt->req->getThreadNum()] += time - pkt->time;
500 pkt->makeTimingResponse();
501 pkt->result = Packet::Success;
502 CacheEvent *reqCpu = new CacheEvent(cpuSidePort, pkt);
503 reqCpu->schedule(time);
507 * Suppliess the data if cache to cache transfers are enabled.
508 * @param req The bus transaction to fulfill.
510 void respondToSnoop(Packet *pkt)
512 assert("Implement\n" && 0);
513 // mi->respond(pkt,curTick + hitLatency);
517 * Notification from master interface that a address range changed. Nothing
520 void rangeChange() {}
522 void getAddressRanges(AddrRangeList &resp, AddrRangeList &snoop)
524 panic("Unimplimented\n");
528 #endif //__BASE_CACHE_HH__