2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Authors: Erik Hallnor
33 * Declares a basic cache interface BaseCache.
36 #ifndef __BASE_CACHE_HH__
37 #define __BASE_CACHE_HH__
44 #include "base/misc.hh"
45 #include "base/statistics.hh"
46 #include "base/trace.hh"
47 #include "mem/mem_object.hh"
48 #include "mem/packet.hh"
49 #include "mem/port.hh"
50 #include "mem/request.hh"
51 #include "sim/eventq.hh"
54 * Reasons for Caches to be Blocked.
65 * Reasons for cache to request a bus.
76 * A basic cache interface. Implements some common functions for speed.
78 class BaseCache : public MemObject
80 class CachePort : public Port
85 CachePort(const std::string &_name, BaseCache *_cache, bool _isCpuSide);
88 virtual bool recvTiming(PacketPtr pkt);
90 virtual Tick recvAtomic(PacketPtr pkt);
92 virtual void recvFunctional(PacketPtr pkt);
94 virtual void recvStatusChange(Status status);
96 virtual void getDeviceAddressRanges(AddrRangeList &resp,
97 AddrRangeList &snoop);
99 virtual int deviceBlockSize();
101 virtual void recvRetry();
108 bool checkFunctional(PacketPtr pkt);
110 void checkAndSendFunctional(PacketPtr pkt);
112 bool canDrain() { return drainList.empty() && transmitList.empty(); }
122 std::list<PacketPtr> drainList;
124 std::list<std::pair<Tick,PacketPtr> > transmitList;
127 struct CacheEvent : public Event
129 CachePort *cachePort;
133 CacheEvent(CachePort *_cachePort, bool response);
135 const char *description();
138 public: //Made public so coherence can get at it.
139 CachePort *cpuSidePort;
141 CacheEvent *sendEvent;
142 CacheEvent *memSendEvent;
145 CachePort *memSidePort;
148 virtual Port *getPort(const std::string &if_name, int idx = -1);
151 //To be defined in cache_impl.hh not in base class
152 virtual bool doTimingAccess(PacketPtr pkt, CachePort *cachePort, bool isCpuSide)
154 fatal("No implementation");
157 virtual Tick doAtomicAccess(PacketPtr pkt, bool isCpuSide)
159 fatal("No implementation");
162 virtual void doFunctionalAccess(PacketPtr pkt, bool isCpuSide)
164 fatal("No implementation");
167 void recvStatusChange(Port::Status status, bool isCpuSide)
169 if (status == Port::RangeChange){
171 cpuSidePort->sendStatusChange(Port::RangeChange);
174 memSidePort->sendStatusChange(Port::RangeChange);
179 virtual PacketPtr getPacket()
181 fatal("No implementation");
184 virtual PacketPtr getCoherencePacket()
186 fatal("No implementation");
189 virtual void sendResult(PacketPtr &pkt, MSHR* mshr, bool success)
192 fatal("No implementation");
195 virtual void sendCoherenceResult(PacketPtr &pkt, MSHR* mshr, bool success)
198 fatal("No implementation");
202 * Bit vector of the blocking reasons for the access path.
208 * Bit vector for the blocking reasons for the snoop path.
211 uint8_t blockedSnoop;
214 * Bit vector for the outstanding requests for the master interface.
216 uint8_t masterRequests;
219 * Bit vector for the outstanding requests for the slave interface.
221 uint8_t slaveRequests;
225 /** Stores time the cache blocked for statistics. */
228 /** Block size of this cache */
231 /** The number of misses to trigger an exit event. */
234 /** The drain event. */
240 * @addtogroup CacheStatistics
244 /** Number of hits per thread for each type of command. @sa Packet::Command */
245 Stats::Vector<> hits[NUM_MEM_CMDS];
246 /** Number of hits for demand accesses. */
247 Stats::Formula demandHits;
248 /** Number of hit for all accesses. */
249 Stats::Formula overallHits;
251 /** Number of misses per thread for each type of command. @sa Packet::Command */
252 Stats::Vector<> misses[NUM_MEM_CMDS];
253 /** Number of misses for demand accesses. */
254 Stats::Formula demandMisses;
255 /** Number of misses for all accesses. */
256 Stats::Formula overallMisses;
259 * Total number of cycles per thread/command spent waiting for a miss.
260 * Used to calculate the average miss latency.
262 Stats::Vector<> missLatency[NUM_MEM_CMDS];
263 /** Total number of cycles spent waiting for demand misses. */
264 Stats::Formula demandMissLatency;
265 /** Total number of cycles spent waiting for all misses. */
266 Stats::Formula overallMissLatency;
268 /** The number of accesses per command and thread. */
269 Stats::Formula accesses[NUM_MEM_CMDS];
270 /** The number of demand accesses. */
271 Stats::Formula demandAccesses;
272 /** The number of overall accesses. */
273 Stats::Formula overallAccesses;
275 /** The miss rate per command and thread. */
276 Stats::Formula missRate[NUM_MEM_CMDS];
277 /** The miss rate of all demand accesses. */
278 Stats::Formula demandMissRate;
279 /** The miss rate for all accesses. */
280 Stats::Formula overallMissRate;
282 /** The average miss latency per command and thread. */
283 Stats::Formula avgMissLatency[NUM_MEM_CMDS];
284 /** The average miss latency for demand misses. */
285 Stats::Formula demandAvgMissLatency;
286 /** The average miss latency for all misses. */
287 Stats::Formula overallAvgMissLatency;
289 /** The total number of cycles blocked for each blocked cause. */
290 Stats::Vector<> blocked_cycles;
291 /** The number of times this cache blocked for each blocked cause. */
292 Stats::Vector<> blocked_causes;
294 /** The average number of cycles blocked for each blocked cause. */
295 Stats::Formula avg_blocked;
297 /** The number of fast writes (WH64) performed. */
298 Stats::Scalar<> fastWrites;
300 /** The number of cache copies performed. */
301 Stats::Scalar<> cacheCopies;
308 * Register stats for this object.
310 virtual void regStats();
317 /** List of address ranges of this cache. */
318 std::vector<Range<Addr> > addrRange;
319 /** The hit latency for this cache. */
321 /** The block size of this cache. */
324 * The maximum number of misses this cache should handle before
325 * ending the simulation.
330 * Construct an instance of this parameter class.
332 Params(std::vector<Range<Addr> > addr_range,
333 int hit_latency, int _blkSize, Counter max_misses)
334 : addrRange(addr_range), hitLatency(hit_latency), blkSize(_blkSize),
335 maxMisses(max_misses)
341 * Create and initialize a basic cache object.
342 * @param name The name of this cache.
343 * @param hier_params Pointer to the HierParams object for this hierarchy
345 * @param params The parameter object for this BaseCache.
347 BaseCache(const std::string &name, Params ¶ms)
348 : MemObject(name), blocked(0), blockedSnoop(0), masterRequests(0),
349 slaveRequests(0), blkSize(params.blkSize),
350 missCount(params.maxMisses), drainEvent(NULL)
352 //Start ports at null if more than one is created we should panic
366 * Query block size of a cache.
367 * @return The block size
369 int getBlockSize() const
375 * Returns true if the cache is blocked for accesses.
383 * Returns true if the cache is blocked for snoops.
385 bool isBlockedForSnoop()
387 return blockedSnoop != 0;
391 * Marks the access path of the cache as blocked for the given cause. This
392 * also sets the blocked flag in the slave interface.
393 * @param cause The reason for the cache blocking.
395 void setBlocked(BlockedCause cause)
397 uint8_t flag = 1 << cause;
399 blocked_causes[cause]++;
400 blockedCycle = curTick;
402 int old_state = blocked;
403 if (!(blocked & flag)) {
404 //Wasn't already blocked for this cause
406 DPRINTF(Cache,"Blocking for cause %s\n", cause);
408 cpuSidePort->setBlocked();
413 * Marks the snoop path of the cache as blocked for the given cause. This
414 * also sets the blocked flag in the master interface.
415 * @param cause The reason to block the snoop path.
417 void setBlockedForSnoop(BlockedCause cause)
419 uint8_t flag = 1 << cause;
420 uint8_t old_state = blockedSnoop;
421 if (!(blockedSnoop & flag)) {
422 //Wasn't already blocked for this cause
423 blockedSnoop |= flag;
425 memSidePort->setBlocked();
430 * Marks the cache as unblocked for the given cause. This also clears the
431 * blocked flags in the appropriate interfaces.
432 * @param cause The newly unblocked cause.
433 * @warning Calling this function can cause a blocked request on the bus to
434 * access the cache. The cache must be in a state to handle that request.
436 void clearBlocked(BlockedCause cause)
438 uint8_t flag = 1 << cause;
439 DPRINTF(Cache,"Unblocking for cause %s, causes left=%i\n",
445 blocked_cycles[cause] += curTick - blockedCycle;
446 DPRINTF(Cache,"Unblocking from all causes\n");
447 cpuSidePort->clearBlocked();
450 if (blockedSnoop & flag)
452 blockedSnoop &= ~flag;
453 if (!isBlockedForSnoop()) {
454 memSidePort->clearBlocked();
460 * True if the master bus should be requested.
461 * @return True if there are outstanding requests for the master bus.
463 bool doMasterRequest()
465 return masterRequests != 0;
469 * Request the master bus for the given cause and time.
470 * @param cause The reason for the request.
471 * @param time The time to make the request.
473 void setMasterRequest(RequestCause cause, Tick time)
475 if (!doMasterRequest() && !memSidePort->waitingOnRetry)
477 BaseCache::CacheEvent * reqCpu =
478 new BaseCache::CacheEvent(memSidePort, false);
479 reqCpu->schedule(time);
481 uint8_t flag = 1<<cause;
482 masterRequests |= flag;
486 * Clear the master bus request for the given cause.
487 * @param cause The request reason to clear.
489 void clearMasterRequest(RequestCause cause)
491 uint8_t flag = 1<<cause;
492 masterRequests &= ~flag;
497 * Return true if the slave bus should be requested.
498 * @return True if there are outstanding requests for the slave bus.
500 bool doSlaveRequest()
502 return slaveRequests != 0;
506 * Request the slave bus for the given reason and time.
507 * @param cause The reason for the request.
508 * @param time The time to make the request.
510 void setSlaveRequest(RequestCause cause, Tick time)
512 if (!doSlaveRequest() && !cpuSidePort->waitingOnRetry)
514 BaseCache::CacheEvent * reqCpu =
515 new BaseCache::CacheEvent(cpuSidePort, false);
516 reqCpu->schedule(time);
518 uint8_t flag = 1<<cause;
519 slaveRequests |= flag;
523 * Clear the slave bus request for the given reason.
524 * @param cause The request reason to clear.
526 void clearSlaveRequest(RequestCause cause)
528 uint8_t flag = 1<<cause;
529 slaveRequests &= ~flag;
534 * Send a response to the slave interface.
535 * @param pkt The request being responded to.
536 * @param time The time the response is ready.
538 void respond(PacketPtr pkt, Tick time)
540 assert(time >= curTick);
541 if (pkt->needsResponse()) {
542 /* CacheEvent *reqCpu = new CacheEvent(cpuSidePort, pkt);
543 reqCpu->schedule(time);
545 if (cpuSidePort->transmitList.empty()) {
546 assert(!sendEvent->scheduled());
547 sendEvent->schedule(time);
548 cpuSidePort->transmitList.push_back(std::pair<Tick,PacketPtr>
553 // something is on the list and this belongs at the end
554 if (time >= cpuSidePort->transmitList.back().first) {
555 cpuSidePort->transmitList.push_back(std::pair<Tick,PacketPtr>
559 // Something is on the list and this belongs somewhere else
560 std::list<std::pair<Tick,PacketPtr> >::iterator i =
561 cpuSidePort->transmitList.begin();
562 std::list<std::pair<Tick,PacketPtr> >::iterator end =
563 cpuSidePort->transmitList.end();
566 while (i != end && !done) {
567 if (time < i->first) {
568 if (i == cpuSidePort->transmitList.begin()) {
569 //Inserting at begining, reschedule
570 sendEvent->reschedule(time);
572 cpuSidePort->transmitList.insert(i,std::pair<Tick,PacketPtr>
580 if (pkt->cmd != Packet::UpgradeReq)
589 * Send a reponse to the slave interface and calculate miss latency.
590 * @param pkt The request to respond to.
591 * @param time The time the response is ready.
593 void respondToMiss(PacketPtr pkt, Tick time)
595 assert(time >= curTick);
596 if (!pkt->req->isUncacheable()) {
597 missLatency[pkt->cmdToIndex()][0/*pkt->req->getThreadNum()*/] +=
600 if (pkt->needsResponse()) {
601 /* CacheEvent *reqCpu = new CacheEvent(cpuSidePort, pkt);
602 reqCpu->schedule(time);
604 if (cpuSidePort->transmitList.empty()) {
605 assert(!sendEvent->scheduled());
606 sendEvent->schedule(time);
607 cpuSidePort->transmitList.push_back(std::pair<Tick,PacketPtr>
612 // something is on the list and this belongs at the end
613 if (time >= cpuSidePort->transmitList.back().first) {
614 cpuSidePort->transmitList.push_back(std::pair<Tick,PacketPtr>
618 // Something is on the list and this belongs somewhere else
619 std::list<std::pair<Tick,PacketPtr> >::iterator i =
620 cpuSidePort->transmitList.begin();
621 std::list<std::pair<Tick,PacketPtr> >::iterator end =
622 cpuSidePort->transmitList.end();
625 while (i != end && !done) {
626 if (time < i->first) {
627 if (i == cpuSidePort->transmitList.begin()) {
628 //Inserting at begining, reschedule
629 sendEvent->reschedule(time);
631 cpuSidePort->transmitList.insert(i,std::pair<Tick,PacketPtr>
639 if (pkt->cmd != Packet::UpgradeReq)
648 * Suppliess the data if cache to cache transfers are enabled.
649 * @param pkt The bus transaction to fulfill.
651 void respondToSnoop(PacketPtr pkt, Tick time)
653 assert(time >= curTick);
654 assert (pkt->needsResponse());
655 /* CacheEvent *reqMem = new CacheEvent(memSidePort, pkt);
656 reqMem->schedule(time);
658 if (memSidePort->transmitList.empty()) {
659 assert(!memSendEvent->scheduled());
660 memSendEvent->schedule(time);
661 memSidePort->transmitList.push_back(std::pair<Tick,PacketPtr>
666 // something is on the list and this belongs at the end
667 if (time >= memSidePort->transmitList.back().first) {
668 memSidePort->transmitList.push_back(std::pair<Tick,PacketPtr>
672 // Something is on the list and this belongs somewhere else
673 std::list<std::pair<Tick,PacketPtr> >::iterator i =
674 memSidePort->transmitList.begin();
675 std::list<std::pair<Tick,PacketPtr> >::iterator end =
676 memSidePort->transmitList.end();
679 while (i != end && !done) {
680 if (time < i->first) {
681 if (i == memSidePort->transmitList.begin()) {
682 //Inserting at begining, reschedule
683 memSendEvent->reschedule(time);
685 memSidePort->transmitList.insert(i,std::pair<Tick,PacketPtr>(time,pkt));
693 * Notification from master interface that a address range changed. Nothing
696 void rangeChange() {}
698 void getAddressRanges(AddrRangeList &resp, AddrRangeList &snoop, bool isCpuSide)
703 memSidePort->getPeerAddressRanges(resp, dummy);
707 //This is where snoops get updated
709 cpuSidePort->getPeerAddressRanges(dummy, snoop);
714 virtual unsigned int drain(Event *de);
718 if (drainEvent && canDrain()) {
719 drainEvent->process();
720 changeState(SimObject::Drained);
721 // Clear the drain event
728 if (doMasterRequest() || doSlaveRequest()) {
730 } else if (memSidePort && !memSidePort->canDrain()) {
732 } else if (cpuSidePort && !cpuSidePort->canDrain()) {
739 #endif //__BASE_CACHE_HH__