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28 * Authors: Erik Hallnor
33 * Declares a basic cache interface BaseCache.
36 #ifndef __BASE_CACHE_HH__
37 #define __BASE_CACHE_HH__
44 #include "base/misc.hh"
45 #include "base/statistics.hh"
46 #include "base/trace.hh"
47 #include "mem/mem_object.hh"
48 #include "mem/packet.hh"
49 #include "mem/port.hh"
50 #include "mem/request.hh"
51 #include "sim/eventq.hh"
54 * Reasons for Caches to be Blocked.
66 * Reasons for cache to request a bus.
76 * A basic cache interface. Implements some common functions for speed.
78 class BaseCache : public MemObject
80 class CachePort : public Port
85 CachePort(const std::string &_name, BaseCache *_cache, bool _isCpuSide);
88 virtual bool recvTiming(Packet *pkt);
90 virtual Tick recvAtomic(Packet *pkt);
92 virtual void recvFunctional(Packet *pkt);
94 virtual void recvStatusChange(Status status);
96 virtual void getDeviceAddressRanges(AddrRangeList &resp,
97 AddrRangeList &snoop);
99 virtual int deviceBlockSize();
101 virtual void recvRetry();
115 struct CacheEvent : public Event
117 CachePort *cachePort;
120 CacheEvent(CachePort *_cachePort);
121 CacheEvent(CachePort *_cachePort, Packet *_pkt);
123 const char *description();
127 CachePort *cpuSidePort;
128 CachePort *memSidePort;
131 virtual Port *getPort(const std::string &if_name, int idx = -1);
134 //To be defined in cache_impl.hh not in base class
135 virtual bool doTimingAccess(Packet *pkt, CachePort *cachePort, bool isCpuSide)
137 fatal("No implementation");
140 virtual Tick doAtomicAccess(Packet *pkt, bool isCpuSide)
142 fatal("No implementation");
145 virtual void doFunctionalAccess(Packet *pkt, bool isCpuSide)
147 fatal("No implementation");
150 void recvStatusChange(Port::Status status, bool isCpuSide)
152 if (status == Port::RangeChange)
156 cpuSidePort->sendStatusChange(Port::RangeChange);
160 memSidePort->sendStatusChange(Port::RangeChange);
165 virtual Packet *getPacket()
167 fatal("No implementation");
170 virtual Packet *getCoherencePacket()
172 fatal("No implementation");
175 virtual void sendResult(Packet* &pkt, bool success)
178 fatal("No implementation");
182 * Bit vector of the blocking reasons for the access path.
188 * Bit vector for the blocking reasons for the snoop path.
191 uint8_t blockedSnoop;
194 * Bit vector for the outstanding requests for the master interface.
196 uint8_t masterRequests;
199 * Bit vector for the outstanding requests for the slave interface.
201 uint8_t slaveRequests;
205 /** True if this cache is connected to the CPU. */
208 /** Stores time the cache blocked for statistics. */
211 /** Block size of this cache */
214 /** The number of misses to trigger an exit event. */
220 * @addtogroup CacheStatistics
224 /** Number of hits per thread for each type of command. @sa Packet::Command */
225 Stats::Vector<> hits[NUM_MEM_CMDS];
226 /** Number of hits for demand accesses. */
227 Stats::Formula demandHits;
228 /** Number of hit for all accesses. */
229 Stats::Formula overallHits;
231 /** Number of misses per thread for each type of command. @sa Packet::Command */
232 Stats::Vector<> misses[NUM_MEM_CMDS];
233 /** Number of misses for demand accesses. */
234 Stats::Formula demandMisses;
235 /** Number of misses for all accesses. */
236 Stats::Formula overallMisses;
239 * Total number of cycles per thread/command spent waiting for a miss.
240 * Used to calculate the average miss latency.
242 Stats::Vector<> missLatency[NUM_MEM_CMDS];
243 /** Total number of cycles spent waiting for demand misses. */
244 Stats::Formula demandMissLatency;
245 /** Total number of cycles spent waiting for all misses. */
246 Stats::Formula overallMissLatency;
248 /** The number of accesses per command and thread. */
249 Stats::Formula accesses[NUM_MEM_CMDS];
250 /** The number of demand accesses. */
251 Stats::Formula demandAccesses;
252 /** The number of overall accesses. */
253 Stats::Formula overallAccesses;
255 /** The miss rate per command and thread. */
256 Stats::Formula missRate[NUM_MEM_CMDS];
257 /** The miss rate of all demand accesses. */
258 Stats::Formula demandMissRate;
259 /** The miss rate for all accesses. */
260 Stats::Formula overallMissRate;
262 /** The average miss latency per command and thread. */
263 Stats::Formula avgMissLatency[NUM_MEM_CMDS];
264 /** The average miss latency for demand misses. */
265 Stats::Formula demandAvgMissLatency;
266 /** The average miss latency for all misses. */
267 Stats::Formula overallAvgMissLatency;
269 /** The total number of cycles blocked for each blocked cause. */
270 Stats::Vector<> blocked_cycles;
271 /** The number of times this cache blocked for each blocked cause. */
272 Stats::Vector<> blocked_causes;
274 /** The average number of cycles blocked for each blocked cause. */
275 Stats::Formula avg_blocked;
277 /** The number of fast writes (WH64) performed. */
278 Stats::Scalar<> fastWrites;
280 /** The number of cache copies performed. */
281 Stats::Scalar<> cacheCopies;
288 * Register stats for this object.
290 virtual void regStats();
297 /** List of address ranges of this cache. */
298 std::vector<Range<Addr> > addrRange;
299 /** The hit latency for this cache. */
301 /** The block size of this cache. */
304 * The maximum number of misses this cache should handle before
305 * ending the simulation.
310 * Construct an instance of this parameter class.
312 Params(std::vector<Range<Addr> > addr_range,
313 int hit_latency, int _blkSize, Counter max_misses)
314 : addrRange(addr_range), hitLatency(hit_latency), blkSize(_blkSize),
315 maxMisses(max_misses)
321 * Create and initialize a basic cache object.
322 * @param name The name of this cache.
323 * @param hier_params Pointer to the HierParams object for this hierarchy
325 * @param params The parameter object for this BaseCache.
327 BaseCache(const std::string &name, Params ¶ms)
328 : MemObject(name), blocked(0), blockedSnoop(0), masterRequests(0),
329 slaveRequests(0), topLevelCache(false), blkSize(params.blkSize),
330 missCount(params.maxMisses)
332 //Start ports at null if more than one is created we should panic
340 * Query block size of a cache.
341 * @return The block size
343 int getBlockSize() const
349 * Returns true if this cache is connect to the CPU.
350 * @return True if this is a L1 cache.
354 return topLevelCache;
358 * Returns true if the cache is blocked for accesses.
366 * Returns true if the cache is blocked for snoops.
368 bool isBlockedForSnoop()
370 return blockedSnoop != 0;
374 * Marks the access path of the cache as blocked for the given cause. This
375 * also sets the blocked flag in the slave interface.
376 * @param cause The reason for the cache blocking.
378 void setBlocked(BlockedCause cause)
380 uint8_t flag = 1 << cause;
382 blocked_causes[cause]++;
383 blockedCycle = curTick;
386 DPRINTF(Cache,"Blocking for cause %s\n", cause);
387 cpuSidePort->setBlocked();
391 * Marks the snoop path of the cache as blocked for the given cause. This
392 * also sets the blocked flag in the master interface.
393 * @param cause The reason to block the snoop path.
395 void setBlockedForSnoop(BlockedCause cause)
397 uint8_t flag = 1 << cause;
398 blockedSnoop |= flag;
399 memSidePort->setBlocked();
403 * Marks the cache as unblocked for the given cause. This also clears the
404 * blocked flags in the appropriate interfaces.
405 * @param cause The newly unblocked cause.
406 * @warning Calling this function can cause a blocked request on the bus to
407 * access the cache. The cache must be in a state to handle that request.
409 void clearBlocked(BlockedCause cause)
411 uint8_t flag = 1 << cause;
412 DPRINTF(Cache,"Unblocking for cause %s, causes left=%i\n",
418 blocked_cycles[cause] += curTick - blockedCycle;
419 DPRINTF(Cache,"Unblocking from all causes\n");
420 cpuSidePort->clearBlocked();
423 if (blockedSnoop & flag)
425 blockedSnoop &= ~flag;
426 if (!isBlockedForSnoop()) {
427 memSidePort->clearBlocked();
433 * True if the master bus should be requested.
434 * @return True if there are outstanding requests for the master bus.
436 bool doMasterRequest()
438 return masterRequests != 0;
442 * Request the master bus for the given cause and time.
443 * @param cause The reason for the request.
444 * @param time The time to make the request.
446 void setMasterRequest(RequestCause cause, Tick time)
448 if (!doMasterRequest())
450 BaseCache::CacheEvent * reqCpu = new BaseCache::CacheEvent(memSidePort);
451 reqCpu->schedule(time);
453 uint8_t flag = 1<<cause;
454 masterRequests |= flag;
458 * Clear the master bus request for the given cause.
459 * @param cause The request reason to clear.
461 void clearMasterRequest(RequestCause cause)
463 uint8_t flag = 1<<cause;
464 masterRequests &= ~flag;
468 * Return true if the slave bus should be requested.
469 * @return True if there are outstanding requests for the slave bus.
471 bool doSlaveRequest()
473 return slaveRequests != 0;
477 * Request the slave bus for the given reason and time.
478 * @param cause The reason for the request.
479 * @param time The time to make the request.
481 void setSlaveRequest(RequestCause cause, Tick time)
483 uint8_t flag = 1<<cause;
484 slaveRequests |= flag;
485 assert("Implement\n" && 0);
486 // si->pktuest(time);
490 * Clear the slave bus request for the given reason.
491 * @param cause The request reason to clear.
493 void clearSlaveRequest(RequestCause cause)
495 uint8_t flag = 1<<cause;
496 slaveRequests &= ~flag;
500 * Send a response to the slave interface.
501 * @param pkt The request being responded to.
502 * @param time The time the response is ready.
504 void respond(Packet *pkt, Tick time)
506 pkt->makeTimingResponse();
507 pkt->result = Packet::Success;
508 CacheEvent *reqCpu = new CacheEvent(cpuSidePort, pkt);
509 reqCpu->schedule(time);
513 * Send a reponse to the slave interface and calculate miss latency.
514 * @param pkt The request to respond to.
515 * @param time The time the response is ready.
517 void respondToMiss(Packet *pkt, Tick time)
519 if (!pkt->req->isUncacheable()) {
520 missLatency[pkt->cmdToIndex()][pkt->req->getThreadNum()] += time - pkt->time;
522 pkt->makeTimingResponse();
523 pkt->result = Packet::Success;
524 CacheEvent *reqCpu = new CacheEvent(cpuSidePort, pkt);
525 reqCpu->schedule(time);
529 * Suppliess the data if cache to cache transfers are enabled.
530 * @param pkt The bus transaction to fulfill.
532 void respondToSnoop(Packet *pkt)
534 assert("Implement\n" && 0);
535 // mi->respond(pkt,curTick + hitLatency);
539 * Notification from master interface that a address range changed. Nothing
542 void rangeChange() {}
544 void getAddressRanges(AddrRangeList &resp, AddrRangeList &snoop, bool isCpuSide)
549 memSidePort->getPeerAddressRanges(resp, dummy);
553 //This is where snoops get updated
559 #endif //__BASE_CACHE_HH__