src/mem/cache/base_cache.hh

   1 /*
   2  * Copyright (c) 2003-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Erik Hallnor
  29  */
  30
  31 /**
  32  * @file
  33  * Declares a basic cache interface BaseCache.
  34  */
  35
  36 #ifndef __BASE_CACHE_HH__
  37 #define __BASE_CACHE_HH__
  38
  39 #include <vector>
  40 #include <string>
  41 #include <list>
  42 #include <inttypes.h>
  43
  44 #include "base/misc.hh"
  45 #include "base/statistics.hh"
  46 #include "base/trace.hh"
  47 #include "mem/mem_object.hh"
  48 #include "mem/packet.hh"
  49 #include "mem/port.hh"
  50 #include "mem/request.hh"
  51 #include "sim/eventq.hh"
  52
  53 /**
  54  * Reasons for Caches to be Blocked.
  55  */
  56 enum BlockedCause{
  57     Blocked_NoMSHRs,
  58     Blocked_NoTargets,
  59     Blocked_NoWBBuffers,
  60     Blocked_Coherence,
  61     Blocked_Copy,
  62     NUM_BLOCKED_CAUSES
  63 };
  64
  65 /**
  66  * Reasons for cache to request a bus.
  67  */
  68 enum RequestCause{
  69     Request_MSHR,
  70     Request_WB,
  71     Request_Coherence,
  72     Request_PF
  73 };
  74
  75 class MSHR;
  76 /**
  77  * A basic cache interface. Implements some common functions for speed.
  78  */
  79 class BaseCache : public MemObject
  80 {
  81     class CachePort : public Port
  82     {
  83       public:
  84         BaseCache *cache;
  85
  86         CachePort(const std::string &_name, BaseCache *_cache, bool _isCpuSide);
  87
  88       protected:
  89         virtual bool recvTiming(Packet *pkt);
  90
  91         virtual Tick recvAtomic(Packet *pkt);
  92
  93         virtual void recvFunctional(Packet *pkt);
  94
  95         virtual void recvStatusChange(Status status);
  96
  97         virtual void getDeviceAddressRanges(AddrRangeList &resp,
  98                                             AddrRangeList &snoop);
  99
 100         virtual int deviceBlockSize();
 101
 102         virtual void recvRetry();
 103
 104       public:
 105         void setBlocked();
 106
 107         void clearBlocked();
 108
 109         bool blocked;
 110
 111         bool mustSendRetry;
 112
 113         bool isCpuSide;
 114
 115         bool waitingOnRetry;
 116
 117         std::list<Packet *> drainList;
 118
 119         Packet *cshrRetry;
 120     };
 121
 122     struct CacheEvent : public Event
 123     {
 124         CachePort *cachePort;
 125         Packet *pkt;
 126
 127         CacheEvent(CachePort *_cachePort);
 128         CacheEvent(CachePort *_cachePort, Packet *_pkt);
 129         void process();
 130         const char *description();
 131     };
 132
 133   protected:
 134     CachePort *cpuSidePort;
 135     CachePort *memSidePort;
 136
 137     bool snoopRangesSent;
 138
 139   public:
 140     virtual Port *getPort(const std::string &if_name, int idx = -1);
 141
 142   private:
 143     //To be defined in cache_impl.hh not in base class
 144     virtual bool doTimingAccess(Packet *pkt, CachePort *cachePort, bool isCpuSide)
 145     {
 146         fatal("No implementation");
 147     }
 148
 149     virtual Tick doAtomicAccess(Packet *pkt, bool isCpuSide)
 150     {
 151         fatal("No implementation");
 152     }
 153
 154     virtual void doFunctionalAccess(Packet *pkt, bool isCpuSide)
 155     {
 156         fatal("No implementation");
 157     }
 158
 159     void recvStatusChange(Port::Status status, bool isCpuSide)
 160     {
 161         if (status == Port::RangeChange){
 162             if (!isCpuSide) {
 163                 cpuSidePort->sendStatusChange(Port::RangeChange);
 164                 if (!snoopRangesSent) {
 165                     snoopRangesSent = true;
 166                     memSidePort->sendStatusChange(Port::RangeChange);
 167                 }
 168             }
 169             else {
 170                 memSidePort->sendStatusChange(Port::RangeChange);
 171             }
 172         }
 173     }
 174
 175     virtual Packet *getPacket()
 176     {
 177         fatal("No implementation");
 178     }
 179
 180     virtual Packet *getCoherencePacket()
 181     {
 182         fatal("No implementation");
 183     }
 184
 185     virtual void sendResult(Packet* &pkt, MSHR* mshr, bool success)
 186     {
 187
 188         fatal("No implementation");
 189     }
 190
 191     /**
 192      * Bit vector of the blocking reasons for the access path.
 193      * @sa #BlockedCause
 194      */
 195     uint8_t blocked;
 196
 197     /**
 198      * Bit vector for the blocking reasons for the snoop path.
 199      * @sa #BlockedCause
 200      */
 201     uint8_t blockedSnoop;
 202
 203     /**
 204      * Bit vector for the outstanding requests for the master interface.
 205      */
 206     uint8_t masterRequests;
 207
 208     /**
 209      * Bit vector for the outstanding requests for the slave interface.
 210      */
 211     uint8_t slaveRequests;
 212
 213   protected:
 214
 215     /** True if this cache is connected to the CPU. */
 216     bool topLevelCache;
 217
 218
 219     /** Stores time the cache blocked for statistics. */
 220     Tick blockedCycle;
 221
 222     /** Block size of this cache */
 223     const int blkSize;
 224
 225     /** The number of misses to trigger an exit event. */
 226     Counter missCount;
 227
 228   public:
 229     // Statistics
 230     /**
 231      * @addtogroup CacheStatistics
 232      * @{
 233      */
 234
 235     /** Number of hits per thread for each type of command. @sa Packet::Command */
 236     Stats::Vector<> hits[NUM_MEM_CMDS];
 237     /** Number of hits for demand accesses. */
 238     Stats::Formula demandHits;
 239     /** Number of hit for all accesses. */
 240     Stats::Formula overallHits;
 241
 242     /** Number of misses per thread for each type of command. @sa Packet::Command */
 243     Stats::Vector<> misses[NUM_MEM_CMDS];
 244     /** Number of misses for demand accesses. */
 245     Stats::Formula demandMisses;
 246     /** Number of misses for all accesses. */
 247     Stats::Formula overallMisses;
 248
 249     /**
 250      * Total number of cycles per thread/command spent waiting for a miss.
 251      * Used to calculate the average miss latency.
 252      */
 253     Stats::Vector<> missLatency[NUM_MEM_CMDS];
 254     /** Total number of cycles spent waiting for demand misses. */
 255     Stats::Formula demandMissLatency;
 256     /** Total number of cycles spent waiting for all misses. */
 257     Stats::Formula overallMissLatency;
 258
 259     /** The number of accesses per command and thread. */
 260     Stats::Formula accesses[NUM_MEM_CMDS];
 261     /** The number of demand accesses. */
 262     Stats::Formula demandAccesses;
 263     /** The number of overall accesses. */
 264     Stats::Formula overallAccesses;
 265
 266     /** The miss rate per command and thread. */
 267     Stats::Formula missRate[NUM_MEM_CMDS];
 268     /** The miss rate of all demand accesses. */
 269     Stats::Formula demandMissRate;
 270     /** The miss rate for all accesses. */
 271     Stats::Formula overallMissRate;
 272
 273     /** The average miss latency per command and thread. */
 274     Stats::Formula avgMissLatency[NUM_MEM_CMDS];
 275     /** The average miss latency for demand misses. */
 276     Stats::Formula demandAvgMissLatency;
 277     /** The average miss latency for all misses. */
 278     Stats::Formula overallAvgMissLatency;
 279
 280     /** The total number of cycles blocked for each blocked cause. */
 281     Stats::Vector<> blocked_cycles;
 282     /** The number of times this cache blocked for each blocked cause. */
 283     Stats::Vector<> blocked_causes;
 284
 285     /** The average number of cycles blocked for each blocked cause. */
 286     Stats::Formula avg_blocked;
 287
 288     /** The number of fast writes (WH64) performed. */
 289     Stats::Scalar<> fastWrites;
 290
 291     /** The number of cache copies performed. */
 292     Stats::Scalar<> cacheCopies;
 293
 294     /**
 295      * @}
 296      */
 297
 298     /**
 299      * Register stats for this object.
 300      */
 301     virtual void regStats();
 302
 303   public:
 304
 305     class Params
 306     {
 307       public:
 308         /** List of address ranges of this cache. */
 309         std::vector<Range<Addr> > addrRange;
 310         /** The hit latency for this cache. */
 311         int hitLatency;
 312         /** The block size of this cache. */
 313         int blkSize;
 314         /**
 315          * The maximum number of misses this cache should handle before
 316          * ending the simulation.
 317          */
 318         Counter maxMisses;
 319
 320         /**
 321          * Construct an instance of this parameter class.
 322          */
 323         Params(std::vector<Range<Addr> > addr_range,
 324                int hit_latency, int _blkSize, Counter max_misses)
 325             : addrRange(addr_range), hitLatency(hit_latency), blkSize(_blkSize),
 326               maxMisses(max_misses)
 327         {
 328         }
 329     };
 330
 331     /**
 332      * Create and initialize a basic cache object.
 333      * @param name The name of this cache.
 334      * @param hier_params Pointer to the HierParams object for this hierarchy
 335      * of this cache.
 336      * @param params The parameter object for this BaseCache.
 337      */
 338     BaseCache(const std::string &name, Params &params)
 339         : MemObject(name), blocked(0), blockedSnoop(0), masterRequests(0),
 340           slaveRequests(0), topLevelCache(false),  blkSize(params.blkSize),
 341           missCount(params.maxMisses)
 342     {
 343         //Start ports at null if more than one is created we should panic
 344         cpuSidePort = NULL;
 345         memSidePort = NULL;
 346         snoopRangesSent = false;
 347     }
 348
 349     virtual void init();
 350
 351     /**
 352      * Query block size of a cache.
 353      * @return  The block size
 354      */
 355     int getBlockSize() const
 356     {
 357         return blkSize;
 358     }
 359
 360     /**
 361      * Returns true if this cache is connect to the CPU.
 362      * @return True if this is a L1 cache.
 363      */
 364     bool isTopLevel()
 365     {
 366         return topLevelCache;
 367     }
 368
 369     /**
 370      * Returns true if the cache is blocked for accesses.
 371      */
 372     bool isBlocked()
 373     {
 374         return blocked != 0;
 375     }
 376
 377     /**
 378      * Returns true if the cache is blocked for snoops.
 379      */
 380     bool isBlockedForSnoop()
 381     {
 382         return blockedSnoop != 0;
 383     }
 384
 385     /**
 386      * Marks the access path of the cache as blocked for the given cause. This
 387      * also sets the blocked flag in the slave interface.
 388      * @param cause The reason for the cache blocking.
 389      */
 390     void setBlocked(BlockedCause cause)
 391     {
 392         uint8_t flag = 1 << cause;
 393         if (blocked == 0) {
 394             blocked_causes[cause]++;
 395             blockedCycle = curTick;
 396         }
 397         int old_state = blocked;
 398         if (!(blocked & flag)) {
 399             //Wasn't already blocked for this cause
 400             blocked |= flag;
 401             DPRINTF(Cache,"Blocking for cause %s\n", cause);
 402             if (!old_state)
 403                 cpuSidePort->setBlocked();
 404         }
 405     }
 406
 407     /**
 408      * Marks the snoop path of the cache as blocked for the given cause. This
 409      * also sets the blocked flag in the master interface.
 410      * @param cause The reason to block the snoop path.
 411      */
 412     void setBlockedForSnoop(BlockedCause cause)
 413     {
 414         uint8_t flag = 1 << cause;
 415         uint8_t old_state = blockedSnoop;
 416         if (!(blockedSnoop & flag)) {
 417             //Wasn't already blocked for this cause
 418             blockedSnoop |= flag;
 419             if (!old_state)
 420                 memSidePort->setBlocked();
 421         }
 422     }
 423
 424     /**
 425      * Marks the cache as unblocked for the given cause. This also clears the
 426      * blocked flags in the appropriate interfaces.
 427      * @param cause The newly unblocked cause.
 428      * @warning Calling this function can cause a blocked request on the bus to
 429      * access the cache. The cache must be in a state to handle that request.
 430      */
 431     void clearBlocked(BlockedCause cause)
 432     {
 433         uint8_t flag = 1 << cause;
 434         DPRINTF(Cache,"Unblocking for cause %s, causes left=%i\n",
 435                 cause, blocked);
 436         if (blocked & flag)
 437         {
 438             blocked &= ~flag;
 439             if (!isBlocked()) {
 440                 blocked_cycles[cause] += curTick - blockedCycle;
 441                 DPRINTF(Cache,"Unblocking from all causes\n");
 442                 cpuSidePort->clearBlocked();
 443             }
 444         }
 445         if (blockedSnoop & flag)
 446         {
 447             blockedSnoop &= ~flag;
 448             if (!isBlockedForSnoop()) {
 449                 memSidePort->clearBlocked();
 450             }
 451         }
 452     }
 453
 454     /**
 455      * True if the master bus should be requested.
 456      * @return True if there are outstanding requests for the master bus.
 457      */
 458     bool doMasterRequest()
 459     {
 460         return masterRequests != 0;
 461     }
 462
 463     /**
 464      * Request the master bus for the given cause and time.
 465      * @param cause The reason for the request.
 466      * @param time The time to make the request.
 467      */
 468     void setMasterRequest(RequestCause cause, Tick time)
 469     {
 470         if (!doMasterRequest() && !memSidePort->waitingOnRetry)
 471         {
 472             BaseCache::CacheEvent * reqCpu = new BaseCache::CacheEvent(memSidePort);
 473             reqCpu->schedule(time);
 474         }
 475         uint8_t flag = 1<<cause;
 476         masterRequests |= flag;
 477     }
 478
 479     /**
 480      * Clear the master bus request for the given cause.
 481      * @param cause The request reason to clear.
 482      */
 483     void clearMasterRequest(RequestCause cause)
 484     {
 485         uint8_t flag = 1<<cause;
 486         masterRequests &= ~flag;
 487     }
 488
 489     /**
 490      * Return true if the slave bus should be requested.
 491      * @return True if there are outstanding requests for the slave bus.
 492      */
 493     bool doSlaveRequest()
 494     {
 495         return slaveRequests != 0;
 496     }
 497
 498     /**
 499      * Request the slave bus for the given reason and time.
 500      * @param cause The reason for the request.
 501      * @param time The time to make the request.
 502      */
 503     void setSlaveRequest(RequestCause cause, Tick time)
 504     {
 505         uint8_t flag = 1<<cause;
 506         slaveRequests |= flag;
 507         assert("Implement\n" && 0);
 508 //      si->pktuest(time);
 509     }
 510
 511     /**
 512      * Clear the slave bus request for the given reason.
 513      * @param cause The request reason to clear.
 514      */
 515     void clearSlaveRequest(RequestCause cause)
 516     {
 517         uint8_t flag = 1<<cause;
 518         slaveRequests &= ~flag;
 519     }
 520
 521     /**
 522      * Send a response to the slave interface.
 523      * @param pkt The request being responded to.
 524      * @param time The time the response is ready.
 525      */
 526     void respond(Packet *pkt, Tick time)
 527     {
 528         if (pkt->needsResponse()) {
 529             CacheEvent *reqCpu = new CacheEvent(cpuSidePort, pkt);
 530             reqCpu->schedule(time);
 531         }
 532         else {
 533             if (pkt->cmd == Packet::Writeback) delete pkt->req;
 534             delete pkt;
 535         }
 536     }
 537
 538     /**
 539      * Send a reponse to the slave interface and calculate miss latency.
 540      * @param pkt The request to respond to.
 541      * @param time The time the response is ready.
 542      */
 543     void respondToMiss(Packet *pkt, Tick time)
 544     {
 545         if (!pkt->req->isUncacheable()) {
 546             missLatency[pkt->cmdToIndex()][0/*pkt->req->getThreadNum()*/] += time - pkt->time;
 547         }
 548         if (pkt->needsResponse()) {
 549             CacheEvent *reqCpu = new CacheEvent(cpuSidePort, pkt);
 550             reqCpu->schedule(time);
 551         }
 552         else {
 553             if (pkt->cmd == Packet::Writeback) delete pkt->req;
 554             delete pkt;
 555         }
 556     }
 557
 558     /**
 559      * Suppliess the data if cache to cache transfers are enabled.
 560      * @param pkt The bus transaction to fulfill.
 561      */
 562     void respondToSnoop(Packet *pkt, Tick time)
 563     {
 564 //        assert("Implement\n" && 0);
 565 //      mi->respond(pkt,curTick + hitLatency);
 566         assert (pkt->needsResponse());
 567         CacheEvent *reqMem = new CacheEvent(memSidePort, pkt);
 568         reqMem->schedule(time);
 569     }
 570
 571     /**
 572      * Notification from master interface that a address range changed. Nothing
 573      * to do for a cache.
 574      */
 575     void rangeChange() {}
 576
 577     void getAddressRanges(AddrRangeList &resp, AddrRangeList &snoop, bool isCpuSide)
 578     {
 579         if (isCpuSide)
 580         {
 581             AddrRangeList dummy;
 582             memSidePort->getPeerAddressRanges(resp, dummy);
 583         }
 584         else
 585         {
 586             //This is where snoops get updated
 587             AddrRangeList dummy;
 588 //            if (!topLevelCache)
 589 //            {
 590                 cpuSidePort->getPeerAddressRanges(dummy, snoop);
 591 //            }
 592 //            else
 593 //            {
 594 //                snoop.push_back(RangeSize(0,-1));
 595 //            }
 596
 597             return;
 598         }
 599     }
 600 };
 601
 602 #endif //__BASE_CACHE_HH__