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28 * Authors: Erik Hallnor
33 * Declares a basic cache interface BaseCache.
36 #ifndef __BASE_CACHE_HH__
37 #define __BASE_CACHE_HH__
44 #include "base/misc.hh"
45 #include "base/statistics.hh"
46 #include "base/trace.hh"
47 #include "mem/mem_object.hh"
48 #include "mem/packet.hh"
49 #include "mem/port.hh"
50 #include "mem/request.hh"
51 #include "sim/eventq.hh"
54 * Reasons for Caches to be Blocked.
65 * Reasons for cache to request a bus.
76 * A basic cache interface. Implements some common functions for speed.
78 class BaseCache : public MemObject
80 class CachePort : public Port
85 CachePort(const std::string &_name, BaseCache *_cache, bool _isCpuSide);
88 virtual bool recvTiming(PacketPtr pkt);
90 virtual Tick recvAtomic(PacketPtr pkt);
92 virtual void recvFunctional(PacketPtr pkt);
94 virtual void recvStatusChange(Status status);
96 virtual void getDeviceAddressRanges(AddrRangeList &resp,
97 AddrRangeList &snoop);
99 virtual int deviceBlockSize();
101 virtual void recvRetry();
108 bool canDrain() { return drainList.empty(); }
118 std::list<PacketPtr> drainList;
122 struct CacheEvent : public Event
124 CachePort *cachePort;
127 CacheEvent(CachePort *_cachePort);
128 CacheEvent(CachePort *_cachePort, PacketPtr _pkt);
130 const char *description();
133 public: //Made public so coherence can get at it.
134 CachePort *cpuSidePort;
137 CachePort *memSidePort;
139 bool snoopRangesSent;
142 virtual Port *getPort(const std::string &if_name, int idx = -1);
145 //To be defined in cache_impl.hh not in base class
146 virtual bool doTimingAccess(PacketPtr pkt, CachePort *cachePort, bool isCpuSide)
148 fatal("No implementation");
151 virtual Tick doAtomicAccess(PacketPtr pkt, bool isCpuSide)
153 fatal("No implementation");
156 virtual void doFunctionalAccess(PacketPtr pkt, bool isCpuSide)
158 fatal("No implementation");
161 void recvStatusChange(Port::Status status, bool isCpuSide)
163 if (status == Port::RangeChange){
165 cpuSidePort->sendStatusChange(Port::RangeChange);
166 if (!snoopRangesSent) {
167 snoopRangesSent = true;
168 memSidePort->sendStatusChange(Port::RangeChange);
172 memSidePort->sendStatusChange(Port::RangeChange);
177 virtual PacketPtr getPacket()
179 fatal("No implementation");
182 virtual PacketPtr getCoherencePacket()
184 fatal("No implementation");
187 virtual void sendResult(PacketPtr &pkt, MSHR* mshr, bool success)
190 fatal("No implementation");
193 virtual void sendCoherenceResult(PacketPtr &pkt, MSHR* mshr, bool success)
196 fatal("No implementation");
200 * Bit vector of the blocking reasons for the access path.
206 * Bit vector for the blocking reasons for the snoop path.
209 uint8_t blockedSnoop;
212 * Bit vector for the outstanding requests for the master interface.
214 uint8_t masterRequests;
217 * Bit vector for the outstanding requests for the slave interface.
219 uint8_t slaveRequests;
223 /** Stores time the cache blocked for statistics. */
226 /** Block size of this cache */
229 /** The number of misses to trigger an exit event. */
232 /** The drain event. */
238 * @addtogroup CacheStatistics
242 /** Number of hits per thread for each type of command. @sa Packet::Command */
243 Stats::Vector<> hits[NUM_MEM_CMDS];
244 /** Number of hits for demand accesses. */
245 Stats::Formula demandHits;
246 /** Number of hit for all accesses. */
247 Stats::Formula overallHits;
249 /** Number of misses per thread for each type of command. @sa Packet::Command */
250 Stats::Vector<> misses[NUM_MEM_CMDS];
251 /** Number of misses for demand accesses. */
252 Stats::Formula demandMisses;
253 /** Number of misses for all accesses. */
254 Stats::Formula overallMisses;
257 * Total number of cycles per thread/command spent waiting for a miss.
258 * Used to calculate the average miss latency.
260 Stats::Vector<> missLatency[NUM_MEM_CMDS];
261 /** Total number of cycles spent waiting for demand misses. */
262 Stats::Formula demandMissLatency;
263 /** Total number of cycles spent waiting for all misses. */
264 Stats::Formula overallMissLatency;
266 /** The number of accesses per command and thread. */
267 Stats::Formula accesses[NUM_MEM_CMDS];
268 /** The number of demand accesses. */
269 Stats::Formula demandAccesses;
270 /** The number of overall accesses. */
271 Stats::Formula overallAccesses;
273 /** The miss rate per command and thread. */
274 Stats::Formula missRate[NUM_MEM_CMDS];
275 /** The miss rate of all demand accesses. */
276 Stats::Formula demandMissRate;
277 /** The miss rate for all accesses. */
278 Stats::Formula overallMissRate;
280 /** The average miss latency per command and thread. */
281 Stats::Formula avgMissLatency[NUM_MEM_CMDS];
282 /** The average miss latency for demand misses. */
283 Stats::Formula demandAvgMissLatency;
284 /** The average miss latency for all misses. */
285 Stats::Formula overallAvgMissLatency;
287 /** The total number of cycles blocked for each blocked cause. */
288 Stats::Vector<> blocked_cycles;
289 /** The number of times this cache blocked for each blocked cause. */
290 Stats::Vector<> blocked_causes;
292 /** The average number of cycles blocked for each blocked cause. */
293 Stats::Formula avg_blocked;
295 /** The number of fast writes (WH64) performed. */
296 Stats::Scalar<> fastWrites;
298 /** The number of cache copies performed. */
299 Stats::Scalar<> cacheCopies;
306 * Register stats for this object.
308 virtual void regStats();
315 /** List of address ranges of this cache. */
316 std::vector<Range<Addr> > addrRange;
317 /** The hit latency for this cache. */
319 /** The block size of this cache. */
322 * The maximum number of misses this cache should handle before
323 * ending the simulation.
328 * Construct an instance of this parameter class.
330 Params(std::vector<Range<Addr> > addr_range,
331 int hit_latency, int _blkSize, Counter max_misses)
332 : addrRange(addr_range), hitLatency(hit_latency), blkSize(_blkSize),
333 maxMisses(max_misses)
339 * Create and initialize a basic cache object.
340 * @param name The name of this cache.
341 * @param hier_params Pointer to the HierParams object for this hierarchy
343 * @param params The parameter object for this BaseCache.
345 BaseCache(const std::string &name, Params ¶ms)
346 : MemObject(name), blocked(0), blockedSnoop(0), masterRequests(0),
347 slaveRequests(0), blkSize(params.blkSize),
348 missCount(params.maxMisses), drainEvent(NULL)
350 //Start ports at null if more than one is created we should panic
353 snoopRangesSent = false;
359 * Query block size of a cache.
360 * @return The block size
362 int getBlockSize() const
368 * Returns true if the cache is blocked for accesses.
376 * Returns true if the cache is blocked for snoops.
378 bool isBlockedForSnoop()
380 return blockedSnoop != 0;
384 * Marks the access path of the cache as blocked for the given cause. This
385 * also sets the blocked flag in the slave interface.
386 * @param cause The reason for the cache blocking.
388 void setBlocked(BlockedCause cause)
390 uint8_t flag = 1 << cause;
392 blocked_causes[cause]++;
393 blockedCycle = curTick;
395 int old_state = blocked;
396 if (!(blocked & flag)) {
397 //Wasn't already blocked for this cause
399 DPRINTF(Cache,"Blocking for cause %s\n", cause);
401 cpuSidePort->setBlocked();
406 * Marks the snoop path of the cache as blocked for the given cause. This
407 * also sets the blocked flag in the master interface.
408 * @param cause The reason to block the snoop path.
410 void setBlockedForSnoop(BlockedCause cause)
412 uint8_t flag = 1 << cause;
413 uint8_t old_state = blockedSnoop;
414 if (!(blockedSnoop & flag)) {
415 //Wasn't already blocked for this cause
416 blockedSnoop |= flag;
418 memSidePort->setBlocked();
423 * Marks the cache as unblocked for the given cause. This also clears the
424 * blocked flags in the appropriate interfaces.
425 * @param cause The newly unblocked cause.
426 * @warning Calling this function can cause a blocked request on the bus to
427 * access the cache. The cache must be in a state to handle that request.
429 void clearBlocked(BlockedCause cause)
431 uint8_t flag = 1 << cause;
432 DPRINTF(Cache,"Unblocking for cause %s, causes left=%i\n",
438 blocked_cycles[cause] += curTick - blockedCycle;
439 DPRINTF(Cache,"Unblocking from all causes\n");
440 cpuSidePort->clearBlocked();
443 if (blockedSnoop & flag)
445 blockedSnoop &= ~flag;
446 if (!isBlockedForSnoop()) {
447 memSidePort->clearBlocked();
453 * True if the master bus should be requested.
454 * @return True if there are outstanding requests for the master bus.
456 bool doMasterRequest()
458 return masterRequests != 0;
462 * Request the master bus for the given cause and time.
463 * @param cause The reason for the request.
464 * @param time The time to make the request.
466 void setMasterRequest(RequestCause cause, Tick time)
468 if (!doMasterRequest() && !memSidePort->waitingOnRetry)
470 BaseCache::CacheEvent * reqCpu = new BaseCache::CacheEvent(memSidePort);
471 reqCpu->schedule(time);
473 uint8_t flag = 1<<cause;
474 masterRequests |= flag;
478 * Clear the master bus request for the given cause.
479 * @param cause The request reason to clear.
481 void clearMasterRequest(RequestCause cause)
483 uint8_t flag = 1<<cause;
484 masterRequests &= ~flag;
489 * Return true if the slave bus should be requested.
490 * @return True if there are outstanding requests for the slave bus.
492 bool doSlaveRequest()
494 return slaveRequests != 0;
498 * Request the slave bus for the given reason and time.
499 * @param cause The reason for the request.
500 * @param time The time to make the request.
502 void setSlaveRequest(RequestCause cause, Tick time)
504 if (!doSlaveRequest() && !cpuSidePort->waitingOnRetry)
506 BaseCache::CacheEvent * reqCpu = new BaseCache::CacheEvent(cpuSidePort);
507 reqCpu->schedule(time);
509 uint8_t flag = 1<<cause;
510 slaveRequests |= flag;
514 * Clear the slave bus request for the given reason.
515 * @param cause The request reason to clear.
517 void clearSlaveRequest(RequestCause cause)
519 uint8_t flag = 1<<cause;
520 slaveRequests &= ~flag;
525 * Send a response to the slave interface.
526 * @param pkt The request being responded to.
527 * @param time The time the response is ready.
529 void respond(PacketPtr pkt, Tick time)
531 if (pkt->needsResponse()) {
532 CacheEvent *reqCpu = new CacheEvent(cpuSidePort, pkt);
533 reqCpu->schedule(time);
536 if (pkt->cmd != Packet::UpgradeReq)
545 * Send a reponse to the slave interface and calculate miss latency.
546 * @param pkt The request to respond to.
547 * @param time The time the response is ready.
549 void respondToMiss(PacketPtr pkt, Tick time)
551 if (!pkt->req->isUncacheable()) {
552 missLatency[pkt->cmdToIndex()][0/*pkt->req->getThreadNum()*/] += time - pkt->time;
554 if (pkt->needsResponse()) {
555 CacheEvent *reqCpu = new CacheEvent(cpuSidePort, pkt);
556 reqCpu->schedule(time);
559 if (pkt->cmd != Packet::UpgradeReq)
568 * Suppliess the data if cache to cache transfers are enabled.
569 * @param pkt The bus transaction to fulfill.
571 void respondToSnoop(PacketPtr pkt, Tick time)
573 assert (pkt->needsResponse());
574 CacheEvent *reqMem = new CacheEvent(memSidePort, pkt);
575 reqMem->schedule(time);
579 * Notification from master interface that a address range changed. Nothing
582 void rangeChange() {}
584 void getAddressRanges(AddrRangeList &resp, AddrRangeList &snoop, bool isCpuSide)
589 memSidePort->getPeerAddressRanges(resp, dummy);
593 //This is where snoops get updated
595 cpuSidePort->getPeerAddressRanges(dummy, snoop);
600 virtual unsigned int drain(Event *de);
604 if (drainEvent && canDrain()) {
605 drainEvent->process();
606 changeState(SimObject::Drained);
607 // Clear the drain event
614 if (doMasterRequest() || doSlaveRequest()) {
616 } else if (memSidePort && !memSidePort->canDrain()) {
618 } else if (cpuSidePort && !cpuSidePort->canDrain()) {
625 #endif //__BASE_CACHE_HH__