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28 * Authors: Erik Hallnor
33 * Declares a basic cache interface BaseCache.
36 #ifndef __BASE_CACHE_HH__
37 #define __BASE_CACHE_HH__
44 #include "base/misc.hh"
45 #include "base/statistics.hh"
46 #include "base/trace.hh"
47 #include "mem/mem_object.hh"
48 #include "mem/packet.hh"
49 #include "mem/port.hh"
50 #include "mem/request.hh"
51 #include "sim/eventq.hh"
54 * Reasons for Caches to be Blocked.
66 * Reasons for cache to request a bus.
77 * A basic cache interface. Implements some common functions for speed.
79 class BaseCache : public MemObject
81 class CachePort : public Port
86 CachePort(const std::string &_name, BaseCache *_cache, bool _isCpuSide);
89 virtual bool recvTiming(Packet *pkt);
91 virtual Tick recvAtomic(Packet *pkt);
93 virtual void recvFunctional(Packet *pkt);
95 virtual void recvStatusChange(Status status);
97 virtual void getDeviceAddressRanges(AddrRangeList &resp,
98 AddrRangeList &snoop);
100 virtual int deviceBlockSize();
102 virtual void recvRetry();
117 std::list<Packet *> drainList;
121 struct CacheEvent : public Event
123 CachePort *cachePort;
126 CacheEvent(CachePort *_cachePort);
127 CacheEvent(CachePort *_cachePort, Packet *_pkt);
129 const char *description();
133 CachePort *cpuSidePort;
134 CachePort *memSidePort;
136 bool snoopRangesSent;
139 virtual Port *getPort(const std::string &if_name, int idx = -1);
142 //To be defined in cache_impl.hh not in base class
143 virtual bool doTimingAccess(Packet *pkt, CachePort *cachePort, bool isCpuSide)
145 fatal("No implementation");
148 virtual Tick doAtomicAccess(Packet *pkt, bool isCpuSide)
150 fatal("No implementation");
153 virtual void doFunctionalAccess(Packet *pkt, bool isCpuSide)
155 fatal("No implementation");
158 void recvStatusChange(Port::Status status, bool isCpuSide)
160 if (status == Port::RangeChange){
162 cpuSidePort->sendStatusChange(Port::RangeChange);
163 if (!snoopRangesSent) {
164 snoopRangesSent = true;
165 memSidePort->sendStatusChange(Port::RangeChange);
169 memSidePort->sendStatusChange(Port::RangeChange);
174 virtual Packet *getPacket()
176 fatal("No implementation");
179 virtual Packet *getCoherencePacket()
181 fatal("No implementation");
184 virtual void sendResult(Packet* &pkt, MSHR* mshr, bool success)
187 fatal("No implementation");
190 virtual void sendCoherenceResult(Packet* &pkt, MSHR* mshr, bool success)
193 fatal("No implementation");
197 * Bit vector of the blocking reasons for the access path.
203 * Bit vector for the blocking reasons for the snoop path.
206 uint8_t blockedSnoop;
209 * Bit vector for the outstanding requests for the master interface.
211 uint8_t masterRequests;
214 * Bit vector for the outstanding requests for the slave interface.
216 uint8_t slaveRequests;
220 /** Stores time the cache blocked for statistics. */
223 /** Block size of this cache */
226 /** The number of misses to trigger an exit event. */
232 * @addtogroup CacheStatistics
236 /** Number of hits per thread for each type of command. @sa Packet::Command */
237 Stats::Vector<> hits[NUM_MEM_CMDS];
238 /** Number of hits for demand accesses. */
239 Stats::Formula demandHits;
240 /** Number of hit for all accesses. */
241 Stats::Formula overallHits;
243 /** Number of misses per thread for each type of command. @sa Packet::Command */
244 Stats::Vector<> misses[NUM_MEM_CMDS];
245 /** Number of misses for demand accesses. */
246 Stats::Formula demandMisses;
247 /** Number of misses for all accesses. */
248 Stats::Formula overallMisses;
251 * Total number of cycles per thread/command spent waiting for a miss.
252 * Used to calculate the average miss latency.
254 Stats::Vector<> missLatency[NUM_MEM_CMDS];
255 /** Total number of cycles spent waiting for demand misses. */
256 Stats::Formula demandMissLatency;
257 /** Total number of cycles spent waiting for all misses. */
258 Stats::Formula overallMissLatency;
260 /** The number of accesses per command and thread. */
261 Stats::Formula accesses[NUM_MEM_CMDS];
262 /** The number of demand accesses. */
263 Stats::Formula demandAccesses;
264 /** The number of overall accesses. */
265 Stats::Formula overallAccesses;
267 /** The miss rate per command and thread. */
268 Stats::Formula missRate[NUM_MEM_CMDS];
269 /** The miss rate of all demand accesses. */
270 Stats::Formula demandMissRate;
271 /** The miss rate for all accesses. */
272 Stats::Formula overallMissRate;
274 /** The average miss latency per command and thread. */
275 Stats::Formula avgMissLatency[NUM_MEM_CMDS];
276 /** The average miss latency for demand misses. */
277 Stats::Formula demandAvgMissLatency;
278 /** The average miss latency for all misses. */
279 Stats::Formula overallAvgMissLatency;
281 /** The total number of cycles blocked for each blocked cause. */
282 Stats::Vector<> blocked_cycles;
283 /** The number of times this cache blocked for each blocked cause. */
284 Stats::Vector<> blocked_causes;
286 /** The average number of cycles blocked for each blocked cause. */
287 Stats::Formula avg_blocked;
289 /** The number of fast writes (WH64) performed. */
290 Stats::Scalar<> fastWrites;
292 /** The number of cache copies performed. */
293 Stats::Scalar<> cacheCopies;
300 * Register stats for this object.
302 virtual void regStats();
309 /** List of address ranges of this cache. */
310 std::vector<Range<Addr> > addrRange;
311 /** The hit latency for this cache. */
313 /** The block size of this cache. */
316 * The maximum number of misses this cache should handle before
317 * ending the simulation.
322 * Construct an instance of this parameter class.
324 Params(std::vector<Range<Addr> > addr_range,
325 int hit_latency, int _blkSize, Counter max_misses)
326 : addrRange(addr_range), hitLatency(hit_latency), blkSize(_blkSize),
327 maxMisses(max_misses)
333 * Create and initialize a basic cache object.
334 * @param name The name of this cache.
335 * @param hier_params Pointer to the HierParams object for this hierarchy
337 * @param params The parameter object for this BaseCache.
339 BaseCache(const std::string &name, Params ¶ms)
340 : MemObject(name), blocked(0), blockedSnoop(0), masterRequests(0),
341 slaveRequests(0), blkSize(params.blkSize),
342 missCount(params.maxMisses)
344 //Start ports at null if more than one is created we should panic
347 snoopRangesSent = false;
353 * Query block size of a cache.
354 * @return The block size
356 int getBlockSize() const
362 * Returns true if the cache is blocked for accesses.
370 * Returns true if the cache is blocked for snoops.
372 bool isBlockedForSnoop()
374 return blockedSnoop != 0;
378 * Marks the access path of the cache as blocked for the given cause. This
379 * also sets the blocked flag in the slave interface.
380 * @param cause The reason for the cache blocking.
382 void setBlocked(BlockedCause cause)
384 uint8_t flag = 1 << cause;
386 blocked_causes[cause]++;
387 blockedCycle = curTick;
389 int old_state = blocked;
390 if (!(blocked & flag)) {
391 //Wasn't already blocked for this cause
393 DPRINTF(Cache,"Blocking for cause %s\n", cause);
395 cpuSidePort->setBlocked();
400 * Marks the snoop path of the cache as blocked for the given cause. This
401 * also sets the blocked flag in the master interface.
402 * @param cause The reason to block the snoop path.
404 void setBlockedForSnoop(BlockedCause cause)
406 uint8_t flag = 1 << cause;
407 uint8_t old_state = blockedSnoop;
408 if (!(blockedSnoop & flag)) {
409 //Wasn't already blocked for this cause
410 blockedSnoop |= flag;
412 memSidePort->setBlocked();
417 * Marks the cache as unblocked for the given cause. This also clears the
418 * blocked flags in the appropriate interfaces.
419 * @param cause The newly unblocked cause.
420 * @warning Calling this function can cause a blocked request on the bus to
421 * access the cache. The cache must be in a state to handle that request.
423 void clearBlocked(BlockedCause cause)
425 uint8_t flag = 1 << cause;
426 DPRINTF(Cache,"Unblocking for cause %s, causes left=%i\n",
432 blocked_cycles[cause] += curTick - blockedCycle;
433 DPRINTF(Cache,"Unblocking from all causes\n");
434 cpuSidePort->clearBlocked();
437 if (blockedSnoop & flag)
439 blockedSnoop &= ~flag;
440 if (!isBlockedForSnoop()) {
441 memSidePort->clearBlocked();
447 * True if the master bus should be requested.
448 * @return True if there are outstanding requests for the master bus.
450 bool doMasterRequest()
452 return masterRequests != 0;
456 * Request the master bus for the given cause and time.
457 * @param cause The reason for the request.
458 * @param time The time to make the request.
460 void setMasterRequest(RequestCause cause, Tick time)
462 if (!doMasterRequest() && !memSidePort->waitingOnRetry)
464 BaseCache::CacheEvent * reqCpu = new BaseCache::CacheEvent(memSidePort);
465 reqCpu->schedule(time);
467 uint8_t flag = 1<<cause;
468 masterRequests |= flag;
472 * Clear the master bus request for the given cause.
473 * @param cause The request reason to clear.
475 void clearMasterRequest(RequestCause cause)
477 uint8_t flag = 1<<cause;
478 masterRequests &= ~flag;
482 * Return true if the slave bus should be requested.
483 * @return True if there are outstanding requests for the slave bus.
485 bool doSlaveRequest()
487 return slaveRequests != 0;
491 * Request the slave bus for the given reason and time.
492 * @param cause The reason for the request.
493 * @param time The time to make the request.
495 void setSlaveRequest(RequestCause cause, Tick time)
497 if (!doSlaveRequest() && !cpuSidePort->waitingOnRetry)
499 BaseCache::CacheEvent * reqCpu = new BaseCache::CacheEvent(cpuSidePort);
500 reqCpu->schedule(time);
502 uint8_t flag = 1<<cause;
503 slaveRequests |= flag;
507 * Clear the slave bus request for the given reason.
508 * @param cause The request reason to clear.
510 void clearSlaveRequest(RequestCause cause)
512 uint8_t flag = 1<<cause;
513 slaveRequests &= ~flag;
517 * Send a response to the slave interface.
518 * @param pkt The request being responded to.
519 * @param time The time the response is ready.
521 void respond(Packet *pkt, Tick time)
523 if (pkt->needsResponse()) {
524 CacheEvent *reqCpu = new CacheEvent(cpuSidePort, pkt);
525 reqCpu->schedule(time);
528 if (pkt->cmd == Packet::Writeback) delete pkt->req;
534 * Send a reponse to the slave interface and calculate miss latency.
535 * @param pkt The request to respond to.
536 * @param time The time the response is ready.
538 void respondToMiss(Packet *pkt, Tick time)
540 if (!pkt->req->isUncacheable()) {
541 missLatency[pkt->cmdToIndex()][0/*pkt->req->getThreadNum()*/] += time - pkt->time;
543 if (pkt->needsResponse()) {
544 CacheEvent *reqCpu = new CacheEvent(cpuSidePort, pkt);
545 reqCpu->schedule(time);
548 if (pkt->cmd == Packet::Writeback) delete pkt->req;
554 * Suppliess the data if cache to cache transfers are enabled.
555 * @param pkt The bus transaction to fulfill.
557 void respondToSnoop(Packet *pkt, Tick time)
559 assert (pkt->needsResponse());
560 CacheEvent *reqMem = new CacheEvent(memSidePort, pkt);
561 reqMem->schedule(time);
565 * Notification from master interface that a address range changed. Nothing
568 void rangeChange() {}
570 void getAddressRanges(AddrRangeList &resp, AddrRangeList &snoop, bool isCpuSide)
575 memSidePort->getPeerAddressRanges(resp, dummy);
579 //This is where snoops get updated
581 cpuSidePort->getPeerAddressRanges(dummy, snoop);
587 #endif //__BASE_CACHE_HH__