src/mem/cache/blk.hh

   1 /*
   2  * Copyright (c) 2012-2015 ARM Limited
   3  * All rights reserved.
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2003-2005 The Regents of The University of Michigan
  15  * All rights reserved.
  16  *
  17  * Redistribution and use in source and binary forms, with or without
  18  * modification, are permitted provided that the following conditions are
  19  * met: redistributions of source code must retain the above copyright
  20  * notice, this list of conditions and the following disclaimer;
  21  * redistributions in binary form must reproduce the above copyright
  22  * notice, this list of conditions and the following disclaimer in the
  23  * documentation and/or other materials provided with the distribution;
  24  * neither the name of the copyright holders nor the names of its
  25  * contributors may be used to endorse or promote products derived from
  26  * this software without specific prior written permission.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  33  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  34  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  35  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  36  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  37  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39  *
  40  * Authors: Erik Hallnor
  41  *          Andreas Sandberg
  42  */
  43
  44 /** @file
  45  * Definitions of a simple cache block class.
  46  */
  47
  48 #ifndef __MEM_CACHE_BLK_HH__
  49 #define __MEM_CACHE_BLK_HH__
  50
  51 #include <list>
  52
  53 #include "base/printable.hh"
  54 #include "mem/packet.hh"
  55 #include "mem/request.hh"
  56
  57 /**
  58  * Cache block status bit assignments
  59  */
  60 enum CacheBlkStatusBits : unsigned {
  61     /** valid, readable */
  62     BlkValid =          0x01,
  63     /** write permission */
  64     BlkWritable =       0x02,
  65     /** read permission (yes, block can be valid but not readable) */
  66     BlkReadable =       0x04,
  67     /** dirty (modified) */
  68     BlkDirty =          0x08,
  69     /** block was a hardware prefetch yet unaccessed*/
  70     BlkHWPrefetched =   0x20,
  71     /** block holds data from the secure memory space */
  72     BlkSecure =         0x40,
  73 };
  74
  75 /**
  76  * A Basic Cache block.
  77  * Contains the tag, status, and a pointer to data.
  78  */
  79 class CacheBlk
  80 {
  81   public:
  82     /** Task Id associated with this block */
  83     uint32_t task_id;
  84
  85     /** The address space ID of this block. */
  86     int asid;
  87     /** Data block tag value. */
  88     Addr tag;
  89     /**
  90      * Contains a copy of the data in this block for easy access. This is used
  91      * for efficient execution when the data could be actually stored in
  92      * another format (COW, compressed, sub-blocked, etc). In all cases the
  93      * data stored here should be kept consistant with the actual data
  94      * referenced by this block.
  95      */
  96     uint8_t *data;
  97     /** the number of bytes stored in this block. */
  98     unsigned size;
  99
 100     /** block state: OR of CacheBlkStatusBit */
 101     typedef unsigned State;
 102
 103     /** The current status of this block. @sa CacheBlockStatusBits */
 104     State status;
 105
 106     /** Which curTick() will this block be accessable */
 107     Tick whenReady;
 108
 109     /**
 110      * The set and way this block belongs to.
 111      * @todo Move this into subclasses when we fix CacheTags to use them.
 112      */
 113     int set, way;
 114
 115     /** whether this block has been touched */
 116     bool isTouched;
 117
 118     /** Number of references to this block since it was brought in. */
 119     unsigned refCount;
 120
 121     /** holds the source requestor ID for this block. */
 122     int srcMasterId;
 123
 124     Tick tickInserted;
 125
 126   protected:
 127     /**
 128      * Represents that the indicated thread context has a "lock" on
 129      * the block, in the LL/SC sense.
 130      */
 131     class Lock {
 132       public:
 133         ContextID contextId;     // locking context
 134         Addr lowAddr;      // low address of lock range
 135         Addr highAddr;     // high address of lock range
 136
 137         // check for matching execution context
 138         bool matchesContext(const RequestPtr req) const
 139         {
 140             Addr req_low = req->getPaddr();
 141             Addr req_high = req_low + req->getSize() -1;
 142             return (contextId == req->contextId()) &&
 143                    (req_low >= lowAddr) && (req_high <= highAddr);
 144         }
 145
 146         bool overlapping(const RequestPtr req) const
 147         {
 148             Addr req_low = req->getPaddr();
 149             Addr req_high = req_low + req->getSize() - 1;
 150
 151             return (req_low <= highAddr) && (req_high >= lowAddr);
 152         }
 153
 154         Lock(const RequestPtr req)
 155             : contextId(req->contextId()),
 156               lowAddr(req->getPaddr()),
 157               highAddr(lowAddr + req->getSize() - 1)
 158         {
 159         }
 160     };
 161
 162     /** List of thread contexts that have performed a load-locked (LL)
 163      * on the block since the last store. */
 164     std::list<Lock> lockList;
 165
 166   public:
 167
 168     CacheBlk()
 169         : task_id(ContextSwitchTaskId::Unknown),
 170           asid(-1), tag(0), data(0) ,size(0), status(0), whenReady(0),
 171           set(-1), way(-1), isTouched(false), refCount(0),
 172           srcMasterId(Request::invldMasterId),
 173           tickInserted(0)
 174     {}
 175
 176     CacheBlk(const CacheBlk&) = delete;
 177     CacheBlk& operator=(const CacheBlk&) = delete;
 178
 179     /**
 180      * Checks the write permissions of this block.
 181      * @return True if the block is writable.
 182      */
 183     bool isWritable() const
 184     {
 185         const State needed_bits = BlkWritable | BlkValid;
 186         return (status & needed_bits) == needed_bits;
 187     }
 188
 189     /**
 190      * Checks the read permissions of this block.  Note that a block
 191      * can be valid but not readable if there is an outstanding write
 192      * upgrade miss.
 193      * @return True if the block is readable.
 194      */
 195     bool isReadable() const
 196     {
 197         const State needed_bits = BlkReadable | BlkValid;
 198         return (status & needed_bits) == needed_bits;
 199     }
 200
 201     /**
 202      * Checks that a block is valid.
 203      * @return True if the block is valid.
 204      */
 205     bool isValid() const
 206     {
 207         return (status & BlkValid) != 0;
 208     }
 209
 210     /**
 211      * Invalidate the block and clear all state.
 212      */
 213     void invalidate()
 214     {
 215         status = 0;
 216         isTouched = false;
 217         clearLoadLocks();
 218     }
 219
 220     /**
 221      * Check to see if a block has been written.
 222      * @return True if the block is dirty.
 223      */
 224     bool isDirty() const
 225     {
 226         return (status & BlkDirty) != 0;
 227     }
 228
 229     /**
 230      * Check if this block was the result of a hardware prefetch, yet to
 231      * be touched.
 232      * @return True if the block was a hardware prefetch, unaccesed.
 233      */
 234     bool wasPrefetched() const
 235     {
 236         return (status & BlkHWPrefetched) != 0;
 237     }
 238
 239     /**
 240      * Check if this block holds data from the secure memory space.
 241      * @return True if the block holds data from the secure memory space.
 242      */
 243     bool isSecure() const
 244     {
 245         return (status & BlkSecure) != 0;
 246     }
 247
 248     /**
 249      * Track the fact that a local locked was issued to the block.  If
 250      * multiple LLs get issued from the same context we could have
 251      * redundant records on the list, but that's OK, as they'll all
 252      * get blown away at the next store.
 253      */
 254     void trackLoadLocked(PacketPtr pkt)
 255     {
 256         assert(pkt->isLLSC());
 257         lockList.emplace_front(pkt->req);
 258     }
 259
 260     /**
 261      * Clear the list of valid load locks.  Should be called whenever
 262      * block is written to or invalidated.
 263      */
 264     void clearLoadLocks(RequestPtr req = nullptr)
 265     {
 266         if (!req) {
 267             // No request, invaldate all locks to this line
 268             lockList.clear();
 269         } else {
 270             // Only invalidate locks that overlap with this request
 271             auto lock_itr = lockList.begin();
 272             while (lock_itr != lockList.end()) {
 273                 if (lock_itr->overlapping(req)) {
 274                     lock_itr = lockList.erase(lock_itr);
 275                 } else {
 276                     ++lock_itr;
 277                 }
 278             }
 279         }
 280     }
 281
 282     /**
 283      * Pretty-print a tag, and interpret state bits to readable form
 284      * including mapping to a MOESI stat.
 285      *
 286      * @return string with basic state information
 287      */
 288     std::string print() const
 289     {
 290         /**
 291          *  state       M   O   E   S   I
 292          *  writable    1   0   1   0   0
 293          *  dirty       1   1   0   0   0
 294          *  valid       1   1   1   1   0
 295          *
 296          *  state   writable    dirty   valid
 297          *  M       1           1       1
 298          *  O       0           1       1
 299          *  E       1           0       1
 300          *  S       0           0       1
 301          *  I       0           0       0
 302          **/
 303         unsigned state = isWritable() << 2 | isDirty() << 1 | isValid();
 304         char s = '?';
 305         switch (state) {
 306           case 0b111: s = 'M'; break;
 307           case 0b011: s = 'O'; break;
 308           case 0b101: s = 'E'; break;
 309           case 0b001: s = 'S'; break;
 310           case 0b000: s = 'I'; break;
 311           default:    s = 'T'; break; // @TODO add other types
 312         }
 313         return csprintf("state: %x (%c) valid: %d writable: %d readable: %d "
 314                         "dirty: %d tag: %x", status, s, isValid(),
 315                         isWritable(), isReadable(), isDirty(), tag);
 316     }
 317
 318     /**
 319      * Handle interaction of load-locked operations and stores.
 320      * @return True if write should proceed, false otherwise.  Returns
 321      * false only in the case of a failed store conditional.
 322      */
 323     bool checkWrite(PacketPtr pkt)
 324     {
 325         // common case
 326         if (!pkt->isLLSC() && lockList.empty())
 327             return true;
 328
 329         RequestPtr req = pkt->req;
 330
 331         if (pkt->isLLSC()) {
 332             // it's a store conditional... have to check for matching
 333             // load locked.
 334             bool success = false;
 335
 336             for (const auto& l : lockList) {
 337                 if (l.matchesContext(req)) {
 338                     // it's a store conditional, and as far as the memory
 339                     // system can tell, the requesting context's lock is
 340                     // still valid.
 341                     success = true;
 342                     break;
 343                 }
 344             }
 345
 346             req->setExtraData(success ? 1 : 0);
 347             clearLoadLocks(req);
 348             return success;
 349         } else {
 350             // for *all* stores (conditional or otherwise) we have to
 351             // clear the list of load-locks as they're all invalid now.
 352             clearLoadLocks(req);
 353             return true;
 354         }
 355     }
 356 };
 357
 358 /**
 359  * Simple class to provide virtual print() method on cache blocks
 360  * without allocating a vtable pointer for every single cache block.
 361  * Just wrap the CacheBlk object in an instance of this before passing
 362  * to a function that requires a Printable object.
 363  */
 364 class CacheBlkPrintWrapper : public Printable
 365 {
 366     CacheBlk *blk;
 367   public:
 368     CacheBlkPrintWrapper(CacheBlk *_blk) : blk(_blk) {}
 369     virtual ~CacheBlkPrintWrapper() {}
 370     void print(std::ostream &o, int verbosity = 0,
 371                const std::string &prefix = "") const;
 372 };
 373
 374 /**
 375  * Base class for cache block visitor, operating on the cache block
 376  * base class (later subclassed for the various tag classes). This
 377  * visitor class is used as part of the forEachBlk interface in the
 378  * tag classes.
 379  */
 380 class CacheBlkVisitor
 381 {
 382   public:
 383
 384     CacheBlkVisitor() {}
 385     virtual ~CacheBlkVisitor() {}
 386
 387     virtual bool operator()(CacheBlk &blk) = 0;
 388 };
 389
 390 #endif //__MEM_CACHE_BLK_HH__