src/mem/cache/blk.hh

   1 /*
   2  * Copyright (c) 2003-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Erik Hallnor
  29  */
  30
  31 /** @file
  32  * Definitions of a simple cache block class.
  33  */
  34
  35 #ifndef __CACHE_BLK_HH__
  36 #define __CACHE_BLK_HH__
  37
  38 #include <list>
  39
  40 #include "base/printable.hh"
  41 #include "sim/core.hh"          // for Tick
  42 #include "arch/isa_traits.hh"   // for Addr
  43 #include "mem/packet.hh"
  44 #include "mem/request.hh"
  45
  46 /**
  47  * Cache block status bit assignments
  48  */
  49 enum CacheBlkStatusBits {
  50     /** valid, readable */
  51     BlkValid =          0x01,
  52     /** write permission */
  53     BlkWritable =       0x02,
  54     /** read permission (yes, block can be valid but not readable) */
  55     BlkReadable =       0x04,
  56     /** dirty (modified) */
  57     BlkDirty =          0x08,
  58     /** block was referenced */
  59     BlkReferenced =     0x10,
  60     /** block was a hardware prefetch yet unaccessed*/
  61     BlkHWPrefetched =   0x20
  62 };
  63
  64 /**
  65  * A Basic Cache block.
  66  * Contains the tag, status, and a pointer to data.
  67  */
  68 class CacheBlk
  69 {
  70   public:
  71     /** The address space ID of this block. */
  72     int asid;
  73     /** Data block tag value. */
  74     Addr tag;
  75     /**
  76      * Contains a copy of the data in this block for easy access. This is used
  77      * for efficient execution when the data could be actually stored in
  78      * another format (COW, compressed, sub-blocked, etc). In all cases the
  79      * data stored here should be kept consistant with the actual data
  80      * referenced by this block.
  81      */
  82     uint8_t *data;
  83     /** the number of bytes stored in this block. */
  84     int size;
  85
  86     /** block state: OR of CacheBlkStatusBit */
  87     typedef unsigned State;
  88
  89     /** The current status of this block. @sa CacheBlockStatusBits */
  90     State status;
  91
  92     /** Which curTick will this block be accessable */
  93     Tick whenReady;
  94
  95     /**
  96      * The set this block belongs to.
  97      * @todo Move this into subclasses when we fix CacheTags to use them.
  98      */
  99     int set;
 100
 101     /** whether this block has been touched */
 102     bool isTouched;
 103
 104     /** Number of references to this block since it was brought in. */
 105     int refCount;
 106
 107   protected:
 108     /**
 109      * Represents that the indicated thread context has a "lock" on
 110      * the block, in the LL/SC sense.
 111      */
 112     class Lock {
 113       public:
 114         int contextId;     // locking context
 115
 116         // check for matching execution context
 117         bool matchesContext(Request *req)
 118         {
 119             return (contextId == req->contextId());
 120         }
 121
 122         Lock(Request *req)
 123             : contextId(req->contextId())
 124         {
 125         }
 126     };
 127
 128     /** List of thread contexts that have performed a load-locked (LL)
 129      * on the block since the last store. */
 130     std::list<Lock> lockList;
 131
 132   public:
 133
 134     CacheBlk()
 135         : asid(-1), tag(0), data(0) ,size(0), status(0), whenReady(0),
 136           set(-1), isTouched(false), refCount(0)
 137     {}
 138
 139     /**
 140      * Copy the state of the given block into this one.
 141      * @param rhs The block to copy.
 142      * @return a const reference to this block.
 143      */
 144     const CacheBlk& operator=(const CacheBlk& rhs)
 145     {
 146         asid = rhs.asid;
 147         tag = rhs.tag;
 148         data = rhs.data;
 149         size = rhs.size;
 150         status = rhs.status;
 151         whenReady = rhs.whenReady;
 152         set = rhs.set;
 153         refCount = rhs.refCount;
 154         return *this;
 155     }
 156
 157     /**
 158      * Checks the write permissions of this block.
 159      * @return True if the block is writable.
 160      */
 161     bool isWritable() const
 162     {
 163         const State needed_bits = BlkWritable | BlkValid;
 164         return (status & needed_bits) == needed_bits;
 165     }
 166
 167     /**
 168      * Checks the read permissions of this block.  Note that a block
 169      * can be valid but not readable if there is an outstanding write
 170      * upgrade miss.
 171      * @return True if the block is readable.
 172      */
 173     bool isReadable() const
 174     {
 175         const State needed_bits = BlkReadable | BlkValid;
 176         return (status & needed_bits) == needed_bits;
 177     }
 178
 179     /**
 180      * Checks that a block is valid.
 181      * @return True if the block is valid.
 182      */
 183     bool isValid() const
 184     {
 185         return (status & BlkValid) != 0;
 186     }
 187
 188     /**
 189      * Check to see if a block has been written.
 190      * @return True if the block is dirty.
 191      */
 192     bool isDirty() const
 193     {
 194         return (status & BlkDirty) != 0;
 195     }
 196
 197     /**
 198      * Check if this block has been referenced.
 199      * @return True if the block has been referenced.
 200      */
 201     bool isReferenced() const
 202     {
 203         return (status & BlkReferenced) != 0;
 204     }
 205
 206     /**
 207      * Check if this block was the result of a hardware prefetch, yet to
 208      * be touched.
 209      * @return True if the block was a hardware prefetch, unaccesed.
 210      */
 211     bool wasPrefetched() const
 212     {
 213         return (status & BlkHWPrefetched) != 0;
 214     }
 215
 216     /**
 217      * Track the fact that a local locked was issued to the block.  If
 218      * multiple LLs get issued from the same context we could have
 219      * redundant records on the list, but that's OK, as they'll all
 220      * get blown away at the next store.
 221      */
 222     void trackLoadLocked(PacketPtr pkt)
 223     {
 224         assert(pkt->isLLSC());
 225         lockList.push_front(Lock(pkt->req));
 226     }
 227
 228     /**
 229      * Clear the list of valid load locks.  Should be called whenever
 230      * block is written to or invalidated.
 231      */
 232     void clearLoadLocks() { lockList.clear(); }
 233
 234     /**
 235      * Handle interaction of load-locked operations and stores.
 236      * @return True if write should proceed, false otherwise.  Returns
 237      * false only in the case of a failed store conditional.
 238      */
 239     bool checkWrite(PacketPtr pkt)
 240     {
 241         Request *req = pkt->req;
 242         if (pkt->isLLSC()) {
 243             // it's a store conditional... have to check for matching
 244             // load locked.
 245             bool success = false;
 246
 247             for (std::list<Lock>::iterator i = lockList.begin();
 248                  i != lockList.end(); ++i)
 249             {
 250                 if (i->matchesContext(req)) {
 251                     // it's a store conditional, and as far as the memory
 252                     // system can tell, the requesting context's lock is
 253                     // still valid.
 254                     success = true;
 255                     break;
 256                 }
 257             }
 258
 259             req->setExtraData(success ? 1 : 0);
 260             clearLoadLocks();
 261             return success;
 262         } else {
 263             // for *all* stores (conditional or otherwise) we have to
 264             // clear the list of load-locks as they're all invalid now.
 265             clearLoadLocks();
 266             return true;
 267         }
 268     }
 269 };
 270
 271 /**
 272  * Simple class to provide virtual print() method on cache blocks
 273  * without allocating a vtable pointer for every single cache block.
 274  * Just wrap the CacheBlk object in an instance of this before passing
 275  * to a function that requires a Printable object.
 276  */
 277 class CacheBlkPrintWrapper : public Printable
 278 {
 279     CacheBlk *blk;
 280   public:
 281     CacheBlkPrintWrapper(CacheBlk *_blk) : blk(_blk) {}
 282     virtual ~CacheBlkPrintWrapper() {}
 283     void print(std::ostream &o, int verbosity = 0,
 284                const std::string &prefix = "") const;
 285 };
 286
 287
 288
 289 #endif //__CACHE_BLK_HH__